fix(fvp): workaround when PCIe 2 region is not present in DTB
This patch applies a workaround to the RMM manifest when the DT
does not specify the 2nd PCIe region. As per FVP RevC memory map [1],
there are 2 PCIe regions but the upstream FVP DT sourced from
kernel.org does not have this region specified. Temporarily
workaround this issue in FVP platform layer till the upstream DT is
fixed.
Note that the DT in `fdts` folder of TF-A source tree already has the
2 regions specified.
[1] https://developer.arm.com/documentation/100966/1101-00/Programming-Reference-for-Base-FVPs/Base---memory
Change-Id: If220e2dbeff00a1bf6eccadbb0ebb661b9c5e529
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 9d0463d..f8ad966 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -773,8 +773,8 @@
/* Set number of consoles */
num_consoles = FVP_RMM_CONSOLE_COUNT;
- /* Set number of device non-coherent address ranges based on DT */
- num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+ /* Set number of device non-coherent address ranges for FVP RevC */
+ num_ncoh_regions = 2;
/* Set number of SMMUs */
num_smmus = FVP_RMM_SMMU_COUNT;
@@ -907,6 +907,11 @@
(void)memset((void *)ncoh_region_ptr, 0,
sizeof(struct memory_bank) * num_ncoh_regions);
+ /* Set number of device non-coherent address ranges based on DT */
+ num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+ /* At least 1 PCIe region need to be described in DT */
+ assert((num_ncoh_regions > 0) && (num_ncoh_regions <= 2));
+
for (unsigned long i = 0UL; i < num_ncoh_regions; i++) {
ncoh_region_ptr[i].base =
FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base);
@@ -914,6 +919,17 @@
FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size);
}
+ /*
+ * Workaround if the DT does not specify the 2nd PCIe region. This code can be
+ * removed when upstream DT is updated to have 2nd PCIe region.
+ */
+ if (num_ncoh_regions == 1) {
+ num_ncoh_regions++;
+ /* Add 3GB of 2nd PCIe region */
+ ncoh_region_ptr[1].base = 0x4000000000;
+ ncoh_region_ptr[1].size = 0xc0000000;
+ }
+
/* Update checksum */
checksum += checksum_calc((uint64_t *)ncoh_region_ptr,
sizeof(struct memory_bank) * num_ncoh_regions);