fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk
index 546bc2e..b42253b 100644
--- a/plat/intel/soc/agilex5/platform.mk
+++ b/plat/intel/soc/agilex5/platform.mk
@@ -83,6 +83,7 @@
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_psci_common.c \
plat/intel/soc/agilex5/bl31_plat_setup.c \
+ plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \
plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_sip_svc.c \
diff --git a/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c b/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
index cc68153..fdf1a82 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
@@ -14,6 +14,7 @@
#include "agilex5_clock_manager.h"
#include "agilex5_system_manager.h"
#include "socfpga_handoff.h"
+#include "socfpga_system_manager.h"
uint32_t wait_pll_lock(void)
{
@@ -251,3 +252,9 @@
return mmc_clk;
}
+
+/* Return mpu_periph_clk tick */
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
+}