refactor(arm): unify SPSR retrieval logic
Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces duplication and simplifies control over SPSR
generation for later stages, particularly BL33.
The SPD remains responsible for setting the SPSR for BL32.
Change-Id: Ibbba708d607e7676989f5c7ceffe33d7bb2195f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index 0726c26..0901df3 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -61,7 +61,7 @@
static inline void bl31_set_default_config(void)
{
bl32_image_ep_info.pc = BL32_BASE;
- bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+ bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID);
#if defined(SPD_opteed)
#if (TRANSFER_LIST == 0)
/* NS dtb addr passed to optee_os */
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 946af3b..d0493a7 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -266,7 +266,7 @@
WARN("OPTEE header parse error.\n");
}
#endif
- bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
+ bl_mem_params->ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID);
break;
#endif
@@ -275,7 +275,7 @@
/* BL33 expects to receive the primary CPU MPID (through r0) */
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
#endif /* !USE_KERNEL_DT_CONVENTION */
- bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
+ bl_mem_params->ep_info.spsr = arm_get_spsr(BL33_IMAGE_ID);
break;
#ifdef SCP_BL2_BASE
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index f44be5c..353efac 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -172,7 +172,7 @@
*/
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
- bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+ bl33_image_ep_info.spsr = arm_get_spsr(BL33_IMAGE_ID);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
bl33_image_ep_info.args.arg0 = PLAT_ARM_TRANSFER_LIST_DTB_OFFSET;
@@ -227,7 +227,7 @@
0);
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
bl32_image_ep_info.pc = BL32_BASE;
- bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+ bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID);
#if defined(SPD_spmd)
bl32_image_ep_info.args.arg0 = ARM_SPMC_MANIFEST_BASE;
@@ -253,7 +253,7 @@
bl33_image_ep_info.args.arg3 = 0U;
#endif /* ARM_LINUX_KERNEL_AS_BL33 */
- bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+ bl33_image_ep_info.spsr = arm_get_spsr(BL33_IMAGE_ID);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
#if ENABLE_RME
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index 2d4165c..3278a31 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -71,26 +71,20 @@
}
/*******************************************************************************
- * Gets SPSR for BL32 entry
+ * Gets SPSR for next stage images.
******************************************************************************/
-uint32_t arm_get_spsr_for_bl32_entry(void)
+uint32_t arm_get_spsr(unsigned int image_id)
{
- /*
- * The Secure Payload Dispatcher service is responsible for
- * setting the SPSR prior to entry into the BL32 image.
- */
- return 0;
-}
+ unsigned int __unused hyp_status, mode, spsr;
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
+ if (image_id == BL32_IMAGE_ID) {
+ /* The Secure Payload Dispatcher service is responsible for
+ * setting the SPSR prior to entry into the BL32 image.
+ */
+ return 0;
+ }
+
#ifdef __aarch64__
-uint32_t arm_get_spsr_for_bl33_entry(void)
-{
- unsigned int mode;
- uint32_t spsr;
-
/* Figure out what mode we enter the non-secure world in */
mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
@@ -100,16 +94,7 @@
* well.
*/
spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
- return spsr;
-}
#else
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-uint32_t arm_get_spsr_for_bl33_entry(void)
-{
- unsigned int hyp_status, mode, spsr;
-
hyp_status = GET_VIRT_EXT(read_id_pfr1());
mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
@@ -120,10 +105,11 @@
* well.
*/
spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
- SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+ SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+#endif /* __aarch64__ */
+
return spsr;
}
-#endif /* __aarch64__ */
/*******************************************************************************
* Configures access to the system counter timer module.
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index 6b15b73..2b52a76 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -97,16 +97,13 @@
#if RESET_TO_SP_MIN
/* Populate entry point information for BL33 */
- SET_PARAM_HEAD(&bl33_image_ep_info,
- PARAM_EP,
- VERSION_1,
- 0);
+ SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
/*
* Tell SP_MIN where the non-trusted software image
* is located and the entry state information
*/
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
- bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+ bl33_image_ep_info.spsr = arm_get_spsr(BL33_IMAGE_ID);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
#if ARM_LINUX_KERNEL_AS_BL33
diff --git a/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c b/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
index 4b29bbc..2179e7a 100644
--- a/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
+++ b/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* Copyright (C) 2017-2023 Nuvoton Ltd.
*
@@ -167,7 +167,7 @@
0);
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
bl32_image_ep_info.pc = BL32_BASE;
- bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+ bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID);
#if defined(SPD_spmd)
/*
@@ -194,7 +194,7 @@
*/
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
/* Generic ARM code will switch to EL2, revert to EL1 */
- bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+ bl33_image_ep_info.spsr = arm_get_spsr(BL33_IMAGE_ID);
bl33_image_ep_info.spsr &= ~0x8;
bl33_image_ep_info.spsr |= 0x4;
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 70b0fa6..4e2a3d9 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
@@ -55,7 +55,7 @@
static inline void bl31_set_default_config(void)
{
bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
- bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry();
+ bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr(BL32_IMAGE_ID);
bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index 2308a75..faeb335 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
@@ -53,7 +53,7 @@
static inline void bl31_set_default_config(void)
{
bl32_image_ep_info.pc = BL32_BASE;
- bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+ bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID);
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 65616e5..9841f7d 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -58,7 +58,7 @@
static inline void bl31_set_default_config(void)
{
bl32_image_ep_info.pc = BL32_BASE;
- bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+ bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID);
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);