blob: a6a480c655d10960fc6ab211c0beb6f97fd0a5f7 [file] [log] [blame]
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02001/*
2 * Copyright (c) 2018, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __ARCH_H__
8#define __ARCH_H__
9
10#define MPIDR_MT_MASK (1 << 24)
11#define MPIDR_AFFLVL_MASK 0xff
12#define MPIDR_AFFINITY_BITS 8
13#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
14#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
15#define MPIDR_AFF0_SHIFT 0
16#define MPIDR_AFF1_SHIFT 8
17#define MPIDR_AFF2_SHIFT 16
18#define MPIDR_AFFINITY_MASK 0xff00ffffff
19
20#endif /* __ARCH_H__ */