fix(plat/arm/fvp): make address space configurable
Make FVP physical/virtual address space sizes configurable, with
default at 34-bit (previously hard-coded value).
Maximum tested value is 48-bit, FVP interconnect doesn't yet support
52-bit PA.
Increase MAX_XLAT_TABLE and consequently NS_BL1U_RW_SIZE and
NS_BLU2_LIMIT to accommodate the increased translation tables (based
on 48-bit max PA size).
Custom PA size is passed to build system through the PA_SIZE define.
FVP needs to be configured in a compatible way through the parameters:
* cluster0.PA_SIZE, for each cluster;
* bp.dram_size, setting a memory limit corresponding at least to
PA_SIZE;
* cci550.addr_width, interconnect address width should match PA_SIZE;
* pci.pci_smmuv3.mmu.SMMU_IDR5, SMMU has to be configured as well if
present.
Change-Id: I57bc898fb2c9696c01fc8e20d00b4a3d09e22326
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
diff --git a/plat/arm/fvp/include/platform_def.h b/plat/arm/fvp/include/platform_def.h
index 8555c1f..fffacfc 100644
--- a/plat/arm/fvp/include/platform_def.h
+++ b/plat/arm/fvp/include/platform_def.h
@@ -137,7 +137,7 @@
* calculated using the current NS_BL1U RW debug size plus a little space
* for growth.
******************************************************************************/
-#define NS_BL1U_RW_SIZE (0x7000)
+#define NS_BL1U_RW_SIZE (0x9000)
#define NS_BL1U_RW_BASE (NSRAM_BASE)
#define NS_BL1U_RW_LIMIT (NS_BL1U_RW_BASE + NS_BL1U_RW_SIZE)
@@ -153,7 +153,7 @@
* Base address and limit for NS_BL2U image.
******************************************************************************/
#define NS_BL2U_BASE DRAM_BASE
-#define NS_BL2U_LIMIT (NS_BL2U_BASE + 0x4D000)
+#define NS_BL2U_LIMIT (NS_BL2U_BASE + 0x4E000)
/******************************************************************************
* Memory mapped Generic timer interfaces
@@ -239,8 +239,8 @@
* Platform specific page table and MMU setup constants
******************************************************************************/
#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 34)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 34)
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << PA_SIZE)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << PA_SIZE)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
@@ -252,7 +252,7 @@
#define MAX_MMAP_REGIONS 50
#else
#if IMAGE_CACTUS
-#define MAX_XLAT_TABLES 6
+#define MAX_XLAT_TABLES 8
#else
#define MAX_XLAT_TABLES 5
#endif
diff --git a/plat/arm/fvp/platform.mk b/plat/arm/fvp/platform.mk
index c9bbe6e..e467cd6 100644
--- a/plat/arm/fvp/platform.mk
+++ b/plat/arm/fvp/platform.mk
@@ -80,6 +80,15 @@
$(eval $(call add_define,TFTF_DEFINES,FVP_MAX_CPUS_PER_CLUSTER))
$(eval $(call add_define,TFTF_DEFINES,FVP_MAX_PE_PER_CPU))
+# Default PA size for FVP platform
+PA_SIZE := 34
+
+$(eval $(call add_define,CACTUS_DEFINES,PA_SIZE))
+$(eval $(call add_define,IVY_DEFINES,PA_SIZE))
+$(eval $(call add_define,NS_BL1U_DEFINES,PA_SIZE))
+$(eval $(call add_define,NS_BL2U_DEFINES,PA_SIZE))
+$(eval $(call add_define,TFTF_DEFINES,PA_SIZE))
+
PLAT_INCLUDES += -Iplat/arm/fvp/include/
PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \