test(realm): fix realm_printf string
Remove extra Realm: string from realm printf
correct the print format
Change-Id: I1916cf5bda23aab2cdee59457872353c108148c7
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
diff --git a/realm/realm_simd.c b/realm/realm_simd.c
index 106a849..2eb3eab 100644
--- a/realm/realm_simd.c
+++ b/realm/realm_simd.c
@@ -65,7 +65,7 @@
output = (struct sve_cmd_id_regs *)sd->realm_cmd_output_buffer;
memset((void *)output, 0, sizeof(struct sve_cmd_id_regs));
- realm_printf("Realm: reading ID registers: ID_AA64PFR0_EL1, "
+ realm_printf("reading ID registers: ID_AA64PFR0_EL1, "
" ID_AA64ZFR0_EL1\n");
output->id_aa64pfr0_el1 = read_id_aa64pfr0_el1();
output->id_aa64zfr0_el1 = read_id_aa64zfr0_el1();
@@ -118,7 +118,7 @@
/* Check result of SVE operations. */
for (i = 0; i < RL_SVE_OP_ARRAYSIZE; i++) {
if (rl_sve_op_1[i] != (val - i - SVE_TEST_ITERATIONS)) {
- realm_printf("Realm: SVE ops failed\n");
+ realm_printf("SVE ops failed\n");
return false;
}
}
@@ -181,7 +181,7 @@
/* fpcr, fpsr common registers */
fpu_cs_regs_read(&rl_fpu_cs_regs_read);
if (fpu_cs_regs_compare(&rl_fpu_cs_regs_write, &rl_fpu_cs_regs_read)) {
- ERROR("Realm: FPCR/FPSR mismatch\n");
+ ERROR("FPCR/FPSR mismatch\n");
rc = false;
}
@@ -193,7 +193,7 @@
uint64_t esr_el1 = read_esr_el1();
if (EC_BITS(esr_el1) == EC_UNKNOWN) {
- realm_printf("Realm: received undefined abort. "
+ realm_printf("received undefined abort. "
"esr_el1: 0x%llx elr_el1: 0x%llx\n",
esr_el1, read_elr_el1());
realm_got_undef_abort++;
@@ -228,7 +228,7 @@
output = (struct sme_cmd_id_regs *)sd->realm_cmd_output_buffer;
memset((void *)output, 0, sizeof(struct sme_cmd_id_regs));
- realm_printf("Realm: reading ID registers: ID_AA64PFR1_EL1, "
+ realm_printf("reading ID registers: ID_AA64PFR1_EL1, "
" ID_AA64SMFR0_EL1\n");
output->id_aa64pfr1_el1 = read_id_aa64pfr1_el1();