Trusted Firmware-A Tests, version 2.0
This is the first public version of the tests for the Trusted
Firmware-A project. Please see the documentation provided in the
source tree for more details.
Change-Id: I6f3452046a1351ac94a71b3525c30a4ca8db7867
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: amobal01 <amol.balasokamble@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Co-authored-by: Asha R <asha.r@arm.com>
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Co-authored-by: David Cunado <david.cunado@arm.com>
Co-authored-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Co-authored-by: Douglas Raillard <douglas.raillard@arm.com>
Co-authored-by: dp-arm <dimitris.papastamos@arm.com>
Co-authored-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Co-authored-by: Jonathan Wright <jonathan.wright@arm.com>
Co-authored-by: Kévin Petit <kevin.petit@arm.com>
Co-authored-by: Roberto Vargas <roberto.vargas@arm.com>
Co-authored-by: Sathees Balya <sathees.balya@arm.com>
Co-authored-by: Shawon Roy <Shawon.Roy@arm.com>
Co-authored-by: Soby Mathew <soby.mathew@arm.com>
Co-authored-by: Thomas Abraham <thomas.abraham@arm.com>
Co-authored-by: Vikram Kanigiri <vikram.kanigiri@arm.com>
Co-authored-by: Yatharth Kochar <yatharth.kochar@arm.com>
diff --git a/tftf/tests/misc_tests/boot_req_tests/test_cntfrq.c b/tftf/tests/misc_tests/boot_req_tests/test_cntfrq.c
new file mode 100644
index 0000000..78289bb
--- /dev/null
+++ b/tftf/tests/misc_tests/boot_req_tests/test_cntfrq.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <plat_topology.h>
+#include <power_management.h>
+#include <psci.h>
+#include <stdlib.h>
+#include <test_helpers.h>
+#include <tftf_lib.h>
+
+static test_result_t cntfrq_check(void)
+{
+ u_register_t cntfrq_el0, ns_cntfrq;
+ cntfrq_el0 = read_cntfrq_el0();
+
+ ns_cntfrq = mmio_read_32(SYS_CNT_BASE1 + CNTBASEN_CNTFRQ);
+
+ if (cntfrq_el0 != ns_cntfrq) {
+ tftf_testcase_printf("CNTFRQ read from sys_reg = %llx and NS timer = %llx differs/n",
+ (unsigned long long)cntfrq_el0,
+ (unsigned long long)ns_cntfrq);
+ return TEST_RESULT_FAIL;
+ }
+
+ return TEST_RESULT_SUCCESS;
+}
+
+/*
+ * The ARM ARM says that the cntfrq_el0, cntfrq memory mapped register and
+ * the RO views in NS timer frames must all be initialized by the firmware.
+ * (See I3.6.7 and D7.5.1 section in ARM ARM).
+ * This tests the same on all the CPUs in the system.
+ * Returns:
+ * TEST_RESULT_SUCCESS: if all the cntfrq values match
+ * TEST_RESULT_FAIL: if any of the cntfrq value mismatch
+ */
+test_result_t test_cntfrq_check(void)
+{
+ unsigned int lead_mpid = read_mpidr_el1() & MPID_MASK;
+ unsigned int cpu_node, cpu_mpid;
+ int rc;
+
+ /* Bring every CPU online */
+ for_each_cpu(cpu_node) {
+ cpu_mpid = tftf_get_mpidr_from_node(cpu_node);
+ /* Skip lead CPU as it is already on */
+ if (cpu_mpid == lead_mpid)
+ continue;
+
+ rc = tftf_cpu_on(cpu_mpid,
+ (uintptr_t) cntfrq_check,
+ 0);
+ if (rc != PSCI_E_SUCCESS) {
+ tftf_testcase_printf(
+ "Failed to power on CPU 0x%x (%d)\n",
+ cpu_mpid, rc);
+ return TEST_RESULT_FAIL;
+ }
+ }
+
+ rc = cntfrq_check();
+
+ /* Wait for the CPUs to turn OFF */
+ for_each_cpu(cpu_node) {
+ cpu_mpid = tftf_get_mpidr_from_node(cpu_node);
+
+ /* Wait for all non lead CPUs to turn OFF before returning */
+ if (cpu_mpid == lead_mpid)
+ continue;
+
+ /* Wait for the target CPU to turn OFF */
+ while (tftf_psci_affinity_info(cpu_mpid,
+ MPIDR_AFFLVL0) != PSCI_STATE_OFF)
+ ;
+ }
+
+ return rc;
+}
diff --git a/tftf/tests/misc_tests/inject_serror.S b/tftf/tests/misc_tests/inject_serror.S
new file mode 100644
index 0000000..0d7dbf2
--- /dev/null
+++ b/tftf/tests/misc_tests/inject_serror.S
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <sdei.h>
+
+
+#ifdef AARCH64
+ .globl inject_serror
+ .globl inject_uncontainable
+ .globl serror_sdei_event_handler
+
+/*
+ * Program fault injection register, and wait for ever for the fault to trigger.
+ * Note that Trusted Firmware must be compiled for ARMv8.4 along with
+ * FAULT_INJECTION_SUPPORT=1 for this to work. Besides, the model has to be
+ * launched with fault inject support.
+ *
+ * x0: Fault record number to program
+ * x1: Injected fault properties
+ * x2: Type of error to be generated
+ * x3: Memory location to wait for, or 0 if no waiting is required
+ */
+func inject_serror_record
+ /* Choose Error record 0 on the PE */
+ msr ERRSELR_EL1, x0
+ isb
+
+ /* Enable error reporting */
+ orr x1, x1, #ERXCTLR_ED_BIT
+ msr ERXCTLR_EL1, x1
+
+ /* Program count down timer to 1 */
+ mov x0, #1
+ msr ERXPFGCDN_EL1, x0
+
+ /* Start count down to generate error */
+ orr x2, x2, #ERXPFGCTL_CDEN_BIT
+ msr ERXPFGCTL_EL1, x2
+ isb
+
+ cbz x3, 2f
+
+ /* Clear SError received flag */
+ str xzr, [x3, #0]
+ sevl
+
+1:
+ wfe
+ ldr x0, [x3, #0]
+ cbz x0, 1b
+
+2:
+ ret
+endfunc inject_serror_record
+
+/*
+ * Inject Unrecoverable error through fault record 0. Wait until serror_received
+ * is set by the SDEI handler in response to receving the event.
+ */
+func inject_serror
+ /* Inject fault into record 0 */
+ mov x0, #0
+
+ /* Enable error reporting */
+ mov x1, #ERXCTLR_UE_BIT
+ msr ERXCTLR_EL1, x1
+
+ /* Injected fault control */
+ mov x2, #ERXPFGCTL_UEU_BIT
+
+ /* Wait address */
+ adrp x3, serror_received
+ add x3, x3, :lo12:serror_received
+
+ b inject_serror_record
+endfunc inject_serror
+
+/*
+ * Inject Uncontainable error through fault record 0. This function doesn't wait
+ * as the handling is terminal in EL3.
+ */
+func inject_uncontainable
+ /* Inject fault into record 0 */
+ mov x0, #0
+
+ mov x1, xzr
+
+ /* Injected fault control */
+ mov x2, #ERXPFGCTL_UC_BIT
+
+ /* Nothing to wait for */
+ mov x3, xzr
+
+ b inject_serror_record
+endfunc inject_uncontainable
+
+/*
+ * SDEI event handler for SErrors.
+ */
+func serror_sdei_event_handler
+ stp x29, x30, [sp, #-16]!
+ bl serror_handler
+ ldp x29, x30, [sp], #16
+ mov_imm x0, SDEI_EVENT_COMPLETE
+ mov x1, xzr
+ smc #0
+ b .
+endfunc serror_sdei_event_handler
+#endif
diff --git a/tftf/tests/misc_tests/test_single_fault.c b/tftf/tests/misc_tests/test_single_fault.c
new file mode 100644
index 0000000..e652211
--- /dev/null
+++ b/tftf/tests/misc_tests/test_single_fault.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#include <arch_helpers.h>
+#include <sdei.h>
+#include <tftf_lib.h>
+
+#ifndef AARCH32
+
+uint64_t serror_received;
+
+extern void inject_serror(void);
+
+int serror_handler(int ev, uint64_t arg)
+{
+ serror_received = 1;
+ tftf_testcase_printf("SError SDEI event received.\n");
+
+ return 0;
+}
+
+extern int serror_sdei_event_handler(int ev, uint64_t arg);
+
+test_result_t test_single_fault(void)
+{
+ int64_t ret;
+ const int event_id = 5000;
+
+ /* Register SDEI handler */
+ ret = sdei_event_register(event_id, serror_sdei_event_handler, 0,
+ SDEI_REGF_RM_PE, read_mpidr_el1());
+ if (ret < 0) {
+ tftf_testcase_printf("SDEI event register failed: 0x%llx\n",
+ ret);
+ return TEST_RESULT_FAIL;
+ }
+
+ ret = sdei_event_enable(event_id);
+ if (ret < 0) {
+ tftf_testcase_printf("SDEI event enable failed: 0x%llx\n", ret);
+ return TEST_RESULT_FAIL;
+ }
+
+ ret = sdei_pe_unmask();
+ if (ret < 0) {
+ tftf_testcase_printf("SDEI pe unmask failed: 0x%llx\n", ret);
+ return TEST_RESULT_FAIL;
+ }
+
+ inject_serror();
+
+ return TEST_RESULT_SUCCESS;
+}
+
+#else
+
+test_result_t test_single_fault(void)
+{
+ tftf_testcase_printf("Not supported on AArch32.\n");
+ return TEST_RESULT_SKIPPED;
+}
+
+#endif
diff --git a/tftf/tests/misc_tests/test_uncontainable.c b/tftf/tests/misc_tests/test_uncontainable.c
new file mode 100644
index 0000000..79c9031
--- /dev/null
+++ b/tftf/tests/misc_tests/test_uncontainable.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <tftf_lib.h>
+
+#ifndef AARCH32
+
+extern void inject_uncontainable(void);
+
+test_result_t test_uncontainable(void)
+{
+ inject_uncontainable();
+
+ return TEST_RESULT_SUCCESS;
+}
+
+#else
+
+test_result_t test_uncontainable(void)
+{
+ tftf_testcase_printf("Not supported on AArch32.\n");
+ return TEST_RESULT_SKIPPED;
+}
+
+#endif