plat/arm/rdinfra: Add initial platform support for RD-N1-Edge
RD-N1-Edge platform consists of two clusters of four CPU's
each. The FVP for this platform does not support system suspend and
resume functionality as there is no wakeup source supported. So all
the system suspend and resume related tests are skipped.
Change-Id: I33649c7c67023127e736c760bf0ec4193c95ed1a
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
diff --git a/plat/arm/rdinfra/rdn1edge/topology.c b/plat/arm/rdinfra/rdn1edge/topology.c
new file mode 100644
index 0000000..5521de4
--- /dev/null
+++ b/plat/arm/rdinfra/rdn1edge/topology.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <plat_topology.h>
+#include <tftf_lib.h>
+
+static const struct {
+ unsigned int cluster_id;
+ unsigned int cpu_id;
+} plat_cores[] = {
+ /* Cluster0: 4 cores*/
+ { 0, 0 },
+ { 0, 1 },
+ { 0, 2 },
+ { 0, 3 },
+ /* Cluster1: 4 cores */
+ { 1, 0 },
+ { 1, 1 },
+ { 1, 2 },
+ { 1, 3 },
+};
+
+/*
+ * The power domain tree descriptor. The cluster power domains are
+ * arranged so that when the PSCI generic code creates the power domain tree,
+ * the indices of the CPU power domain nodes it allocates match the linear
+ * indices returned by plat_core_pos_by_mpidr().
+ */
+const unsigned char plat_pd_tree_desc[] = {
+ /* Number of root nodes */
+ SGI_CLUSTER_COUNT,
+ /* Number of children for the 1st node */
+ SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 2nd node */
+ SGI_MAX_CPUS_PER_CLUSTER
+};
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+ return plat_pd_tree_desc;
+}
+
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+ unsigned int mpid;
+
+ assert(core_pos < PLATFORM_CORE_COUNT);
+
+ mpid = make_mpid(
+ plat_cores[core_pos].cluster_id,
+ plat_cores[core_pos].cpu_id);
+
+ return mpid;
+}