fix(versal-net): check ttc irq status
Continuous interrupts are observed after cancel timer operation
as proper cleanup is not done in cancel timer routine.
Provide proper cleanup in cancel timer routine by reading the
ttc interrupt status register for cause of interrupt and disabling
the ttc counter by setting bit 0 in ttc counter control register.
Value of per-cpu hypervisor timer interrupt id is set to 26 in
accordance with arm documentation and reference for same is present in
arm juno and nvidia settings.
Change-Id: I4f19314deaec9fa05b6fcbe04d0192e3c2a1a772
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
diff --git a/plat/xilinx/common/timer/timers.c b/plat/xilinx/common/timer/timers.c
index f53cd84..da8467b 100644
--- a/plat/xilinx/common/timer/timers.c
+++ b/plat/xilinx/common/timer/timers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,6 +26,7 @@
#define TTC_IER_OFFSET U(0x60) /* Interrupt Enable Reg, RW */
#define TTC_CNT_CNTRL_DISABLE_MASK BIT(0)
+#define TTC_ISR_INTERVAL_BIT BIT_32(0)
#define TTC_CLK_SEL_MASK GENMASK(1, 0)
@@ -68,12 +69,22 @@
static int cancel_timer(void)
{
+ uint32_t status;
+ uint32_t reg;
+
+ status = timer_read_32(TTC_ISR_OFFSET);
+ if (status & TTC_ISR_INTERVAL_BIT) {
+ VERBOSE("Timer Interval Interrupt Event! %x\n", status);
+ } else {
+ INFO("Its not a Timer Interval Interrupt Event %d\n", status);
+ }
/* Disable Interrupt */
timer_write_32(TTC_IER_OFFSET, 0);
/* Disable Counter */
- timer_write_32(TTC_CLK_CNTRL_OFFSET, !CLK_CNTRL_PRESCALE_EN);
- timer_write_32(TTC_CNT_CNTRL_OFFSET, !CLK_CNTRL_PRESCALE_EN);
+ reg = timer_read_32(TTC_CNT_CNTRL_OFFSET);
+ reg |= TTC_CNT_CNTRL_DISABLE_MASK;
+ timer_write_32(TTC_CNT_CNTRL_OFFSET, reg);
return RET_SUCCESS;
}
diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index 92a7ba0..12c5910 100644
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -99,7 +99,7 @@
#define IRQ_NS_SGI_7 7
/* Per-CPU Hypervisor Timer Interrupt ID */
-#define IRQ_PCPU_HP_TIMER U(29)
+#define IRQ_PCPU_HP_TIMER U(26)
/* Datasheet: TIME00 event*/
#define IRQ_CNTPSIRQ1 U(29)