fix(versal-net): check ttc irq status
Continuous interrupts are observed after cancel timer operation
as proper cleanup is not done in cancel timer routine.
Provide proper cleanup in cancel timer routine by reading the
ttc interrupt status register for cause of interrupt and disabling
the ttc counter by setting bit 0 in ttc counter control register.
Value of per-cpu hypervisor timer interrupt id is set to 26 in
accordance with arm documentation and reference for same is present in
arm juno and nvidia settings.
Change-Id: I4f19314deaec9fa05b6fcbe04d0192e3c2a1a772
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
2 files changed