Merge changes from topic "fix_pmuv3p9_test"
* changes:
feat(ras): add RAS system registers access test
fix(smccc): availability test: add two features and fix TRNDR
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index 8ca4cdf..1ab35ba 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -279,6 +279,14 @@
} \
} while (false)
+#define SKIP_TEST_IF_RAS_NOT_SUPPORTED() \
+ do { \
+ if(!is_feat_ras_present()){ \
+ tftf_testcase_printf("ARMv8.2-RAS not supported\n"); \
+ return TEST_RESULT_SKIPPED; \
+ } \
+ } while (false)
+
#ifdef __aarch64__
#define SKIP_TEST_IF_PA_SIZE_LESS_THAN(n) \
do { \
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 2e2e1df..d9009dd 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -273,6 +273,7 @@
#define ID_AA64DFR0_PMUVER_SHIFT U(8)
#define ID_AA64DFR0_PMUVER_MASK ULL(0xf)
#define ID_AA64DFR0_PMUVER_NOT_SUPPORTED ULL(0)
+#define ID_AA64DFR0_PMUVER_V3P9_SUPPORTED ULL(9)
/* ID_AA64DFR0_EL1.TraceVer definitions */
#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
@@ -285,6 +286,10 @@
/* ID_AA64ISAR0_EL1 definitions */
#define ID_AA64ISAR0_EL1 S3_0_C0_C6_0
+#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
+#define ID_AA64ISAR0_RNDR_SHIFT U(60)
+#define ID_AA64ISAR0_RNDR_WIDTH U(4)
+#define ID_AA64ISAR0_RNDR_SUPPORTED ULL(0x1)
#define ID_AA64ISAR0_TLB_MASK ULL(0xf)
#define ID_AA64ISAR0_TLB_SHIFT U(56)
#define ID_AA64ISAR0_TLB_WIDTH U(4)
@@ -408,6 +413,10 @@
#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
+#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
+#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
+#define ID_AA64MMFR1_EL1_TWED_WIDTH U(4)
+#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index cee8dd2..3b4fffc 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -230,6 +230,13 @@
ID_AA64ISAR2_WFXT_MASK) == ID_AA64ISAR2_WFXT_SUPPORTED);
}
+static inline bool is_feat_rng_present(void)
+{
+ return (((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) &
+ ID_AA64ISAR0_RNDR_MASK)
+ >= ID_AA64ISAR0_RNDR_SUPPORTED);
+}
+
static inline bool is_feat_rng_trap_present(void)
{
return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) &
@@ -273,6 +280,12 @@
ID_AA64DFR0_PMUVER_MASK) != ID_AA64DFR0_PMUVER_NOT_SUPPORTED);
}
+static inline bool is_feat_pmuv3p9_present(void)
+{
+ return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMUVER_SHIFT) &
+ ID_AA64DFR0_PMUVER_MASK) >= ID_AA64DFR0_PMUVER_V3P9_SUPPORTED);
+}
+
static inline bool get_feat_hpmn0_supported(void)
{
return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_HPMN0_SHIFT) &
@@ -477,6 +490,12 @@
return amu_get_version() >= ID_AA64PFR0_AMU_V1P1;
}
+static inline bool is_feat_twed_present(void)
+{
+ return EXTRACT(ID_AA64MMFR1_EL1_TWED, read_id_aa64mmfr1_el1())
+ >= ID_AA64MMFR1_EL1_TWED_SUPPORTED;
+}
+
static inline bool is_feat_trbe_present(void)
{
return EXTRACT(ID_AA64DFR0_TRACEBUFFER, read_id_aa64dfr0_el1())
diff --git a/tftf/tests/extensions/ras/test_ras.c b/tftf/tests/extensions/ras/test_ras.c
new file mode 100644
index 0000000..cd27f16
--- /dev/null
+++ b/tftf/tests/extensions/ras/test_ras.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <test_helpers.h>
+#include <tftf_lib.h>
+#include <tftf.h>
+
+/*
+ * FEAT_RAS introduces EL1 system registers to query error records, those
+ * CPU specific parts of the RAS extension can be accessed independently of
+ * any FFH/KFH handling setup or any system specific RAS implementation.
+ * Reading these registers will trap to EL3 and crash when EL3 has not
+ * allowed access, which is controlled by the SCR_EL3.TERR bit.
+ */
+
+test_result_t test_ras_reg_access(void)
+{
+ SKIP_TEST_IF_AARCH32();
+
+#ifdef __aarch64__
+ SKIP_TEST_IF_RAS_NOT_SUPPORTED();
+
+ read_erridr_el1();
+
+ return TEST_RESULT_SUCCESS;
+#endif
+}
diff --git a/tftf/tests/runtime_services/arm_arch_svc/smccc_feature_availability.c b/tftf/tests/runtime_services/arm_arch_svc/smccc_feature_availability.c
index 1418ca1..7c7f91b 100644
--- a/tftf/tests/runtime_services/arm_arch_svc/smccc_feature_availability.c
+++ b/tftf/tests/runtime_services/arm_arch_svc/smccc_feature_availability.c
@@ -79,12 +79,13 @@
CHECK_BIT_SET(is_feat_tcr2_supported, SCR_TCR2EN_BIT);
CHECK_BIT_SET(is_feat_the_supported, SCR_RCWMASKEn_BIT);
CHECK_BIT_SET(is_feat_sme_supported, SCR_ENTP2_BIT);
- CHECK_BIT_SET(is_feat_rng_trap_present, SCR_TRNDR_BIT);
+ CHECK_BIT_SET(is_feat_rng_present, SCR_TRNDR_BIT);
CHECK_BIT_SET(is_feat_gcs_present, SCR_GCSEn_BIT);
CHECK_BIT_SET(get_feat_hcx_support, SCR_HXEn_BIT);
CHECK_BIT_SET(is_feat_ls64_accdata_present, SCR_ADEn_BIT);
CHECK_BIT_SET(is_feat_ls64_accdata_present, SCR_EnAS0_BIT);
CHECK_BIT_SET(is_feat_amuv1p1_present, SCR_AMVOFFEN_BIT);
+ CHECK_BIT_SET(is_feat_twed_present, SCR_TWEDEn_BIT);
CHECK_BIT_SET(get_armv8_6_ecv_support, SCR_ECVEN_BIT);
CHECK_BIT_SET(is_armv8_6_fgt_present, SCR_FGTEN_BIT);
CHECK_BIT_SET(is_feat_mte2_present, SCR_ATA_BIT);
@@ -108,6 +109,7 @@
CHECK_BIT_SET(is_feat_trbe_present, MDCR_NSTB(1));
CHECK_BIT_SET(get_armv8_4_trf_support, MDCR_TTRF_BIT);
CHECK_BIT_SET(is_feat_spe_supported, MDCR_NSPB(1));
+ CHECK_BIT_SET(is_feat_pmuv3p9_present, MDCR_EnPM2_BIT);
CHECK_BIT_SET(is_feat_doublelock_present, MDCR_TDOSA_BIT);
CHECK_BIT_SET(always_present, MDCR_TDA_BIT);
CHECK_BIT_SET(get_feat_pmuv3_supported, MDCR_TPM_BIT);
diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk
index 9358c49..37e41de 100644
--- a/tftf/tests/tests-cpu-extensions.mk
+++ b/tftf/tests/tests-cpu-extensions.mk
@@ -19,6 +19,7 @@
extensions/mte/test_mte.c \
extensions/pauth/test_pauth.c \
extensions/pmuv3/test_pmuv3.c \
+ extensions/ras/test_ras.c \
extensions/sctlr2/test_sctlr2.c \
extensions/sme/test_sme.c \
extensions/sme/test_sme2.c \
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index 632e231..dd60bc1 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -19,6 +19,7 @@
<testcase name="Check for Pointer Authentication key leakage from EL3" function="test_pauth_leakage" />
<testcase name="Check for Pointer Authentication key leakage from TSP" function="test_pauth_leakage_tsp" />
<testcase name="Access MPAM registers" function="test_mpam_reg_access" />
+ <testcase name="Access RAS registers" function="test_ras_reg_access" />
<testcase name="Use MTE Instructions" function="test_mte_instructions" />
<testcase name="Check for MTE register leakage" function="test_mte_leakage" />
<testcase name="Use FGT Registers" function="test_fgt_enabled" />