feat: tftf realm extension
This patch adds Realm payload management capabilities to TFTF
to act as a NS Host, it includes creation and destruction of a Realm,
mapping of protected data and creation of all needed RTT levels,
sharing of NS memory buffer from Host to Realm by mapping of
unprotected IPA, create REC and auxiliary granules, exit Realm
using RSI_HOST_CALL ABI.
Older realm_payload name is used now for only R-EL1 test cases,
RMI and SPM test cases have been moved to new file tests-rmi-spm.
New TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk,
as an offset from where R-EL1 payload memory resources start.
Signed-off-by: Nabil Kahlouche <nabil.kahlouche@arm.com>
Change-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7
diff --git a/include/common/debug.h b/include/common/debug.h
index 4b30175..6025590 100644
--- a/include/common/debug.h
+++ b/include/common/debug.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2014-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +24,11 @@
void mp_printf(const char *fmt, ...);
#endif /* IMAGE_CACTUS_MM */
+#ifdef IMAGE_REALM
+void realm_printf(const char *fmt, ...);
+#define mp_printf realm_printf
+#endif
+
/*
* The log output macros print output to the console. These macros produce
* compiled log output only if the LOG_LEVEL defined in the makefile (or the
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h
index a4b7d7d..230d69a 100644
--- a/include/lib/aarch32/arch.h
+++ b/include/lib/aarch32/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -505,6 +505,50 @@
#define CNTP_CTL_IMASK_MASK U(1)
#define CNTP_CTL_ISTATUS_MASK U(1)
+/* Exception Syndrome register bits and bobs */
+#define ESR_EC_SHIFT U(26)
+#define ESR_EC_MASK U(0x3f)
+#define ESR_EC_LENGTH U(6)
+#define ESR_ISS_SHIFT U(0x0)
+#define ESR_ISS_MASK U(0x1ffffff)
+#define EC_UNKNOWN U(0x0)
+#define EC_WFE_WFI U(0x1)
+#define EC_CP15_MRC_MCR U(0x3)
+#define EC_CP15_MRRC_MCRR U(0x4)
+#define EC_CP14_MRC_MCR U(0x5)
+#define EC_CP14_LDC_STC U(0x6)
+#define EC_FP_SIMD U(0x7)
+#define EC_CP10_MRC U(0x8)
+#define EC_CP14_MRRC_MCRR U(0xc)
+#define EC_ILLEGAL U(0xe)
+#define EC_SVC U(0x11)
+#define EC_HVC U(0x12)
+#define EC_SMC U(0x13)
+#define EC_IABORT_LOWER_EL U(0x20)
+#define EC_IABORT_CUR_EL U(0x21)
+#define EC_PC_ALIGN U(0x22)
+#define EC_DABORT_LOWER_EL U(0x24)
+#define EC_DABORT_CUR_EL U(0x25)
+#define EC_SP_ALIGN U(0x26)
+#define EC_FP U(0x28)
+#define EC_SERROR U(0x2f)
+/* Data Fault Status code, not all error codes listed */
+#define ISS_DFSC_MASK U(0x3f)
+#define DFSC_EXT_DABORT U(0x10)
+#define DFSC_GPF_DABORT U(0x28)
+/* ISS encoding an exception from HVC or SVC instruction execution */
+#define ISS_HVC_SMC_IMM16_MASK U(0xffff)
+
+/*
+ * External Abort bit in Instruction and Data Aborts synchronous exception
+ * syndromes.
+ */
+#define ESR_ISS_EABORT_EA_BIT U(9)
+
+#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
+#define ISS_BITS(x) (((x) >> ESR_ISS_SHIFT) & ESR_ISS_MASK)
+
+
/* MAIR macros */
#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3)))
#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3)))
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 534e1cf..e436e6b 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -717,6 +717,8 @@
#define ISS_DFSC_MASK U(0x3f)
#define DFSC_EXT_DABORT U(0x10)
#define DFSC_GPF_DABORT U(0x28)
+/* ISS encoding an exception from HVC or SVC instruction execution */
+#define ISS_HVC_SMC_IMM16_MASK U(0xffff)
/*
* External Abort bit in Instruction and Data Aborts synchronous exception
diff --git a/include/lib/heap/page_alloc.h b/include/lib/heap/page_alloc.h
new file mode 100644
index 0000000..7580b78
--- /dev/null
+++ b/include/lib/heap/page_alloc.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PAGE_ALLOC_H
+#define PAGE_ALLOC_H
+
+#include <stdint.h>
+#include <stdlib.h>
+
+#define HEAP_NULL_PTR 0U
+#define HEAP_INVALID_LEN -1
+#define HEAP_OUT_OF_RANGE -2
+#define HEAP_INIT_FAILED -3
+#define HEAP_INIT_SUCCESS 0
+
+/*
+ * Initialize the memory heap space to be used
+ * @heap_base: heap base address
+ * @heap_len: heap size for use
+ */
+int page_pool_init(uint64_t heap_base, uint64_t heap_len);
+
+/*
+ * Return the pointer to the allocated pages
+ * @bytes_size: pages to allocate in byte unit
+ */
+void *page_alloc(u_register_t bytes_size);
+
+/*
+ * Reset heap memory usage cursor to heap base address
+ */
+void page_pool_reset(void);
+void page_free(u_register_t ptr);
+
+#endif /* PAGE_ALLOC_H */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 78d4131..9638495 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -162,4 +162,20 @@
#define COMPILER_BARRIER() __asm__ volatile ("" ::: "memory")
+#define MASK(regfield) \
+ ((~0ULL >> (64ULL - (regfield##_WIDTH))) << (regfield##_SHIFT))
+
+#define EXTRACT(regfield, reg) \
+ (((reg) & MASK(regfield)) >> (regfield##_SHIFT))
+
+/*
+ * Defines member of structure and reserves space
+ * for the next member with specified offset.
+ */
+#define SET_MEMBER(member, start, end) \
+ union { \
+ member; \
+ unsigned char reserved##end[end - start]; \
+ }
+
#endif /* UTILS_DEF_H */
diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index 1fd3c83..ba0559c 100644
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -179,4 +179,24 @@
#define XN_SHIFT 54
#define UXN_SHIFT XN_SHIFT
+/*
+ * Stage 2 translation Lower attributes
+ */
+#define S2TTE_AP_SHIFT 6
+#define S2TTE_AP_RW (3UL << S2TTE_AP_SHIFT)
+
+#define S2TTE_SH_SHIFT 8
+#define S2TTE_SH_MASK (3UL << S2TTE_SH_SHIFT)
+#define S2TTE_SH_NS (0UL << S2TTE_SH_SHIFT)
+#define S2TTE_SH_OS (2UL << S2TTE_SH_SHIFT)
+#define S2TTE_SH_IS (3UL << S2TTE_SH_SHIFT)
+
+/*
+ * Attributes when FEAT_S2FWB is enabled at EL2 (HCR_EL2.FWB == 1).
+ * For Normal WB cacheability attribute, set bit[4] to 1 and bits[3:2] to 0b10.
+ */
+#define S2TTE_MEMATTR_FWB_NORMAL_WB ((1UL << 4) | (2UL << 2))
+#define S2TTE_ATTR_FWB_WB_RW (S2TTE_MEMATTR_FWB_NORMAL_WB | S2TTE_AP_RW | \
+ S2TTE_SH_IS)
+
#endif /* XLAT_TABLES_DEFS_H */
diff --git a/include/runtime_services/host_realm_managment/host_realm_helper.h b/include/runtime_services/host_realm_managment/host_realm_helper.h
new file mode 100644
index 0000000..a103630
--- /dev/null
+++ b/include/runtime_services/host_realm_managment/host_realm_helper.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef HOST_REALM_HELPER_H
+#define HOST_REALM_HELPER_H
+
+#include <host_realm_rmi.h>
+
+bool host_create_realm_payload(u_register_t realm_payload_adr,
+ u_register_t plat_mem_pool_adr,
+ u_register_t plat_mem_pool_size,
+ u_register_t realm_pages_size);
+bool host_create_shared_mem(
+ u_register_t ns_shared_mem_adr,
+ u_register_t ns_shared_mem_size);
+bool host_destroy_realm(void);
+bool host_enter_realm_execute(uint8_t cmd);
+
+#endif /* HOST_REALM_HELPER_H */
+
diff --git a/include/runtime_services/host_realm_managment/host_realm_mem_layout.h b/include/runtime_services/host_realm_managment/host_realm_mem_layout.h
new file mode 100644
index 0000000..2c5a605
--- /dev/null
+++ b/include/runtime_services/host_realm_managment/host_realm_mem_layout.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef HOST_REALM_MEM_LAYOUT_H
+#define HOST_REALM_MEM_LAYOUT_H
+
+#include <realm_def.h>
+
+#include <platform_def.h>
+
+/*
+ * Realm payload Memory Usage Layout
+ *
+ * +--------------------------+ +---------------------------+
+ * | | | Host Image |
+ * | TFTF | | (TFTF_MAX_IMAGE_SIZE) |
+ * | Normal World | ==> +---------------------------+
+ * | Image | | Realm Image |
+ * | (MAX_NS_IMAGE_SIZE) | | (REALM_MAX_LOAD_IMG_SIZE |
+ * +--------------------------+ +---------------------------+
+ * | Memory Pool | | Heap Memory |
+ * | (NS_REALM_SHARED_MEM_SIZE| | (PAGE_POOL_MAX_SIZE) |
+ * | + PAGE_POOL_MAX_SIZE) | ==> | |
+ * | | | |
+ * | | +---------------------------+
+ * | | | Shared Region |
+ * | | | (NS_REALM_SHARED_MEM_SIZE)|
+ * +--------------------------+ +---------------------------+
+ *
+ */
+
+/*
+ * Default values defined in platform.mk, and can be provided as build arguments
+ * TFTF_MAX_IMAGE_SIZE: 1mb
+ */
+
+#ifdef TFTF_MAX_IMAGE_SIZE
+/* 1MB for shared buffer between Realm and Host*/
+ #define NS_REALM_SHARED_MEM_SIZE U(0x100000)
+/* 3MB of memory used as a pool for realm's objects creation*/
+ #define PAGE_POOL_MAX_SIZE U(0x300000)
+/* Base address of each section */
+ #define REALM_IMAGE_BASE (TFTF_BASE + TFTF_MAX_IMAGE_SIZE)
+ #define PAGE_POOL_BASE (REALM_IMAGE_BASE + REALM_MAX_LOAD_IMG_SIZE)
+ #define NS_REALM_SHARED_MEM_BASE (PAGE_POOL_BASE + PAGE_POOL_MAX_SIZE)
+#else
+ #define NS_REALM_SHARED_MEM_SIZE 0U
+ #define PAGE_POOL_MAX_SIZE 0U
+ #define TFTF_MAX_IMAGE_SIZE DRAM_SIZE
+/* Base address of each section */
+ #define REALM_IMAGE_BASE 0U
+ #define PAGE_POOL_BASE 0U
+ #define NS_REALM_SHARED_MEM_BASE 0U
+#endif
+
+#endif /* HOST_REALM_MEM_LAYOUT_H */
diff --git a/include/runtime_services/host_realm_managment/host_realm_rmi.h b/include/runtime_services/host_realm_managment/host_realm_rmi.h
new file mode 100644
index 0000000..4e5f8c6
--- /dev/null
+++ b/include/runtime_services/host_realm_managment/host_realm_rmi.h
@@ -0,0 +1,507 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef HOST_REALM_RMI_H
+#define HOST_REALM_RMI_H
+
+#include <stdint.h>
+
+#include <realm_rsi.h>
+#include <smccc.h>
+#include <utils_def.h>
+
+#define RMI_FNUM_MIN_VALUE U(0x150)
+#define RMI_FNUM_MAX_VALUE U(0x18F)
+
+/* Get RMI fastcall std FID from offset */
+#define SMC64_RMI_FID(_offset) \
+ ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \
+ (SMC_64 << FUNCID_CC_SHIFT) | \
+ (OEN_STD_START << FUNCID_OEN_SHIFT) | \
+ (((RMI_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \
+ << FUNCID_NUM_SHIFT))
+
+#define RMI_ABI_VERSION_GET_MAJOR(_version) (((_version) >> 16U) & 0x8FFF)
+#define RMI_ABI_VERSION_GET_MINOR(_version) ((_version) & 0xFFFF)
+
+#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
+#define __ALIGN(x, a) __ALIGN_MASK(x, (typeof(x))(a) - 1U)
+#define ALIGN(x, a) __ALIGN((x), (a))
+
+/*
+ * SMC_RMM_INIT_COMPLETE is the only function in the RMI that originates from
+ * the Realm world and is handled by the RMMD. The remaining functions are
+ * always invoked by the Normal world, forwarded by RMMD and handled by the
+ * RMM
+ */
+/* RMI SMC64 FIDs handled by the RMMD */
+/* no parameters */
+#define RMI_VERSION SMC64_RMI_FID(U(0x0))
+
+/*
+ * arg0 == target granule address
+ */
+#define RMI_GRANULE_DELEGATE SMC64_RMI_FID(U(0x1))
+
+/*
+ * arg0 == target granule address
+ */
+#define RMI_GRANULE_UNDELEGATE SMC64_RMI_FID(U(0x2))
+
+/*
+ * arg0 == data address
+ * arg1 == RD address
+ * arg2 == map address
+ * arg3 == SRC address
+ */
+#define RMI_DATA_CREATE SMC64_RMI_FID(U(0x3))
+
+/*
+ * arg0 == data address
+ * arg1 == RD address
+ * arg2 == map address
+ */
+#define RMI_DATA_CREATE_UNKNOWN SMC64_RMI_FID(U(0x4))
+
+/*
+ * arg0 == RD address
+ * arg1 == map address
+ */
+#define RMI_DATA_DESTROY SMC64_RMI_FID(U(0x5))
+
+/*
+ * arg0 == RD address
+ */
+#define RMI_REALM_ACTIVATE SMC64_RMI_FID(U(0x7))
+
+/*
+ * arg0 == RD address
+ * arg1 == struct rmi_realm_params addr
+ */
+#define RMI_REALM_CREATE SMC64_RMI_FID(U(0x8))
+
+/*
+ * arg0 == RD address
+ */
+#define RMI_REALM_DESTROY SMC64_RMI_FID(U(0x9))
+
+/*
+ * arg0 == REC address
+ * arg1 == RD address
+ * arg2 == struct rmm_rec address
+ */
+#define RMI_REC_CREATE SMC64_RMI_FID(U(0xA))
+
+/*
+ * arg0 == REC address
+ */
+#define RMI_REC_DESTROY SMC64_RMI_FID(U(0xB))
+
+/*
+ * arg0 == rec address
+ * arg1 == rec_run address
+ */
+#define RMI_REC_ENTER SMC64_RMI_FID(U(0xC))
+
+/*
+ * arg0 == RTT address
+ * arg1 == RD address
+ * arg2 == map address
+ * arg3 == level
+ */
+#define RMI_RTT_CREATE SMC64_RMI_FID(U(0xD))
+
+/*
+ * arg0 == RTT address
+ * arg1 == RD address
+ * arg2 == map address
+ * arg3 == level
+ */
+#define RMI_RTT_DESTROY SMC64_RMI_FID(U(0xE))
+
+/*
+ * arg0 == RD address
+ * arg1 == map address
+ * arg2 == level
+ * arg3 == s2tte
+ */
+#define RMI_RTT_MAP_UNPROTECTED SMC64_RMI_FID(U(0xF))
+
+/*
+ * arg0 == RD address
+ * arg1 == map address
+ * arg2 == level
+ * ret1 == level
+ * ret2 == s2tte type
+ * ret3 == s2tte
+ * ret4 == ripas
+ */
+#define RMI_RTT_READ_ENTRY SMC64_RMI_FID(U(0x11))
+
+/*
+ * arg0 == RD address
+ * arg1 == map address
+ * arg2 == level
+ */
+#define RMI_RTT_UNMAP_UNPROTECTED SMC64_RMI_FID(U(0x12))
+
+/*
+ * arg0 == calling rec address
+ * arg1 == target rec address
+ */
+#define RMI_PSCI_COMPLETE SMC64_RMI_FID(U(0x14))
+
+/*
+ * arg0 == Feature register index
+ */
+#define RMI_FEATURES SMC64_RMI_FID(U(0x15))
+
+/*
+ * arg0 == RTT address
+ * arg1 == RD address
+ * arg2 == map address
+ * arg3 == level
+ */
+#define RMI_RTT_FOLD SMC64_RMI_FID(U(0x16))
+
+/*
+ * arg0 == RD address
+ */
+#define RMI_REC_AUX_COUNT SMC64_RMI_FID(U(0x17))
+
+/*
+ * arg1 == RD address
+ * arg2 == map address
+ * arg3 == level
+ */
+#define RMI_RTT_INIT_RIPAS SMC64_RMI_FID(U(0x18))
+
+/*
+ * arg0 == RD address
+ * arg1 == REC address
+ * arg2 == map address
+ * arg3 == level
+ * arg4 == ripas
+ */
+#define RMI_RTT_SET_RIPAS SMC64_RMI_FID(U(0x19))
+
+#define GRANULE_SIZE PAGE_SIZE_4KB
+
+/* Maximum number of auxiliary granules required for a REC */
+#define MAX_REC_AUX_GRANULES 16U
+#define REC_PARAMS_AUX_GRANULES 16U
+#define REC_EXIT_NR_GPRS 31U
+/* Size of Realm Personalization Value */
+#define RPV_SIZE 64U
+/* RmiDisposeResponse types */
+#define RMI_DISPOSE_ACCEPT 0U
+#define RMI_DISPOSE_REJECT 1U
+
+/* RmiFeatureLpa2 types */
+#define RMI_NO_LPA2 0U
+#define RMI_LPA2 1U
+
+/* RmiInterfaceVersion type */
+#define RMI_MAJOR_VERSION 0U
+#define RMI_MINOR_VERSION 0U
+
+/* RmiRealmMeasurementAlgorithm types */
+#define RMI_HASH_SHA_256 0U
+#define RMI_HASH_SHA_512 1U
+
+/* RmiRecEmulatedMmio types */
+#define RMI_NOT_EMULATED_MMIO 0U
+#define RMI_EMULATED_MMIO 1U
+
+/*
+ * RmiRecExitReason represents the reason for a REC exit.
+ * This is returned to NS hosts via RMI_REC_ENTER::run_ptr.
+ */
+#define RMI_EXIT_SYNC 0U
+#define RMI_EXIT_IRQ 1U
+#define RMI_EXIT_FIQ 2U
+#define RMI_EXIT_PSCI 3U
+#define RMI_EXIT_RIPAS_CHANGE 4U
+#define RMI_EXIT_HOST_CALL 5U
+#define RMI_EXIT_SERROR 6U
+#define RMI_EXIT_INVALID 0xFFFFFU
+
+/* RmiRecRunnable types */
+#define RMI_NOT_RUNNABLE 0U
+#define RMI_RUNNABLE 1U
+
+/* RttEntryState: represents the state of an RTTE */
+#define RMI_UNASSIGNED 0U
+#define RMI_DESTROYED 1U
+#define RMI_ASSIGNED 2U
+#define RMI_TABLE 3U
+#define RMI_VALID_NS 4U
+
+#define RMI_FEATURE_REGISTER_0_S2SZ GENMASK(7, 0)
+#define RMI_FEATURE_REGISTER_0_LPA2 BIT(8)
+#define RMI_FEATURE_REGISTER_0_SVE_EN BIT(9)
+#define RMI_FEATURE_REGISTER_0_SVE_VL GENMASK(13, 10)
+#define RMI_FEATURE_REGISTER_0_NUM_BPS GENMASK(17, 14)
+#define RMI_FEATURE_REGISTER_0_NUM_WPS GENMASK(21, 18)
+#define RMI_FEATURE_REGISTER_0_PMU_EN BIT(22)
+#define RMI_FEATURE_REGISTER_0_PMU_NUM_CTRS GENMASK(27, 23)
+#define RMI_FEATURE_REGISTER_0_HASH_SHA_256 BIT(28)
+#define RMI_FEATURE_REGISTER_0_HASH_SHA_512 BIT(29)
+
+#define RMM_FEATURE_MIN_IPA_SIZE 32U
+#define RMM_FEATURE_REGISTER_0_INDEX 0UL
+#define RMM_FEATURE_REGISTER_0_S2SZ_SHIFT 0UL
+#define RMM_FEATURE_REGISTER_0_S2SZ_WIDTH 8UL
+#define RMM_FEATURE_REGISTER_0_LPA2_SHIFT 8UL
+#define RMM_FEATURE_REGISTER_0_LPA2_WIDTH 1UL
+
+/* RmiStatusCode types */
+/*
+ * Status codes which can be returned from RMM commands.
+ *
+ * For each code, the meaning of return_code_t::index is stated.
+ */
+typedef enum {
+ /*
+ * Command completed successfully.
+ *
+ * index is zero.
+ */
+ RMI_SUCCESS = 0,
+ /*
+ * The value of a command input value caused the command to fail.
+ *
+ * index is zero.
+ */
+ RMI_ERROR_INPUT = 1,
+ /*
+ * An attribute of a Realm does not match the expected value.
+ *
+ * index varies between usages.
+ */
+ RMI_ERROR_REALM = 2,
+ /*
+ * An attribute of a REC does not match the expected value.
+ *
+ * index is zero.
+ */
+ RMI_ERROR_REC = 3,
+ /*
+ * An RTT walk terminated before reaching the target RTT level,
+ * or reached an RTTE with an unexpected value.
+ *
+ * index: RTT level at which the walk terminated
+ */
+ RMI_ERROR_RTT = 4,
+ /*
+ * An operation cannot be completed because a resource is in use.
+ *
+ * index is zero.
+ */
+ RMI_ERROR_IN_USE = 5,
+ RMI_ERROR_COUNT
+} status_t;
+
+#define RMI_RETURN_STATUS(ret) ((ret) & 0xFF)
+#define RMI_RETURN_INDEX(ret) (((ret) >> 8U) & 0xFF)
+#define RTT_MAX_LEVEL 3U
+#define ALIGN_DOWN(x, a) ((uint64_t)(x) & ~(((uint64_t)(a)) - 1ULL))
+#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a)-1U)) == 0U)
+#define PAGE_SHIFT FOUR_KB_SHIFT
+#define RTT_LEVEL_SHIFT(l) XLAT_ADDR_SHIFT(l)
+#define RTT_L2_BLOCK_SIZE (1UL << RTT_LEVEL_SHIFT(2U))
+
+#define REC_CREATE_NR_GPRS 8U
+#define REC_HVC_NR_GPRS 7U
+#define REC_GIC_NUM_LRS 16U
+
+/*
+ * The error code 0x201 is the packed version of the
+ * rmm error {RMM_STATUS_ERROR_INPUT,2U}
+ * happened when Granule(params_ptr).pas != NS
+ */
+#define RMM_STATUS_ERROR_INPUT 0x201UL
+
+/*
+ * The Realm attribute parameters are shared by the Host via
+ * RMI_REALM_CREATE::params_ptr. The values can be observed or modified
+ * either by the Host or by the Realm.
+ */
+struct rmi_realm_params {
+ /* Realm feature register 0 */
+ SET_MEMBER(u_register_t features_0, 0, 0x100); /* Offset 0 */
+ /* Measurement algorithm */
+ SET_MEMBER(unsigned char hash_algo, 0x100, 0x400); /* 0x100 */
+ /* Realm Personalization Value */
+ SET_MEMBER(unsigned char rpv[RPV_SIZE], 0x400, 0x800); /* 0x400 */
+ SET_MEMBER(struct {
+ /* Virtual Machine Identifier */
+ unsigned short vmid; /* 0x800 */
+ /* Realm Translation Table base */
+ u_register_t rtt_base; /* 0x808 */
+ /* RTT starting level */
+ long rtt_level_start; /* 0x810 */
+ /* Number of starting level RTTs */
+ unsigned int rtt_num_start; /* 0x818 */
+ }, 0x800, 0x1000);
+};
+
+/*
+ * The REC attribute parameters are shared by the Host via
+ * MI_REC_CREATE::params_ptr. The values can be observed or modified
+ * either by the Host or by the Realm which owns the REC.
+ */
+struct rmi_rec_params {
+ /* Flags */
+ SET_MEMBER(u_register_t flags, 0, 0x100); /* Offset 0 */
+ /* MPIDR of the REC */
+ SET_MEMBER(u_register_t mpidr, 0x100, 0x200); /* 0x100 */
+ /* Program counter */
+ SET_MEMBER(u_register_t pc, 0x200, 0x300); /* 0x200 */
+ /* General-purpose registers */
+ SET_MEMBER(u_register_t gprs[REC_CREATE_NR_GPRS], 0x300, 0x800); /* 0x300 */
+ SET_MEMBER(struct {
+ /* Number of auxiliary Granules */
+ u_register_t num_aux; /* 0x800 */
+ /* Addresses of auxiliary Granules */
+ u_register_t aux[MAX_REC_AUX_GRANULES]; /* 0x808 */
+ }, 0x800, 0x1000);
+};
+
+/*
+ * Structure contains data passed from the Host to the RMM on REC entry
+ */
+struct rmi_rec_entry {
+ /* Flags */
+ SET_MEMBER(u_register_t flags, 0, 0x200); /* Offset 0 */
+ /* General-purpose registers */
+ SET_MEMBER(u_register_t gprs[REC_EXIT_NR_GPRS], 0x200, 0x300); /* 0x200 */
+ SET_MEMBER(struct {
+ /* GICv3 Hypervisor Control Register */
+ u_register_t gicv3_hcr; /* 0x300 */
+ /* GICv3 List Registers */
+ u_register_t gicv3_lrs[REC_GIC_NUM_LRS]; /* 0x308 */
+ }, 0x300, 0x800);
+};
+
+/*
+ * Structure contains data passed from the RMM to the Host on REC exit
+ */
+struct rmi_rec_exit {
+ /* Exit reason */
+ SET_MEMBER(u_register_t exit_reason, 0, 0x100);/* Offset 0 */
+ SET_MEMBER(struct {
+ /* Exception Syndrome Register */
+ u_register_t esr; /* 0x100 */
+ /* Fault Address Register */
+ u_register_t far; /* 0x108 */
+ /* Hypervisor IPA Fault Address register */
+ u_register_t hpfar; /* 0x110 */
+ }, 0x100, 0x200);
+ /* General-purpose registers */
+ SET_MEMBER(u_register_t gprs[REC_EXIT_NR_GPRS], 0x200, 0x300); /* 0x200 */
+ SET_MEMBER(struct {
+ /* GICv3 Hypervisor Control Register */
+ u_register_t gicv3_hcr; /* 0x300 */
+ /* GICv3 List Registers */
+ u_register_t gicv3_lrs[REC_GIC_NUM_LRS]; /* 0x308 */
+ /* GICv3 Maintenance Interrupt State Register */
+ u_register_t gicv3_misr; /* 0x388 */
+ /* GICv3 Virtual Machine Control Register */
+ u_register_t gicv3_vmcr; /* 0x390 */
+ }, 0x300, 0x400);
+ SET_MEMBER(struct {
+ /* Counter-timer Physical Timer Control Register */
+ u_register_t cntp_ctl; /* 0x400 */
+ /* Counter-timer Physical Timer CompareValue Register */
+ u_register_t cntp_cval; /* 0x408 */
+ /* Counter-timer Virtual Timer Control Register */
+ u_register_t cntv_ctl; /* 0x410 */
+ /* Counter-timer Virtual Timer CompareValue Register */
+ u_register_t cntv_cval; /* 0x418 */
+ }, 0x400, 0x500);
+ SET_MEMBER(struct {
+ /* Base address of pending RIPAS change */
+ u_register_t ripas_base; /* 0x500 */
+ /* Size of pending RIPAS change */
+ u_register_t ripas_size; /* 0x508 */
+ /* RIPAS value of pending RIPAS change */
+ unsigned char ripas_value; /* 0x510 */
+ }, 0x500, 0x600);
+ /* Host call immediate value */
+ SET_MEMBER(unsigned int imm, 0x600, 0x800); /* 0x600 */
+};
+
+/*
+ * Structure contains shared information between RMM and Host
+ * during REC entry and REC exit.
+ */
+struct rmi_rec_run {
+ /* Entry information */
+ SET_MEMBER(struct rmi_rec_entry entry, 0, 0x800); /* Offset 0 */
+ /* Exit information */
+ SET_MEMBER(struct rmi_rec_exit exit, 0x800, 0x1000); /* 0x800 */
+};
+
+struct rtt_entry {
+ uint64_t walk_level;
+ uint64_t out_addr;
+ int state;
+};
+
+enum realm_state {
+ REALM_STATE_NULL,
+ REALM_STATE_NEW,
+ REALM_STATE_ACTIVE,
+ REALM_STATE_SYSTEM_OFF
+};
+
+struct realm {
+ u_register_t par_base;
+ u_register_t par_size;
+ u_register_t rd;
+ u_register_t rtt_addr;
+ u_register_t rec;
+ u_register_t run;
+ u_register_t num_aux;
+ u_register_t rmm_feat_reg0;
+ u_register_t ipa_ns_buffer;
+ u_register_t ns_buffer_size;
+ u_register_t aux_pages[REC_PARAMS_AUX_GRANULES];
+ enum realm_state state;
+};
+
+/* RMI/SMC */
+u_register_t rmi_version(void);
+u_register_t rmi_granule_delegate(u_register_t addr);
+u_register_t rmi_granule_undelegate(u_register_t addr);
+u_register_t rmi_realm_create(u_register_t rd, u_register_t params_ptr);
+u_register_t rmi_realm_destroy(u_register_t rd);
+u_register_t rmi_features(u_register_t index, u_register_t *features);
+
+/* Realm management */
+u_register_t realm_map_protected_data_unknown(struct realm *realm,
+ u_register_t target_pa,
+ u_register_t map_size);
+u_register_t realm_create(struct realm *realm);
+u_register_t realm_map_payload_image(struct realm *realm,
+ u_register_t realm_payload_adr);
+u_register_t realm_map_ns_shared(struct realm *realm,
+ u_register_t ns_shared_mem_adr,
+ u_register_t ns_shared_mem_size);
+u_register_t realm_rec_create(struct realm *realm);
+u_register_t realm_activate(struct realm *realm);
+u_register_t realm_destroy(struct realm *realm);
+u_register_t realm_rec_enter(struct realm *realm, u_register_t *exit_reason,
+ unsigned int *test_result);
+u_register_t realm_init_ipa_state(struct realm *realm,
+ u_register_t level,
+ u_register_t start,
+ uint64_t end);
+
+
+#endif /* HOST_REALM_RMI_H */
diff --git a/include/runtime_services/host_realm_managment/host_shared_data.h b/include/runtime_services/host_realm_managment/host_shared_data.h
new file mode 100644
index 0000000..9c9cc8c
--- /dev/null
+++ b/include/runtime_services/host_realm_managment/host_shared_data.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef HOST_SHARED_DATA_H
+#define HOST_SHARED_DATA_H
+
+#include <stdint.h>
+#include <spinlock.h>
+
+#define MAX_BUF_SIZE 10240U
+#define MAX_DATA_SIZE 5U
+
+/*
+ * This structure maps the shared memory to be used between the Host and Realm
+ * payload
+ */
+typedef struct host_shared_data {
+ /* Buffer used from Realm for logging*/
+ uint8_t log_buffer[MAX_BUF_SIZE];
+
+ /* Command set from Host and used by Realm*/
+ uint8_t realm_cmd;
+
+ /* array of params passed from Host to Realm*/
+ u_register_t host_param_val[MAX_DATA_SIZE];
+
+ /* array of output results passed from Realm to Host*/
+ u_register_t realm_out_val[MAX_DATA_SIZE];
+
+ /* Lock to avoid concurrent accesses to log_buffer */
+ spinlock_t printf_lock;
+} host_shared_data_t;
+
+/*
+ * Different commands that the Host can requests the Realm to perform
+ */
+enum realm_cmd {
+ REALM_SLEEP_CMD = 1U,
+ REALM_GET_RSI_VERSION
+};
+
+/*
+ * Index values for each parameter in the host_param_val array.
+ */
+enum host_param_index {
+ HOST_CMD_INDEX = 0U,
+ HOST_SLEEP_INDEX
+};
+/*
+ * Return shared buffer pointer mapped as host_shared_data_t structure
+ */
+host_shared_data_t *host_get_shared_structure(void);
+/*
+ * Set data to be shared from Host to realm
+ */
+void realm_shared_data_set_host_val(uint8_t index, u_register_t val);
+
+/*
+ * Set guest mapped shared buffer pointer
+ */
+void realm_set_shared_structure(host_shared_data_t *ptr);
+
+/*
+ * Get guest mapped shared buffer pointer
+ */
+host_shared_data_t *realm_get_shared_structure(void);
+
+/*
+ * Set data to be shared from Realm to Host
+ */
+void realm_shared_data_set_realm_val(uint8_t index, u_register_t val);
+
+/*
+ * Return Host's data at index
+ */
+u_register_t realm_shared_data_get_host_val(uint8_t index);
+
+/*
+ * Return Realm's data at index
+ */
+u_register_t realm_shared_data_get_realm_val(uint8_t index);
+
+/*
+ * Clear shared realm data
+ */
+void realm_shared_data_clear_realm_val(void);
+
+/*
+ * Clear shared Host data
+ */
+void realm_shared_data_clear_host_val(void);
+
+/*
+ * Get command sent from Host to realm
+ */
+uint8_t realm_shared_data_get_realm_cmd(void);
+
+/*
+ * Set command to be send from Host to realm
+ */
+void realm_shared_data_set_realm_cmd(uint8_t cmd);
+
+#endif /* HOST_SHARED_DATA_H */
diff --git a/include/runtime_services/host_realm_managment/realm_def.h b/include/runtime_services/host_realm_managment/realm_def.h
new file mode 100644
index 0000000..22cd380
--- /dev/null
+++ b/include/runtime_services/host_realm_managment/realm_def.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef REALM_DEF_H
+#define REALM_DEF_H
+
+#include <xlat_tables_defs.h>
+
+/* 1mb for Realm payload as a default value*/
+#define REALM_MAX_LOAD_IMG_SIZE U(0x100000)
+#define REALM_STACK_SIZE 0x1000U
+#define DATA_PATTERN_1 0x12345678U
+#define DATA_PATTERN_2 0x11223344U
+#define REALM_SUCCESS 0U
+#define REALM_ERROR 1U
+
+/* Only support 4KB at the moment */
+
+#if (PAGE_SIZE == PAGE_SIZE_4KB)
+#define PAGE_ALIGNMENT PAGE_SIZE_4KB
+#define TCR_TG0 TCR_TG0_4K
+#else
+#error "Undefined value for PAGE_SIZE"
+#endif
+
+#endif /* REALM_DEF_H */
diff --git a/include/runtime_services/host_realm_managment/rmi_spm_tests.h b/include/runtime_services/host_realm_managment/rmi_spm_tests.h
new file mode 100644
index 0000000..11c8c12
--- /dev/null
+++ b/include/runtime_services/host_realm_managment/rmi_spm_tests.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef REALM_PAYLOAD_TEST_H
+#define REALM_PAYLOAD_TEST_H
+
+#define NUM_GRANULES 5U
+#define NUM_RANDOM_ITERATIONS 7U
+#define B_DELEGATED 0U
+#define B_UNDELEGATED 1U
+#define NUM_CPU_DED_SPM PLATFORM_CORE_COUNT / 2U
+
+#endif /* REALM_PAYLOAD_TEST_H */
diff --git a/include/runtime_services/realm_payload/realm_payload_test.h b/include/runtime_services/realm_payload/realm_payload_test.h
deleted file mode 100644
index 048dda1..0000000
--- a/include/runtime_services/realm_payload/realm_payload_test.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <smccc.h>
-#include <tftf_lib.h>
-
-#define RMI_FNUM_MIN_VALUE U(0x150)
-#define RMI_FNUM_MAX_VALUE U(0x18F)
-
-/* Get RMI fastcall std FID from offset */
-#define SMC64_RMI_FID(_offset) \
- ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \
- (SMC_64 << FUNCID_CC_SHIFT) | \
- (OEN_STD_START << FUNCID_OEN_SHIFT) | \
- (((RMI_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \
- << FUNCID_NUM_SHIFT))
-
-/* RMI SMC64 FIDs handled by the RMMD */
-#define RMI_RMM_REQ_VERSION SMC64_RMI_FID(U(0))
-#define SMC_RMM_GRANULE_DELEGATE SMC64_RMI_FID(U(1))
-#define SMC_RMM_GRANULE_UNDELEGATE SMC64_RMI_FID(U(2))
-#define SMC_RMM_REALM_CREATE SMC64_RMI_FID(U(8))
-#define SMC_RMM_REALM_DESTROY SMC64_RMI_FID(U(9))
-
-#define RMI_ABI_VERSION_GET_MAJOR(_version) ((_version) >> 16)
-#define RMI_ABI_VERSION_GET_MINOR(_version) ((_version) & 0xFFFF)
-
-#define NUM_GRANULES 5
-#define NUM_RANDOM_ITERATIONS 7
-#define GRANULE_SIZE 4096
-
-#define B_DELEGATED 0
-#define B_UNDELEGATED 1
-
-#define NUM_CPU_DED_SPM PLATFORM_CORE_COUNT / 2
-/*
- * The error code 513 is the packed version of the
- * rmm error {RMM_STATUS_ERROR_INPUT,2}
- * happened when Granule(params_ptr).pas != NS
- */
-#define RMM_STATUS_ERROR_INPUT 513UL
-u_register_t realm_version(void);
-u_register_t realm_granule_delegate(uintptr_t);
-u_register_t realm_granule_undelegate(uintptr_t);
-u_register_t realm_create(uintptr_t, uintptr_t);
-u_register_t realm_destroy(uintptr_t);
\ No newline at end of file