)]}' { "log": [ { "commit": "fa267c12f9aa790b43b38d171273cf63892e8d51", "tree": "923258b2252c15b5761c58d8efb1416aaa9c001c", "parents": [ "8a1865cbea3d8fe8bcfcabf1d0c6f3ce3fe38888", "0ed12509aff10b80a4f4092f4a44be81f645a48b" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed May 21 09:46:44 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 21 09:46:44 2025 +0000" }, "message": "Merge \"docs(release): changelog for v2.13 release\"" }, { "commit": "0ed12509aff10b80a4f4092f4a44be81f645a48b", "tree": "923258b2252c15b5761c58d8efb1416aaa9c001c", "parents": [ "8a1865cbea3d8fe8bcfcabf1d0c6f3ce3fe38888" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri May 09 08:51:02 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu May 15 10:23:15 2025 +0000" }, "message": "docs(release): changelog for v2.13 release\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: I7247f50f336dfcfbe62308bd4b6721bc8f9a9fd4\n" }, { "commit": "8a1865cbea3d8fe8bcfcabf1d0c6f3ce3fe38888", "tree": "9a2de9f397be327092dbbf17e6ab1a86ff4b2678", "parents": [ "5ab09e8174e1ec17d6b1c35483f268e0775a5b67", "d72394d0965829a319701247ac8522c365f9e55d" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri May 02 12:09:20 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 02 12:09:20 2025 +0000" }, "message": "Merge changes from topic \"xlnx_versal2_tftf_base\"\n\n* changes:\n fix(versal2): update test skip list\n fix(versal2): update tftf and uart base address\n" }, { "commit": "5ab09e8174e1ec17d6b1c35483f268e0775a5b67", "tree": "3be81b31149a1c413293061bd39d41c94d2416e6", "parents": [ "060efe97ff6c31b7dbec96af9fde0b169db4183d", "089c9ad705c1f393d95dd911c76a6772af45d1fd" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "message": "Merge changes from topic \"hm/handoff-mb\"\n\n* changes:\n feat(handoff): add event log test\n feat(measured-boot): add measured boot drivers\n" }, { "commit": "d72394d0965829a319701247ac8522c365f9e55d", "tree": "506d71bf4de98babd4f0a3ee9ac8d2528814d2f8", "parents": [ "7692564d4e05affc177c245884ca160fca57a3ef" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Wed Apr 23 10:51:15 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Mon Apr 28 08:20:26 2025 +0000" }, "message": "fix(versal2): update test skip list\n\nSkipping tests related to invalid entry addresses and system suspend\nwith cores suspended. This will continue until the implementation in\nTF-A is completed to properly handle invalid entry addresses and\nresolve system suspend failures.\nAdditionally, skipping tests for FFA Group0 in the normal world since\nFFA support is not available.\n\nChange-Id: Icc62f563ffb0321f7cdc2e7399a3c3b6c908d778\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "7692564d4e05affc177c245884ca160fca57a3ef", "tree": "4efc4526184a55be45988545ff43e6dc0ba70865", "parents": [ "060efe97ff6c31b7dbec96af9fde0b169db4183d" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Wed Apr 23 10:37:01 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Mon Apr 28 08:20:22 2025 +0000" }, "message": "fix(versal2): update tftf and uart base address\n\nUpdate TFTF base address as per new DDR address map along\nwith default console base address set to Uart1.\n\nChange-Id: I4dddee2e01984a4fcef1d86ad9a92aff3baaa961\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "089c9ad705c1f393d95dd911c76a6772af45d1fd", "tree": "1842ee9a2fabfe773b56c98a76bb7e831b26b5a0", "parents": [ "b674809e4d937d44f85ef53aa2bdbb9f74b569b2" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:54 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:37 2025 +0000" }, "message": "feat(handoff): add event log test\n\nAdds a new TFTF test to validate presence and correctness of the TPM\nevent log in the transfer list received from EL3. Uses event_log_dump to\nparse and output log data.\n\nChange-Id: I0b1f782429e4bfe3d1760fce52d40a9836dc27a2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "b674809e4d937d44f85ef53aa2bdbb9f74b569b2", "tree": "3192a0624448d4503cb3679f0d939cb7c169ac22", "parents": [ "19620adc7cbcae26cc432a28a9c3b0944957cf13" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:03 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:25 2025 +0000" }, "message": "feat(measured-boot): add measured boot drivers\n\nIntroduces core measured boot support, including TPM event log handling,\nhashing infrastructure, and event formatting per TCG spec. The driver is\nimported from the existing implementation in TF-A.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: Ib2e6a88c86f110f9a6907c3e6dbb0dc736486de9\n" }, { "commit": "060efe97ff6c31b7dbec96af9fde0b169db4183d", "tree": "bc0e18f218d5facba2ae30222dad21bc7f5f3bbd", "parents": [ "336f1c20beba190b912a83756ca91626b2860c14", "2230a5955d328b4a018e72163482690892f5ff59" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Apr 25 16:18:55 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 25 16:18:55 2025 +0200" }, "message": "Merge changes from topic \"fix_pmuv3p9_test\"\n\n* changes:\n feat(ras): add RAS system registers access test\n fix(smccc): availability test: add two features and fix TRNDR\n" }, { "commit": "336f1c20beba190b912a83756ca91626b2860c14", "tree": "9e8bc8ed7479036cf408fa4e88ea354a007ca817", "parents": [ "19620adc7cbcae26cc432a28a9c3b0944957cf13", "06de4bf32ac7a605946ed6af1ea2c51756fc43c4" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Apr 25 16:17:17 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 25 16:17:17 2025 +0200" }, "message": "Merge \"fix(pauth): test an actual ARMv8.3 PointerAuth instruction\"" }, { "commit": "19620adc7cbcae26cc432a28a9c3b0944957cf13", "tree": "aab0fcf5b25e67b5873ec6b69b479aae7a998c3c", "parents": [ "6186cf96b9713be1a7cb7badd7166203b6145793", "2373cbb8ace3d400d2bd0f336507219ae926ae36" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Apr 23 11:58:13 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Apr 23 11:58:13 2025 +0200" }, "message": "Merge \"fix(versal-net): check ttc irq status\"" }, { "commit": "6186cf96b9713be1a7cb7badd7166203b6145793", "tree": "b003e74f5d98b31f0581a3d85f7babcad255aedd", "parents": [ "aeb5c5ccb10a569c258d2b3e24841da4d234d3df", "6cd8b7d4a7d4d2177f5b51827e9d75321e2a9f90" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Apr 22 17:45:33 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Apr 22 17:45:33 2025 +0200" }, "message": "Merge \"test(trp): test el3-rmm ide km interface\"" }, { "commit": "2373cbb8ace3d400d2bd0f336507219ae926ae36", "tree": "63bc19ed2f7bca762ae165804feba211391d3697", "parents": [ "aeb5c5ccb10a569c258d2b3e24841da4d234d3df" ], "author": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Tue Apr 01 15:18:18 2025 +0530" }, "committer": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Mon Apr 21 12:16:51 2025 +0530" }, "message": "fix(versal-net): check ttc irq status\n\nContinuous interrupts are observed after cancel timer operation\nas proper cleanup is not done in cancel timer routine.\nProvide proper cleanup in cancel timer routine by reading the\nttc interrupt status register for cause of interrupt and disabling\nthe ttc counter by setting bit 0 in ttc counter control register.\nValue of per-cpu hypervisor timer interrupt id is set to 26 in\naccordance with arm documentation and reference for same is present in\narm juno and nvidia settings.\n\nChange-Id: I4f19314deaec9fa05b6fcbe04d0192e3c2a1a772\nSigned-off-by: Amit Nagal \u003camit.nagal@amd.com\u003e\n" }, { "commit": "aeb5c5ccb10a569c258d2b3e24841da4d234d3df", "tree": "6d08225409590233f1757d2c32d08220df9300a3", "parents": [ "d06a6f50017d79d67be8c8742ad578963a089024", "b319e455fb8cdaf24d5623cb0617dd496839bb95" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Apr 16 12:26:41 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Apr 16 12:26:41 2025 +0200" }, "message": "Merge changes from topic \"shewan01/tftf-nrd1-deprecation\"\n\n* changes:\n feat(neoverse_rd): deprecate and remove NRD1 platform includes\n feat(neoverse_rd): deprecate and remove RD-V1 platform variants\n feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants\n feat(neoverse_rd): deprecate and remove SGI-575 platform\n" }, { "commit": "b319e455fb8cdaf24d5623cb0617dd496839bb95", "tree": "6d08225409590233f1757d2c32d08220df9300a3", "parents": [ "5179144894ba1c30dfa6befc90eaac8b93839840" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Apr 15 11:36:56 2025 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Apr 16 09:53:05 2025 +0100" }, "message": "feat(neoverse_rd): deprecate and remove NRD1 platform includes\n\nAs NRD1 platforms have been removed, remove common includes for\nNRD1 platforms.\n\nChange-Id: I0805fc135837b2257b51d9a21dd678178b5df8e2\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "5179144894ba1c30dfa6befc90eaac8b93839840", "tree": "aeacb613100d73dd07d647398ca0cb6d520af6ff", "parents": [ "dc4235a917f6e7b4981a5de027e05f2bc8875d4d" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Apr 15 11:34:50 2025 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Apr 16 09:52:57 2025 +0100" }, "message": "feat(neoverse_rd): deprecate and remove RD-V1 platform variants\n\ndeprecate and remove support for RD-V1 and RD-V1-MC platform variants.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I59003ae3a6b3ea0f603f3282c31efc37d312e1fd\n" }, { "commit": "dc4235a917f6e7b4981a5de027e05f2bc8875d4d", "tree": "2c99e6ab6fe0d92af43331cb79ec58b36355fbfb", "parents": [ "d685f8cfd3cf66a64e2afa0f36a217f7f1a461e0" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Apr 15 11:34:22 2025 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Apr 16 09:52:48 2025 +0100" }, "message": "feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants\n\ndeprecate and remove support for RD-N1-Edge and RD-N1-Edgex2 platform\nvariants.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I2b00f3550c8ef0f4d80236d856d644762881eba3\n" }, { "commit": "d685f8cfd3cf66a64e2afa0f36a217f7f1a461e0", "tree": "e91b03d14edc19304132d85ded19ea1aad2087df", "parents": [ "d06a6f50017d79d67be8c8742ad578963a089024" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Apr 15 11:30:08 2025 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Apr 16 09:52:38 2025 +0100" }, "message": "feat(neoverse_rd): deprecate and remove SGI-575 platform\n\ndeprecate and remove support for SGI-575 platform.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: Ia86236155c3185991841ebd05851ac0bfb84ada2\n" }, { "commit": "d06a6f50017d79d67be8c8742ad578963a089024", "tree": "51a91085b7eaabda482d15ae21b9f3e8f846d89d", "parents": [ "caafd5d6e5f6ac5e8760da20ec9d44bfbc016c90", "b33efce3672b335803a1a2ed4a279640b6deb00f" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Apr 11 19:20:11 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 11 19:20:11 2025 +0200" }, "message": "Merge \"docs: update toolchain requirements to 14.2.Rel1\"" }, { "commit": "caafd5d6e5f6ac5e8760da20ec9d44bfbc016c90", "tree": "e46a2cbaba245a68f17c37e32af0df852c331705", "parents": [ "f6f797b92f41b6850a8289e279c55c6f30563ec4", "112498c703d48dceea63fe7ab88a8b243513e7e8" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Apr 10 18:28:26 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 10 18:28:26 2025 +0200" }, "message": "Merge \"feat(handoff): add AArch32 handoff support\"" }, { "commit": "6cd8b7d4a7d4d2177f5b51827e9d75321e2a9f90", "tree": "8f0136a08fbd66642f159d206ac71c65ea6b2bb4", "parents": [ "118652bf8a430b3085b9b79c589e12d8f80c1113" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Mon Mar 31 17:14:46 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Apr 10 14:54:10 2025 +0200" }, "message": "test(trp): test el3-rmm ide km interface\n\nThis patch introduces a new test function that invokes\nPDEV_CREATE on TRP and tests the RMM-EL3 IDE KM interface\nimplemented in EL3.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: Ib7e9e769191f94927b55b099a8c80d40ffc2a756\n" }, { "commit": "112498c703d48dceea63fe7ab88a8b243513e7e8", "tree": "e46a2cbaba245a68f17c37e32af0df852c331705", "parents": [ "f6f797b92f41b6850a8289e279c55c6f30563ec4" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Feb 18 11:52:12 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Apr 10 09:56:36 2025 +0000" }, "message": "feat(handoff): add AArch32 handoff support\n\nAdd support for testing firmware handoff in AArch32 mode. This requires\nsome tweaks to enable the boot args from TF-A to be stashed for later\nuse.\n\nChange-Id: Ib1b88688b6229b10020c936319605c7ed6307ca2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "f6f797b92f41b6850a8289e279c55c6f30563ec4", "tree": "52c27c14788dcd39671f0643f7ea92d107adeb7d", "parents": [ "118652bf8a430b3085b9b79c589e12d8f80c1113", "a1709e0063b271f723790ce9f74a6b2afd2760c4" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Apr 10 09:50:52 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 10 09:50:52 2025 +0200" }, "message": "Merge \"fix(sme): synchronize context before using it\"" }, { "commit": "118652bf8a430b3085b9b79c589e12d8f80c1113", "tree": "bcd5345a199468d52c44de61e38b43c6e675664b", "parents": [ "6d9e106780746a3248901b93f9a334d28eef4e5e", "69a9c4027085d4331f54aa1cc753626749812168" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Apr 08 20:50:56 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Apr 08 20:50:56 2025 +0200" }, "message": "Merge \"feat(mbedtls): update mbedtls to version 3.6.3\"" }, { "commit": "69a9c4027085d4331f54aa1cc753626749812168", "tree": "bcd5345a199468d52c44de61e38b43c6e675664b", "parents": [ "6d9e106780746a3248901b93f9a334d28eef4e5e" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Mon Apr 07 13:18:19 2025 -0500" }, "committer": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Mon Apr 07 13:20:33 2025 -0500" }, "message": "feat(mbedtls): update mbedtls to version 3.6.3\n\nUpdate additional mbedtls submodule to version 3.6.3.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I69814f9a5e7e0c260169111a7ec1dd42dbc3679c\n" }, { "commit": "a1709e0063b271f723790ce9f74a6b2afd2760c4", "tree": "a695a04db22a4bbf49be39a4ba665f893d73f3ad", "parents": [ "6d9e106780746a3248901b93f9a334d28eef4e5e" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Apr 07 09:41:26 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Apr 07 16:00:17 2025 +0100" }, "message": "fix(sme): synchronize context before using it\n\nWe need to wait for the write to cptr_el2 to take effect to consider SME\nenabled. Otherwise, the write to smcr_el2 may fault. Add an isb() to\nsynchronize this.\n\nChange-Id: Ib1fb1803bad2d4fb9e89bc4861e2e611b9882b2e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "6d9e106780746a3248901b93f9a334d28eef4e5e", "tree": "f94fbed4d910a3688fa888f5452a337c38b0fb3b", "parents": [ "0de678ef3e7136af91b314c893030311741a7f80", "d5bb5f6c82f7ebcf28dccbbfad058e27e207c14f" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Apr 04 20:16:58 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 04 20:16:58 2025 +0200" }, "message": "Merge \"feat(mbedtls): update mbedtls to version 3.6.3\"" }, { "commit": "06de4bf32ac7a605946ed6af1ea2c51756fc43c4", "tree": "237951fe262707336610b6d026fea666360df891", "parents": [ "0de678ef3e7136af91b314c893030311741a7f80" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Apr 04 13:29:35 2025 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Apr 04 17:27:06 2025 +0100" }, "message": "fix(pauth): test an actual ARMv8.3 PointerAuth instruction\n\nThe PAuth instruction test promises to test instructions associated with\nFEAT_PAUTH, though actually just issues those that are located in the\nNOP space, so would always execute, even on machines without FEAT_PAUTH.\n\nReplace them with one instruction that is newly defined by FEAY_PAUTH,\nand that would trigger an UNDEF abort if not implemented or would trap\nto EL3 unless SCR_EL3.API is set.\n\nChange-Id: Iece2c60af40800450dadf5b2db609c35cfa6cf95\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "b33efce3672b335803a1a2ed4a279640b6deb00f", "tree": "c066ccd58e5e45c4367333b61fc7b2d55cc0c0f5", "parents": [ "0de678ef3e7136af91b314c893030311741a7f80" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Apr 04 15:55:24 2025 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Apr 04 15:56:16 2025 +0100" }, "message": "docs: update toolchain requirements to 14.2.Rel1\n\nTF-A tests have been validated with toolchain version 14.2.Rel1.\nUpdate documentation to reflect this as the current supported version.\n\nChange-Id: I304a0ce11cab23c5047c9ed772fd53af58a21ac7\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "0de678ef3e7136af91b314c893030311741a7f80", "tree": "03cc016c0059ab0d53ba9880a008a78634a0febe", "parents": [ "a864222f08cc068d6659fa3bedbe322578513d60", "11e574835b289bc3c9742d76ea697a53023527bc" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Apr 04 15:40:59 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 04 15:40:59 2025 +0200" }, "message": "Merge changes from topic \"mp/cpu_off_broadcast\"\n\n* changes:\n test: deny prohibited ABIs while handling CPU_OFF psci msg\n feat: add build flag to control support for CPU_OFF psci msg\n feat(cactus): receive psci msg through direct req framework msg\n" }, { "commit": "a864222f08cc068d6659fa3bedbe322578513d60", "tree": "c1db5fe9b4ca52ca86fcaf77ac45c89e404187bd", "parents": [ "78fb528d0e2ecb53c533f6accf0da1f90d289353", "de873bbd54a58f751553ebd42b302a348ca342a7" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Apr 04 11:57:53 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 04 11:57:53 2025 +0200" }, "message": "Merge \"fix(rme): fix position of RTT_S2AP_INDIRECT bit in RmiFeatureRegister0\"" }, { "commit": "d5bb5f6c82f7ebcf28dccbbfad058e27e207c14f", "tree": "16cd4e4315d2b0f0599a93746efee17eddba924e", "parents": [ "78fb528d0e2ecb53c533f6accf0da1f90d289353" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 03 12:49:06 2025 -0500" }, "committer": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 03 14:10:06 2025 -0500" }, "message": "feat(mbedtls): update mbedtls to version 3.6.3\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I4bfb546c351c30a6fc4d22f29bc03efad316df7d\n" }, { "commit": "de873bbd54a58f751553ebd42b302a348ca342a7", "tree": "c1db5fe9b4ca52ca86fcaf77ac45c89e404187bd", "parents": [ "78fb528d0e2ecb53c533f6accf0da1f90d289353" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Apr 03 11:02:36 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Apr 03 11:02:36 2025 +0100" }, "message": "fix(rme): fix position of RTT_S2AP_INDIRECT bit in RmiFeatureRegister0\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I514368fe64834324fd4ea2b98e9b175dba20288c\n" }, { "commit": "11e574835b289bc3c9742d76ea697a53023527bc", "tree": "4671e58c1aef29334f69dec38de3b4ded5aa05ed", "parents": [ "a2b6b37ed6eaf7d0f9dfc12a04499863b25cf559" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 28 11:46:16 2025 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 01 13:19:18 2025 -0500" }, "message": "test: deny prohibited ABIs while handling CPU_OFF psci msg\n\nFF-A spec states that SPs are prohibited from invoking Direct request,\nFFA_RUN and FFA_YIELD interfaces while handling power management\nframework message. Make the Cactus SP intentionally invoke prohibited\ninterfaces and attest that SPMC should deny such invocations.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I0a823bf950e3895cb4aff7320c6a0ef7fdec634b\n" }, { "commit": "a2b6b37ed6eaf7d0f9dfc12a04499863b25cf559", "tree": "0aed9c7638a65d443bdfaf6c38639184085d1d55", "parents": [ "611d095453cf001e436f795ac8209b27f46a2fdb" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Feb 11 15:39:32 2025 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 01 13:19:15 2025 -0500" }, "message": "feat: add build flag to control support for CPU_OFF psci msg\n\nPlease check the inline comments for detailed description of the\nnew build flag. This flag will help us to create a negative test\nscenario where we can exercise sending DENIED response to SPMC,\nultimately leading to a panic by SPMD.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I30d2ea7f3fbf09e4e4febceb85f045e25f3e6035\n" }, { "commit": "611d095453cf001e436f795ac8209b27f46a2fdb", "tree": "2435b48f94395c106adc5529e5031ccd92ca3197", "parents": [ "78fb528d0e2ecb53c533f6accf0da1f90d289353" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jan 31 16:07:08 2025 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 01 13:07:09 2025 -0500" }, "message": "feat(cactus): receive psci msg through direct req framework msg\n\nCactus receives PSCI CPU_OFF power management operation message\nthrough framework direct request message and it will respond back\nwith framework direct message if all conditions are met.\n\nCactus SP1 and SP2 explicitly subscribe to CPU_OFF power management\nmessage through their respective manifests.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I790a8698d238e29847e376b4fa9447a6241ef17e\n" }, { "commit": "78fb528d0e2ecb53c533f6accf0da1f90d289353", "tree": "c95b395d55d04f234c968909d6483fb356c8f251", "parents": [ "677708401f13bfa0c9d974aff8e3db3f67b77c5a", "a35c1db92b51bb785acef300975919bbb0a69aca" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Apr 01 14:51:10 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Apr 01 14:51:10 2025 +0200" }, "message": "Merge \"fix(tests): undelegate pdev granules if DA ABI fails\"" }, { "commit": "a35c1db92b51bb785acef300975919bbb0a69aca", "tree": "c95b395d55d04f234c968909d6483fb356c8f251", "parents": [ "677708401f13bfa0c9d974aff8e3db3f67b77c5a" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Apr 01 12:14:25 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Apr 01 12:14:25 2025 +0100" }, "message": "fix(tests): undelegate pdev granules if DA ABI fails\n\nIn host_tdi_pdev_setup undelegate pdev and aux granules upon error\nso that the next testcase in the list doesn\u0027t encounter failure.\n\nThis issue is seen when RMM is build with RMM_V1_1\u003dON and DA ABI\nSMC_RMI_PDEV_AUX_COUNT fails.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I97614dbe7c41b89ff8b72db8cfb178d3c6067249\n" }, { "commit": "677708401f13bfa0c9d974aff8e3db3f67b77c5a", "tree": "9aa226627feb27c793ecb2894519550e18dadfd5", "parents": [ "41567dc5c36eb7cb0c621cc801e99543e95093b3", "8205a64846d581937e77919a9fe858db53324a84" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Mar 31 16:28:02 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 31 16:28:02 2025 +0200" }, "message": "Merge changes from topic \"km/ffa_features\"\n\n* changes:\n refactor: refactor `get_ffa_feature_test_target`\n refactor: use an enum for FF-A errors\n" }, { "commit": "8205a64846d581937e77919a9fe858db53324a84", "tree": "77b786526b95ab4219225966828b847eaf2546ab", "parents": [ "af77b16df26371cf954fd410359f55981683d1ea" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jun 19 15:05:19 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Mar 31 11:43:01 2025 +0100" }, "message": "refactor: refactor `get_ffa_feature_test_target`\n\nChange `get_ffa_feature_test_target` to return a `size_t` instead of an\n`unsigned int`, because `size_t` is the return type of operators like\n`sizeof()`.\n\nChange `get_ffa_feature_test_target` to require its argument to be\nnon-null (and assert that it is). This function is only used for getting\nthe array of features to test, so there is no use case where passing a\nnon-null pointer would make sense.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I33597f1a2f7681eda59ece08062e48c28752c111\n" }, { "commit": "af77b16df26371cf954fd410359f55981683d1ea", "tree": "620d8dae4e9d64c4001962eb05ee89b677b08ca8", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jun 19 10:44:54 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Mar 31 11:43:01 2025 +0100" }, "message": "refactor: use an enum for FF-A errors\n\nChange-Id: Id30f36840e0668daa152ab90a2559fade7883c5f\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "41567dc5c36eb7cb0c621cc801e99543e95093b3", "tree": "1d0620e5b07b525e656d82ea22e7aefedba7f6a7", "parents": [ "8993e8ec7c66a849dad48f7b57e866cc40de3191", "43ad50d798007af9d607898597d30bf215d3aa05" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Mar 31 11:35:55 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 31 11:35:55 2025 +0200" }, "message": "Merge \"feat(rme): update FEAT_MPAM tests on Realms\"" }, { "commit": "43ad50d798007af9d607898597d30bf215d3aa05", "tree": "1d0620e5b07b525e656d82ea22e7aefedba7f6a7", "parents": [ "8993e8ec7c66a849dad48f7b57e866cc40de3191" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Mar 28 17:37:04 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Mar 28 17:47:36 2025 +0000" }, "message": "feat(rme): update FEAT_MPAM tests on Realms\n\nCurrently, to test that accessing a FEAT_MPAM register from a Realm\ncauses an undefined abort injected back to the Realm, we only test\nby accessing a single register.\n\nThis patches updates the test by trying to access all MPAM registers\nfrom the Realm to validate that an undefined abort is taken to the\nRealm for all the registers.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I16c88d467eb2a49342694536a1c7b6358416dc34\n" }, { "commit": "8993e8ec7c66a849dad48f7b57e866cc40de3191", "tree": "891b504323eff7bb91489d10ae33ed84613a15c3", "parents": [ "ab680e816552ea29184084482fdf63e2f94cd46a", "2ba1e7812b494abdfb8f440a161f0ded24bee72a" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Mar 27 09:40:19 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 27 09:40:19 2025 +0100" }, "message": "Merge \"fix(errata_abi): update Cortex-A710 errata list\"" }, { "commit": "2ba1e7812b494abdfb8f440a161f0ded24bee72a", "tree": "891b504323eff7bb91489d10ae33ed84613a15c3", "parents": [ "ab680e816552ea29184084482fdf63e2f94cd46a" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Mar 26 16:50:18 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Mar 26 17:15:06 2025 -0500" }, "message": "fix(errata_abi): update Cortex-A710 errata list\n\nThis patch updates the out-of-date parameter of Cortex-A710\u0027s\n2058056 erratum in Errata ABI test.\n\nChange-Id: I194eb7fea0504b532c2e15710fbe4b455b7e631b\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "ab680e816552ea29184084482fdf63e2f94cd46a", "tree": "8e10eed6f9d1169da2c006f4d017ebe4dcafa4ea", "parents": [ "9d84ad1ceb8256e942213537602c6434577b7bc0", "2bd104e2fc8bdf1355ae88ad3e16af9773c1541f" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Mar 25 05:17:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 25 05:17:06 2025 +0100" }, "message": "Merge \"fix(realm): Fix the LPA2 flag setting for BRBE test\"" }, { "commit": "2bd104e2fc8bdf1355ae88ad3e16af9773c1541f", "tree": "8e10eed6f9d1169da2c006f4d017ebe4dcafa4ea", "parents": [ "9d84ad1ceb8256e942213537602c6434577b7bc0" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Fri Mar 21 15:35:27 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Mar 25 04:49:16 2025 +0100" }, "message": "fix(realm): Fix the LPA2 flag setting for BRBE test\n\nThis patch fixes the LPA2 flag setting for BRBE test.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: Id7c53739cc92275a7018a44c2a3b8fdcf74ec25e\n" }, { "commit": "9d84ad1ceb8256e942213537602c6434577b7bc0", "tree": "f1069ac2c0ef008601b2892cae5960fba6665787", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "fb96b980c85d916b55c78b7d22e5b6d8e086ca54" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "message": "Merge changes from topic \"kc/fuzz\"\n\n* changes:\n test(fuzz): add FF-A fuzzing\n test(fuzz): Fix single feature testing\n" }, { "commit": "fb96b980c85d916b55c78b7d22e5b6d8e086ca54", "tree": "2a4c319dd3761099924e160acca59d4075bf749d", "parents": [ "2b6c140b52790beebbb921dd0311efefb0bb0c5c" ], "author": { "name": "Kathleen Capella", "email": "katcap01@u203721.austin.arm.com", "time": "Thu Apr 25 17:09:33 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Mar 11 12:10:59 2025 -0500" }, "message": "test(fuzz): add FF-A fuzzing\n\nAdd necessary components for FF-A calls to be used in fuzzing framework\nincluding bias tree, `run_ffa_fuzz` helper function, makefile additions,\nand initial SMC description file with FF-A smc calls.\n\nCan use ffa_smc_calls.txt to generate necessary header files.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ib19714342d31cacd818471686a7e4c8910fed5c3\n" }, { "commit": "2230a5955d328b4a018e72163482690892f5ff59", "tree": "7ac3698bb9d614af35f74999fc42f4ffee5d7ee3", "parents": [ "37e3f3e1d237b6e8289fbc0a090b2b4dd2d4b9ec" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 17:19:34 2025 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 17:30:44 2025 +0000" }, "message": "feat(ras): add RAS system registers access test\n\nFEAT_RAS introduces EL1 system registers to query error records, those\nCPU specific parts of the RAS extension can be accessed independently of\nany FFH/KFH handling setup or any system specific RAS implementation.\n\nAdd a test to verify that those registers can be read, when the CPUID\nfield advertises the MPAM (CPU) extension.\n\nChange-Id: I7429fc815e7e0ee0cd736603966969b2cfb5f469\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "37e3f3e1d237b6e8289fbc0a090b2b4dd2d4b9ec", "tree": "43448a6e0d637e635d482b1abf2144f0d7dda046", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Mar 07 17:25:24 2025 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 15:04:03 2025 +0000" }, "message": "fix(smccc): availability test: add two features and fix TRNDR\n\nThe SMCCC_ARCH_FEATURE_AVAILABILITY test was not up-to-date and was\nmissing two features: FEAT_TWED and FEAT_PMUV3P9. Connect the SCR_EL3\nand MDCR_EL3 bits to their corresponding ID register fields, so that\nthey can be tested.\n\nAt the same time the FEAT_RNG_TRAP test was slightly off: the SMCCC spec\nsays it should report accessibility of the RNDR and RNDRRS registers, so\nwe should look at FEAT_RNG, not FEAT_RNG_TRAP when checking the TRNDR\nbit.\n\nThis fixes the tf-a-tests run on an FVP with ARMv9.4 enabled, which was\nreporting the following issues before:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\u003e Executing \u0027SMCCC_ARCH_FEATURE_AVAILABILITY test\u0027\n TEST COMPLETE Failed\nis_feat_rng_trap_present says feature is supported but SCR_TRNDR_BIT was\n\tnot set!\nSCR_EL3 still has values set: 0x20000000. Test needs to be updated\nMDCR_EL3 still has values set: 0x80. Test needs to be updated\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nChange-Id: I73a0d240b2cd1a16e1c64d3d66ee30e658c9c946\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "tree": "a0ec5b6bff32d2fa1294f33af597c0d54558306e", "parents": [ "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "c8f5a2ee90f2b376da910f08170af4c4dc7396ae" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "message": "Merge \"test: test the save restore logic for brbcr_el1\"" }, { "commit": "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "tree": "62adf8c4bbb438943acb6e46b52170803509a17b", "parents": [ "3d43731d485b1405c5a224f65a7c2d381d46b093", "43980f9070347622ec9b9ff1b360357a954e96f2" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Sun Mar 09 01:28:21 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sun Mar 09 01:28:21 2025 +0100" }, "message": "Merge \"test(realm): Fix Realm tests marking all memory as RAM\"" }, { "commit": "2b6c140b52790beebbb921dd0311efefb0bb0c5c", "tree": "333ef24bffd0e8a85ea998f3ae2da4c3b8c83047", "parents": [ "3d43731d485b1405c5a224f65a7c2d381d46b093" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Mar 06 10:01:19 2025 -0600" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Fri Mar 07 15:57:39 2025 -0600" }, "message": "test(fuzz): Fix single feature testing\n\n This change fixes an issue where a user provides a new feature\nthat can be fuzzed independently of the current setup of fuzzing.\nCurrently compile fails will cause issues if single feature fuzzing\nis desired and the automated flow will disable sets that are not in\nthe SMC description file. There are some small changes to the source\nfiles to enable this behavior for both SDEI and Vendor. There is also\na change to the automated scripting.\n\nChange-Id: Ic768e9f1b285225f12f23c1e36acb668088ad129\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\n" }, { "commit": "43980f9070347622ec9b9ff1b360357a954e96f2", "tree": "64495265719ce7b62c47bc5f720d88eec5ee15e9", "parents": [ "90506fbda56864b578980bc2d433f2ba38207e61" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Mar 07 20:35:21 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Mar 07 20:35:21 2025 +0000" }, "message": "test(realm): Fix Realm tests marking all memory as RAM\n\nRealm tests only need access to part of DRAM.\nChange only required region RIPAS to RAM.\n\nChange-Id: Ia0120841e51726785062992e8a32dcd8a924a325\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "3d43731d485b1405c5a224f65a7c2d381d46b093", "tree": "c8d15de87f5a5155e57a145d43cbeb18c118f33f", "parents": [ "9b63fa56b4e21ecb87d409c6a95d1d3d5ee06376", "5668f34a89dfcee72c2a8e6aa443c7436f341d61" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "message": "Merge \"fix: add split workaround check in Errata ABI test\"" }, { "commit": "9b63fa56b4e21ecb87d409c6a95d1d3d5ee06376", "tree": "7fc7ec71d57eec9732f6793a5ed15d3e2b354824", "parents": [ "90506fbda56864b578980bc2d433f2ba38207e61", "55d5db87b83b6a073ed3c954d455b862e7b2e7fe" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Mar 07 11:06:37 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 07 11:06:37 2025 +0100" }, "message": "Merge changes Ic57f049d,Ifc98b8c6,I7e34a007,I20cbb9d0\n\n* changes:\n test(realm): extend ripas tests for planes\n test(realm): enhance realm memory exception tests for planes\n test(realm): add test for multi rec planes\n test(realm): validate NS EL1/EL2 context is preserved by RMM\n" }, { "commit": "c8f5a2ee90f2b376da910f08170af4c4dc7396ae", "tree": "625509a3d6d8838e0c31c9e89fbf23ed9361d15f", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Tue Feb 04 15:22:01 2025 -0600" }, "committer": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Mar 06 16:55:05 2025 -0600" }, "message": "test: test the save restore logic for brbcr_el1\n\nThis patch tests the save/restore logic by enabling\nbranch recording at NS-EL2. Additionally this\npatch also tests the trap logic when FEAT_FGT is enabled\nand a Realm tries to access any FEAT_BRBE related registers.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I176ea6feaf01d42cfd6231dc65a9470da8d1e37c\n" }, { "commit": "55d5db87b83b6a073ed3c954d455b862e7b2e7fe", "tree": "0019d75c61f3cbac06bc2f1e25d5944c8f9f3880", "parents": [ "7d3b999376c7416584639411f36bdadf877060d3" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Mar 03 12:56:04 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 21:08:59 2025 +0000" }, "message": "test(realm): extend ripas tests for planes\n\nTest that accessing page with RIPAS\u003dEMPTY from\nPlane N causes plane exit to P0.\n\nChange-Id: Ic57f049d0fa0140630aa7bfc0702a2dc729967a8\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "90506fbda56864b578980bc2d433f2ba38207e61", "tree": "b77200b91f6f52038c3754cc14fc2896d407f149", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120", "b3d451c3bb4b3b6c6a03aaaa8e1a785c5a4ca0a5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Mar 06 21:39:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 06 21:39:06 2025 +0100" }, "message": "Merge \"fix: add xpaci instruction to exception report\"" }, { "commit": "7d3b999376c7416584639411f36bdadf877060d3", "tree": "c22c6390ab2ec7977af1483c1d4dbf56bd2d388f", "parents": [ "bd729193dcdb19a5f5fa9b259770f1d1f365bad0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 25 15:39:55 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 19:50:15 2025 +0000" }, "message": "test(realm): enhance realm memory exception tests for planes\n\nExtend memory exception tests for planes.\n\nChange-Id: Ifc98b8c67e85b04b36a78f16971d17f05d6a87d2\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "5668f34a89dfcee72c2a8e6aa443c7436f341d61", "tree": "9a7778183d2dedaa383e4c517a4a17dae6a7fa49", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Mar 04 02:01:16 2025 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Mar 06 12:43:08 2025 -0600" }, "message": "fix: add split workaround check in Errata ABI test\n\nThis patch adds support to validate split workarounds\nas part of Errata ABI CPU Features testcase. It also\nimproves the test case, making sure it also\nruns on lead cpu.\n\nChange-Id: Ic21fffdf20714ad639e92ad0be96d2f154f37f04\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "bd729193dcdb19a5f5fa9b259770f1d1f365bad0", "tree": "00c47d7308aee2d02a16a3d4a5fbacaf7cf4407d", "parents": [ "78effaa2c47b04abd68273bdea4ebb4f6f9455c0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 24 17:02:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:57:56 2025 +0000" }, "message": "test(realm): add test for multi rec planes\n\nTest exercises SMC_PSCI_CPU_ON from aux plane.\nRequest is first routed to P0 and then to Host.\nHost enters P0 and then P1 on all CPUs.\n\nChange-Id: I7e34a0070ffa7305b97a0d93de62b64042771a18\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "78effaa2c47b04abd68273bdea4ebb4f6f9455c0", "tree": "9ffb7b9430ee5600da7f8e0cd5cd557752ea85fa", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 07 10:30:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:18:01 2025 +0000" }, "message": "test(realm): validate NS EL1/EL2 context is preserved by RMM\n\n- Test validates that NS EL1/EL2 registers are preserved while\n entering and exiting realm world.\n- Test validates that accessing s2por_el1 in realm causes data abort.\n\nChange-Id: I20cbb9d0d59474507f89ee7cf8e127fff4706610\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "992c62b427ad7fc425ec3c02e6c2f5e98e94d120", "tree": "1267fde5c9244b900105a5d2d073c4d938ef7e0d", "parents": [ "3e496b408634030405c5fa5fbcb8b8babcebfb30", "eb2dd23469c8a5f3624b60ce21fab8299785fe4e" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 05 20:46:05 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 05 20:46:05 2025 +0100" }, "message": "Merge changes from topic \"kc/stmm\"\n\n* changes:\n refactor: move StMM to cactus tertiary\n feat(hob): add boot-time prints for cactus-stmm HOB list\n refactor(cactus): map boot information regions\n feat(hob): add HOB definitions to TFTF\n feat(spm): add STMM cactus partition\n" }, { "commit": "b3d451c3bb4b3b6c6a03aaaa8e1a785c5a4ca0a5", "tree": "4f962c5a8e86e12e0bdd0526bbb59dda55efe9b7", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Feb 13 14:24:06 2025 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Mar 04 10:37:16 2025 -0600" }, "message": "fix: add xpaci instruction to exception report\n\nWhen reporting an exception with ENABLE_PAUTH\u003d\u003d1 calling xpaci\nbefore printing the ELR value will remove the PAC and make the\npointer readable.\n\nChange-Id: I45339dbb3396f403768ea3ee780d0c5010da44c4\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "3e496b408634030405c5fa5fbcb8b8babcebfb30", "tree": "730acf129621c21de4c680668a5b8391446f74b1", "parents": [ "6164898b4355bf1f311a78f0796a75baf7f50983", "dc26dfe297eaed205fdbf8a0f98706044a97032d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Feb 28 14:41:46 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 28 14:41:46 2025 +0100" }, "message": "Merge changes I701d7f7f,If85b8c4c\n\n* changes:\n test(realm): fix bug in RMI_RTT_SET_S2AP command helper\n test(realm): add support for s2poe/pie for planes\n" }, { "commit": "dc26dfe297eaed205fdbf8a0f98706044a97032d", "tree": "730acf129621c21de4c680668a5b8391446f74b1", "parents": [ "de01b5dd3ae940a16ad9f370ad1e734190553e73" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 25 16:12:48 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 28 13:01:34 2025 +0000" }, "message": "test(realm): fix bug in RMI_RTT_SET_S2AP command helper\n\npass correct rec adr to RMI_RTT_SET_S2AP command.\nRSI_MEM_SET_PERM_INDEX can be called from any rec.\n\nChange-Id: I701d7f7f9de80f305d10d2582c614b3090fc2ac5\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "de01b5dd3ae940a16ad9f370ad1e734190553e73", "tree": "9dcf2ef13e4449a8322e044da38a1ed94579e171", "parents": [ "6164898b4355bf1f311a78f0796a75baf7f50983" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 02 21:17:11 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 28 13:01:16 2025 +0000" }, "message": "test(realm): add support for s2poe/pie for planes\n\nAdd support for s2poe/pie for planes.\nUpdate planes test to run with s2poe/s2pie\nboth enabled and disabled.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If85b8c4cff9e8fe43978088beaf848fe4b2b9a40\n" }, { "commit": "6164898b4355bf1f311a78f0796a75baf7f50983", "tree": "858cebc6186fb65cc28fc02883dec4a112534603", "parents": [ "42dd088203e40911c67106d46cfccde58d55e1b5", "716c8cc0951fb6a3e212d4bd9b79ea0b6f9bdf9b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 26 13:15:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 26 13:15:06 2025 +0100" }, "message": "Merge \"fix(lib/pcie): bdf macro\"" }, { "commit": "716c8cc0951fb6a3e212d4bd9b79ea0b6f9bdf9b", "tree": "858cebc6186fb65cc28fc02883dec4a112534603", "parents": [ "42dd088203e40911c67106d46cfccde58d55e1b5" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Feb 25 18:22:45 2025 +0000" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Feb 26 11:33:37 2025 +0000" }, "message": "fix(lib/pcie): bdf macro\n\nThe existing PCIE_CREATE_BDF macro is a non standard way of deriving bdf\nvalue. This fix assigns 3 bits for function number, 5 bits for device\nnumber and 8 bits for bus. This bdf value is used as TDISP function id\nwhile passing it to DSM. Using a wrong bdf value results the TDISP\ncommand to fail.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I31301be4dfc9bd2409da73e54715f73079a921cb\n" }, { "commit": "42dd088203e40911c67106d46cfccde58d55e1b5", "tree": "48f1d07ae117eadadd1c0496cc0a8ad895abff3b", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd", "c779d0d0ac9faf894963675dcccb6110e3f0229a" ], "author": { "name": "Sandrine Afsa", "email": "sandrine.afsa@arm.com", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "message": "Merge changes from topic \"xlnx_fix_custom_inval_entry\"\n\n* changes:\n fix(versal): platform definition of invalid entry\n feat(tftf): new interface to get an invalid entrypoint address\n" }, { "commit": "eb2dd23469c8a5f3624b60ce21fab8299785fe4e", "tree": "5e4c4725690951c6339593a72f39466cf6eea1b6", "parents": [ "8808a945590fbc4138c0961717da75ddc383ede0" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Fri Feb 07 18:41:54 2025 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 23:05:23 2025 -0600" }, "message": "refactor: move StMM to cactus tertiary\n\nReuse existing cactus tertiary partition for StMM testing rather than\nadding an additional partition.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I0c40758cc8f5e7cb2239c80346ad785c0d6888e5\n" }, { "commit": "8808a945590fbc4138c0961717da75ddc383ede0", "tree": "992e6e95734b14bddb4dddc924c19122fccc6f69", "parents": [ "8ac4dd8ce81ba17121c62b4d39925ae6b62d7998" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Jan 07 15:45:39 2025 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 23:05:15 2025 -0600" }, "message": "feat(hob): add boot-time prints for cactus-stmm HOB list\n\nAt boot time, print HOB headers and contents.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ic634f045cacdbc8e318836eba85982a93f55fc0f\n" }, { "commit": "8ac4dd8ce81ba17121c62b4d39925ae6b62d7998", "tree": "3508ab1dc7469d12b9df34ab1e1a19f558a8910f", "parents": [ "bde3eab2e68bc0059b5ccfc83a13759287eb9cf4" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Dec 17 19:37:33 2024 +0000" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 13:52:45 2025 -0600" }, "message": "refactor(cactus): map boot information regions\n\nMap the boot contents regions and add optional mapping for boot info\ndescriptor contents depending on whether they will be accessed.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I3dcbff07e9ee33008fa7f64fc74b06a1c42aa5dd\n" }, { "commit": "bde3eab2e68bc0059b5ccfc83a13759287eb9cf4", "tree": "90acb838f69c8c620e7790409df205077a8fe65b", "parents": [ "e8a17a905ca1c20acb1b9248ac725ab847bddc42" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Dec 09 14:04:43 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 13:51:36 2025 -0600" }, "message": "feat(hob): add HOB definitions to TFTF\n\nAdd necessary HOB structure definitions and HOB library to TFTF.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I1a81cd99df52436a077a71030244ca642122497a\n" }, { "commit": "e8a17a905ca1c20acb1b9248ac725ab847bddc42", "tree": "4f6dd3a344ab642adacdbddd6d06a409ee356b8e", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Thu Dec 05 18:28:29 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Fri Feb 21 09:42:27 2025 -0600" }, "message": "feat(spm): add STMM cactus partition\n\nAdd another instance of cactus S-EL1 partition, using\nStMM manifest.\n\nThis is to validate HOB generation at build-time.\n\nThe manifest contains memory region nodes using the\nsame node names as in the StMM partition manifest,\nbut changed the ranges to align with memory map of\nbase FVP. The device region nodes have been dropped,\nas they didn\u0027t affect the creation of the HOB list.\n\nDefined the UUID for the partition in the test code,\nand refactored slightly some of the code paths,\nso it has an RXTX buffer and is able to do the basic\nFF-A setup tests.\n\nAlso added the cactus-stmm node to the sp_layout\nfile.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I05971fc9d63f03bd7ea43b3bcaba5b6362a44ca0\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "c779d0d0ac9faf894963675dcccb6110e3f0229a", "tree": "66a0d99df1847e1ac663da0a378e4d92f3ba63bd", "parents": [ "1e4f7a064f08205a0a37922e660b238be04a8137" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:43:37 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:47 2025 +0000" }, "message": "fix(versal): platform definition of invalid entry\n\nAdd platform specific function to return custom entry address.\n\nChange-Id: I58785a8b7c197e4dae3ac9a29f8d23c29d5cb5e3\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "1e4f7a064f08205a0a37922e660b238be04a8137", "tree": "ccf0e6f9e63ee23a7b249eed564ceedafcee9035", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:40:56 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:16 2025 +0000" }, "message": "feat(tftf): new interface to get an invalid entrypoint address\n\nTFTF test for invalid entry address in cpu hotplug, validates\nfor default entry address 0x0 which doesn\u0027t account for platforms\nfor which 0x0 is a valid address. Added function to retrieve invalid\nentry address for default scenario and platform implementation to\nretrieve specific custom invalid entry address.\n\nChange-Id: I9f109acc8d0443dabd3088cb31852900e8e07853\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "2f2bd013021b4723d42c168f613c4c0ca37223bd", "tree": "968260569451b377582640305eea94d206d9a42c", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e", "af8934c8574fd64bef6ac4b0201c2144b78c8fd7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "message": "Merge \"test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\"" }, { "commit": "af821ebb6fa509f8036b2304c313883842d2c93e", "tree": "d1abf091b8992adae634a55a98ced19523f676f1", "parents": [ "b298a166f8490bb997b794ab404afa5eaae15fa1", "effca4c7db126c7e171256a8a85b60e599274c4d" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Feb 12 18:51:15 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 12 18:51:15 2025 +0100" }, "message": "Merge \"refactor(errata_abi): add Cortex-X925 and update Cortex-X4\"" }, { "commit": "effca4c7db126c7e171256a8a85b60e599274c4d", "tree": "d1abf091b8992adae634a55a98ced19523f676f1", "parents": [ "b298a166f8490bb997b794ab404afa5eaae15fa1" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 16:52:23 2025 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 19:03:22 2025 -0600" }, "message": "refactor(errata_abi): add Cortex-X925 and update Cortex-X4\n\nUpdate errate list for Cortex-X4 and add Cortex-X925\nerratum list and support.\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: Ib4e3324e7289d8e400e9a7f90e384d36cdd8bbcb\n" }, { "commit": "b298a166f8490bb997b794ab404afa5eaae15fa1", "tree": "a185504f6b740a4bfc63fc62f8ee8d91f08d4791", "parents": [ "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "5bccf1d188115e268101024018d26b710c86d3c9" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Feb 06 11:59:13 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 06 11:59:13 2025 +0100" }, "message": "Merge \"fix(realm): fix PMU save/restore registers\"" }, { "commit": "5bccf1d188115e268101024018d26b710c86d3c9", "tree": "a185504f6b740a4bfc63fc62f8ee8d91f08d4791", "parents": [ "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "message": "fix(realm): fix PMU save/restore registers\n\nRemove pmxevcntr_el0 and pmxevtyper_el0 registers\nfrom saving/restoring as aliases for pmevcntrN_el0\nand pmevtyperN_el0, selected by pmselr_el0.sel.\n\nChange-Id: I3def527c46d53c3203f7c3ebc565a2aaf282309c\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "tree": "010803c4d3fb8186d23cfd2f54f923c8271b45cd", "parents": [ "23ec8506918aff276b21b9543831d4825855906d", "82cd82e9868b1f381a5c8d84195657e1583cfca1" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "message": "Merge \"feat(rme): add tests for FEAT_MPAM on Realms\"" }, { "commit": "23ec8506918aff276b21b9543831d4825855906d", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658", "c398c8f7248e9aec29bbc41c94e41005d539863c" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 11:56:02 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 11:56:02 2025 +0100" }, "message": "Merge \"fix(realm): fix realm PMU tests\"" }, { "commit": "82cd82e9868b1f381a5c8d84195657e1583cfca1", "tree": "c7be244d493e784e55df370f501d8c3ba9275523", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jan 17 17:37:42 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Feb 04 15:01:14 2025 +0000" }, "message": "feat(rme): add tests for FEAT_MPAM on Realms\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6e138cbf121793bdaaa3a44824c0dbff74daced1\n" }, { "commit": "c398c8f7248e9aec29bbc41c94e41005d539863c", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jan 16 14:35:48 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Feb 04 11:38:28 2025 +0000" }, "message": "fix(realm): fix realm PMU tests\n\n- FEATURE_PMU_NUM_CTRS field in feature_flag was used\nto pass number of PMU event counters in realm creation.\nThe width of this field was set to 4, which was not\nenough to pass numbers \u003e 15 and was causing PMU tests\nfailures in FVP configuration with more than 15 event\ncounters implemented.\n- This patch removes all FEATURE_XXX macros for setting\nfeature_flag and replaces them with the corresponding\nRMI_FEATURE_REGISTER_0_XXX to match feature register 0.\n- In host_set_pmu_state() function was setting PMSELR_EL0\nto incorrect value 0 instead of 31 to select PMU cycle\ncounter for configurations with no event counters implemented.\n- Test host_realm_pmuv3_mul_rec() was running incorrectly\nwith number of event counters set to 0 or 31.\n- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0\ncan be constrained unpredictable depending on the\nvalue of PMSELR_EL0.SEL and number of accessible event\ncounters. See corresponding TF-RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573\nThis patch fixes host_set_pmu_state() and\nhost_check_pmu_state() functions to avoid unpredictable access\nto these registers.\nThis patch makes Realm PMU tests pass for all possible FVP\nconfigurations clusterN.pmu-num_counters\u003d[0...31].\n\nChange-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "f00a425e1592bd410ff249c1baab8f3b067b1658", "tree": "ec2b7f39414b02fb21446494409ae1729930aaa3", "parents": [ "042541196fbdd814a7c04ee4e24be94f1a2ab4ef", "cd46f276f845a4628982e85dfc38054fc94aa5c3" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Feb 03 15:46:20 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 03 15:46:20 2025 +0100" }, "message": "Merge \"feat: specify the secure partition package for an SP\"" }, { "commit": "042541196fbdd814a7c04ee4e24be94f1a2ab4ef", "tree": "0852b3939e094f0d2fd4b848f3ebb617bfa6efd0", "parents": [ "c8943ba881807922cb84e357461f5482475a47c3", "47078f35247dcb85f5a1ce8ea0bc52d3aee74451" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "message": "Merge changes I7c4ad397,I92e0aeef\n\n* changes:\n test(realm): fix multi rec PMU tests\n test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n" }, { "commit": "c8943ba881807922cb84e357461f5482475a47c3", "tree": "a951dd70d63e29f3616dc48935890f96c8b52fab", "parents": [ "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "message": "Merge changes from topic \"fuzzinit\"\n\n* changes:\n test(fuzz) adding fuzzing for vendor-el3 smccc calls\n test(fuzz) adding fuzzing for all SDEI calls\n test(fuzz): Capability for random inputs\n" }, { "commit": "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c", "tree": "fcf9d81e4b95ffd31ccf36df51df4e1bd0e19221", "parents": [ "0fa7d21bf97d14283ebf8c3df866cd05afaff91e" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jul 23 16:42:16 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 15:13:10 2025 -0600" }, "message": "test(fuzz) adding fuzzing for vendor-el3 smccc calls\n\nChange-Id: I4fd64c0a4c02de6d67a372c9c4bf86bcb9e4d091\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "0fa7d21bf97d14283ebf8c3df866cd05afaff91e", "tree": "b1927aea547dcd718dccc20301cbc301d986faec", "parents": [ "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jun 18 11:17:01 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 14:03:27 2025 -0600" }, "message": "test(fuzz) adding fuzzing for all SDEI calls\n\nadded constraints for all calls\nadded fuzzer feature to start at arbitrary call number\nadded fuzzer features for function exclusion, fuzzer starting/ending call\nworked on additional fuzzing for event_register\n\nChange-Id: I9814b8387ea9e0fb00b53adbdbe0f8429845924e\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "47078f35247dcb85f5a1ce8ea0bc52d3aee74451", "tree": "03562b94399c44ff32b0c1f81d1c8e35016d8e4f", "parents": [ "414346805fa6589643780f6f9ce181facf2e1271" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 16 18:54:24 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 17:44:19 2025 +0000" }, "message": "test(realm): fix multi rec PMU tests\n\n- set different values of PMU event counters for each rec\n- check PMU counters are preserved for each rec\n\nChange-Id: I7c4ad3971d4a10b4515be0dfe096bebf8d903c71\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "tree": "ff6e9cd81f0c19684cf5b58067d02d58f1738b19", "parents": [ "506b98f78e4bb38314129f85da27523f18dd8f8f", "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "message": "Merge changes I7a3b9103,I590fc5a1,Ie6924bcb,I484cbd32\n\n* changes:\n test(realm): add testcase to enter all planes\n test(realm): handle permission fault for planes\n test(realm): add support for planes shared buffer\n test(realm): add plane PSI interface\n" }, { "commit": "af8934c8574fd64bef6ac4b0201c2144b78c8fd7", "tree": "33c29f9b95a29b2b879fc8055d994787b5e79fce", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Fri Jul 26 14:51:14 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Jan 31 16:48:58 2025 +0000" }, "message": "test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\n\n* This patch adds a test that suspends to affinity level 2 with another\n CPU running in a different power domain.\n\n* Previously with the bug identified and resolved in commit (01959a1),\n the function \"psci_is_last_cpu_to_idle_at_pwrlvl\" checked only one\n power domain when suspending to level2. This meant that if there was\n a cpu running outside the power domain of the calling CPU, the suspend\n request would be allowed. But in this case, the request should be\n denied. This test case validates this behaviour and ensures the\n request is denied.\n\n* This patch also adds the following global variables to parameterise\n and reuse the existing functions for the new test.\n * test_should_suspend - an boolean array that allows you to leave\n some CPUs running.\n * test_should_deny - a boolean to specify if the suspend request\n should be denied.\n * cpu_finished - an array of events so that the running CPUs know\n when to terminate.\n\n* Additionally this patch also adds a function to get a CPU that is\n in a different cluster to the lead CPU.\n\nRefer to TF-A commit (01959a1) for more information on the bug.\n\nChange-Id: Ib163aa8d5347baeaa47d1ae6f59599f1c68c11a8\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb", "tree": "506eaf722681380325bde2a5a9de784697915ba9", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Mar 15 12:49:22 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 10:23:24 2025 -0600" }, "message": "test(fuzz): Capability for random inputs\n\nAdding model for random inputs to SMC calls using a\nconstraint mechanism with a multi tiered sanity\nmetric.\n\nChange-Id: Ia750fa57359baa424f1af273ba24483ae7330c38\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "506b98f78e4bb38314129f85da27523f18dd8f8f", "tree": "da255312e5288c911622d83ee21bf8f2cf790a83", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "43d421bb292984fdc56269fb3e87e619ca0892d3" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "message": "Merge \"test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\"" }, { "commit": "414346805fa6589643780f6f9ce181facf2e1271", "tree": "69b825442caff18f8b25d6eee80140c80832d176", "parents": [ "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Dec 05 14:57:48 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 14:53:41 2025 +0000" }, "message": "test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n\ntest for RSI_PLANE_REG_READ/WRITE command\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I92e0aeef48c9b2abe26e5d3b2ea62669a22d4f8b\n" }, { "commit": "158208e895d38d659d216c793d42d132ed90e598", "tree": "86cf20c9982b4b186bcc17944cd9f569701f6fe4", "parents": [ "a0736c3dbf83f3c00ca98c83534070be259fb822" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 10:12:41 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:23 2025 +0000" }, "message": "test(realm): add testcase to enter all planes\n\nTestcase creates realm with all 4 planes.\nEnters all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I7a3b9103e1fbcfe98117c02827624a2fc2d24fc2\n" } ], "next": "a0736c3dbf83f3c00ca98c83534070be259fb822" }