)]}' { "log": [ { "commit": "46d0228e2a1a17c57be8f5011f183ea28e6ba518", "tree": "ce322be37116651bf3ab1d681632c176f8105233", "parents": [ "7c78f7b4a74e58512ff6998f7a5438520e58c343" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Nov 18 16:58:37 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Nov 19 11:22:08 2024 +0100" }, "message": "fix(serror): use custom argument for incrementing elr_elx\n\nAdd a custom argument to increment the elr_elx after handling SError.\nIn some cases, to prevent re-triggering the instruction, ELR needs\nto be incremented by 4. In other cases, it may not be necessary.\n\nThis argument is passed to the handler, which then decides whether\nto increment elr_elx by setting the passed argument accordingly after\nhandling the SError.\n\nChange-Id: I404f3c5e24f894502a8d00c73649be0b2dd540fa\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "7c78f7b4a74e58512ff6998f7a5438520e58c343", "tree": "ea7bd3a6363d1bf5686e5cfbd2a92cabec7a3df6", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Oct 25 11:44:32 2024 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Nov 19 10:10:16 2024 +0000" }, "message": "feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n\nWhen FEAT_DoubleFault2 is supported, TF-RMM must take into\naccount bit SCTLR2_EL1.EASE in order to decide whether to inject\na SEA into the sync exception vector or into the serror one.\n\nThe test on this patch verifies that TF-RMM injects the SEA\nto the right vector depending on SCTLR2.EASE bit.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c976fecb04d123e3efb96c5973b1466e241097f\n" }, { "commit": "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f", "tree": "f8979bc2f589f87671ed5e50216364e64e1dc06d", "parents": [ "a7aa825f328ce0d844f134af8f0cd7468f811d07", "e9c18128b5234f1e76aa0147666d04de61bca93b" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Nov 11 18:48:06 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 11 18:48:06 2024 +0100" }, "message": "Merge \"test: arch timer in nwd is honored across world switch\"" }, { "commit": "4b67210c4ae32e723fc5805f3b7e8c48fb8ec962", "tree": "b5d66c48a39a422a902364d694a41521c35de431", "parents": [ "0db4a3cdde090a94721a8a598cbbbf857f7cf47f" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Sep 23 13:06:15 2024 +0200" }, "committer": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Fri Nov 08 17:48:28 2024 +0100" }, "message": "feat(cm): add test to validate EL2 regs during context switch\n\nVerify that EL2 system registers are preserved when switching\nfrom Normal world to Secure world and vice versa. Do this by\nmodifying the live EL2 register state and dumping it to memory,\nthen performing an FF-A Cactus call and checking whether the\nstate matches the previously saved context.\n\nChange-Id: I0537b4d671c72c0a2fd29ac7e218bf69e1c66001\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "86e5e5d500a839920edcf71783f31b7e4fc20c42", "tree": "c9b96514811730ade3be4cd5449254025502fb07", "parents": [ "af49307617a6861c13008371a1e5397b278bb4c7" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Aug 05 19:52:29 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 16:52:38 2024 +0000" }, "message": "feat(cm): add tests to validate EL1 regs during context switch\n\n* This patch adds a test to verify the integrity of the el1_context\n registers across world-switch.\n\n* It aims at testing the save and restore functionality provided\n by the EL3 context management library.\n\n* It validates the EL1 ctx register entries after interaction with\n TSP (S-EL1) software.\n\nChange-Id: Id435d9d7699231d66e9e7acdbb3459ec439d2aef\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "e9c18128b5234f1e76aa0147666d04de61bca93b", "tree": "0f9061891055da886d987e8245b046d8eaf4288b", "parents": [ "97ee573bf9b34d8d8352b6a8af2f2c47c0f41bf9" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Sep 10 16:28:48 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Nov 06 17:31:31 2024 -0600" }, "message": "test: arch timer in nwd is honored across world switch\n\nThis patch introduces a test to ensure that the functionality of arch\n(EL1 physical) timer configured by NWd endpoint, such as an hypervisor,\nis not corrupted by SPMC when an SP also configures the arch timer for\nits own use.\n\nAlso, necessary helpers and utilities to create the test scenario have\nbeen added.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I1cfd1e1117412b2b23a57af30064c41dc2e66e0b\n" }, { "commit": "72b7ce11edd6042d5a3fe75bba83fb5e7f58ee08", "tree": "6fba961e72767d7a0c58b914acc24723190802a3", "parents": [ "a62262f047c9c48c65021f4e23be7b709e8c2811" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Nov 04 13:44:39 2024 +0000" }, "committer": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Wed Nov 06 21:46:35 2024 +0100" }, "message": "feat(ls64): add LS64_ACCDATA test\n\nFEAT_LS64_ACCDATA introduces the system register ACCDATA_EL1, its value\nreplacing the first four bytes of the data provided to an ST64BV0\ninstruction. As this system register would need context switching\nbetween non-secure and secure worlds, there is an SCR_EL3 bit to allow\ntrapping accesses from lower ELs into EL3.\n\nIntroduce a check to verify that accesses to this system register do not\ntrap into EL3, if the CPUID registers advertise this feature.\nBits[63:32] of ACCDATA_EL1 are described as RES0, so mask those bits\nwhen comparing the read-back values with the written one.\n\nChange-Id: Ia32bcf7187356c701470a1757708b3d554e88629\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "a62262f047c9c48c65021f4e23be7b709e8c2811", "tree": "c9e1bef94457fea688cd23beb3cb694a3f3cb531", "parents": [ "97ee573bf9b34d8d8352b6a8af2f2c47c0f41bf9", "f2f1e27c93581b6a9770b8b70780bcd80b961b24" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Nov 06 21:36:42 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 06 21:36:42 2024 +0100" }, "message": "Merge \"feat(tcr2): add asymmetric feature testing for FEAT_TCR2\"" }, { "commit": "97ee573bf9b34d8d8352b6a8af2f2c47c0f41bf9", "tree": "a6b003f7f9c39f43d3441cb2fbf20870daa80f7d", "parents": [ "a948c86a529c14b98214915d291ed997096836e8", "357177b52669038f8748789de0f2c4ba39e8d09a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Nov 06 11:32:24 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 06 11:32:24 2024 +0100" }, "message": "Merge \"fix(realm): fix host_realm_init_ipa_state()\u0027s retry path\"" }, { "commit": "357177b52669038f8748789de0f2c4ba39e8d09a", "tree": "9f76b4e859037498025b749b4960a0b6ddd303b7", "parents": [ "205400d4e105efde03c993cee10defdaf3190504" ], "author": { "name": "pedro martelletto", "email": "martelletto@google.com", "time": "Mon Nov 04 10:41:31 2024 +0000" }, "committer": { "name": "pedro martelletto", "email": "martelletto@google.com", "time": "Wed Nov 06 06:55:38 2024 +0000" }, "message": "fix(realm): fix host_realm_init_ipa_state()\u0027s retry path\n\nmake sure to initialise the IPA state after creating RTTs and before\nreturning success.\n\nChange-Id: I47da3b0cd343c86567c1c38ebd08a50e1129c455\nSigned-off-by: pedro martelletto \u003cmartelletto@google.com\u003e\n" }, { "commit": "bd2fd4e8d3923d46e3e8ee68f591eaaff2ed07e3", "tree": "6f643f4af1de221d2738a3b0d3092c909aa52105", "parents": [ "80354938c1384a9238b9056ad9f3468defc5d49b" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Oct 15 11:31:54 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 05 10:17:39 2024 +0000" }, "message": "test(memory share): SPMC handles GPF in FFA_MEM_FRAG_RX\n\nAttest SPMC can handle a GPF when handling a FFA_MEM_FRAG_RX.\nThe FFA_MEM_FRAG_RX accesses to a NWd RX buffer, during the\na multi-fragment retrieve request.\nThe SPMC should handle the GPF, and smoothly return\nFFA_ERROR_ABORTED to the NWd.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Id2116755beddb9350f84155ea4a358de679ac780\n" }, { "commit": "80354938c1384a9238b9056ad9f3468defc5d49b", "tree": "9bd76349090a2c961e34647714278a3cd8249a5e", "parents": [ "c362de3e39acb112b466212713476e367ba509d2" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Oct 15 11:24:27 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 05 10:17:39 2024 +0000" }, "message": "refactor: hypervisor retrieve request helpers\n\nFactored out of hypervisor_retrieve_request the looping\npart, for retrieving the fragments of a fragmented\nretrieve request. This is to aid testing hypervisor retrieve\nrequest, when it faults in the middle of the operation.\n\nAlso added two helpers to access the size of a fragment\nand the total size for both ABIs:\n- FFA_MEM_RETRIEVE_RESP.\n- FFA_MEM_FRAG_TX.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I49d12d69eff8c132b0a29954772dd6634f590f88\n" }, { "commit": "c362de3e39acb112b466212713476e367ba509d2", "tree": "a5dc47ab586d6eb0a5ec3535b262a003eb9b6dae", "parents": [ "205400d4e105efde03c993cee10defdaf3190504" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jun 20 12:50:14 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 05 10:17:23 2024 +0000" }, "message": "test(SPM): GPF during FFA_MEM_FRAG_TX\n\nTest that the SPMC recovers from a GPF when handling\nFFA_MEM_FRAG_TX interface.\n\nChange-Id: I5b98419b32cdfd26431b461aede96e88d238b78b\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "205400d4e105efde03c993cee10defdaf3190504", "tree": "88d8cddd6a8f5aee6924bb857e624319d0373b85", "parents": [ "a0c8d3f504eab3ea929ef669bc746ae5a8daa2ef", "dadd2e26e3edb16903c0e5679a4388f2202537a8" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Oct 31 18:31:44 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 31 18:31:44 2024 +0100" }, "message": "Merge \"Revert \"fvp: skip cpu cluster power-on check\"\"" }, { "commit": "f855e9fa002d8bfe25d72e726f16098190076e53", "tree": "1dabc799480b69a2ba571f9b3505da95c3d2001f", "parents": [ "d551d093073f0c5ca808eaed6076f2f62bd336fa" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:11:47 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:33:19 2024 +0000" }, "message": "fix(ff-a): report FFA_YIELD support for SPs only\n\nThe FFA_YIELD interface is only valid at the virtual\nFF-A instace, and not at the physical FF-A instance.\nI.e. SPs can use the ABI with SMC conduit into the SPMC.\nThe NWd is not expected to call FFA_YIELD into SPMC.\n\nThis patch drops FFA_YIELD from the common test target\nfor FFA_FEATURES between tftf and cactus/ivy partitions,\nadds the specific tests to both of them with expected\ndifferences.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I7d9a5729b82f3f2f77631a8ab6210fa026078d7d\n" }, { "commit": "d551d093073f0c5ca808eaed6076f2f62bd336fa", "tree": "dc4ea52bfc57413f3640bb5e410a8cc1f121e933", "parents": [ "fd43af6083438eca1540ff58468f0173da1350ff" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:09:47 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:09:47 2024 +0000" }, "message": "fix(ff-a): reporting support of indirect messaging\n\nHafnium was not reporting the support of indirect messaging\nor direct messaging 2, added in FF-A v1.1 and FF-A v1.2,\nrespectively, in the returned information of the ABI\nFFA_PARTITION_INFO_GET. The patch [1] fixes this issue.\n\nThis patch makes equivalent change to the arguments expected\nfor the FFA_PARTITION_INFO_GET return on cactus partitions.\n\n[1] https://review.trustedfirmware.org/c/hafnium/hafnium/+/31712\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I29ef51a7566a09b6fbeada55725d571f0440fbcd\n" }, { "commit": "fd43af6083438eca1540ff58468f0173da1350ff", "tree": "d49a4388a0f99d2b0ea4b2e55c2aa11f9e623e20", "parents": [ "37a5034e1c96dffd897e7231d406fccb3131aa8d", "951376bb0e8af291cc412be9460e4195692fbd87" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Oct 29 12:10:22 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 29 12:10:22 2024 +0100" }, "message": "Merge changes from topic \"xlnx_plat_versal2\"\n\n* changes:\n docs(versal2): add AMD Versal Gen 2 documentation\n feat(versal2): add support for AMD Versal Gen 2 platform\n" }, { "commit": "f2f1e27c93581b6a9770b8b70780bcd80b961b24", "tree": "e3f021e5f5f1af491df4544fc00fc1e433d9e6f8", "parents": [ "37a5034e1c96dffd897e7231d406fccb3131aa8d" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Sep 03 11:49:51 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Oct 24 11:19:43 2024 +0100" }, "message": "feat(tcr2): add asymmetric feature testing for FEAT_TCR2\n\nChange-Id: I07b27ff58ccf471ccc43643141e2dfe70083fd13\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "9601dc5343d4aee267a5adcebeb2495f395acc4d", "tree": "ba51882deb7e44d3b0832904d0ef0ca61b8c871b", "parents": [ "70de3ff58e06f66819e98a25a9167c6751f87330" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Wed Aug 28 17:27:18 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "feat: skip asymmetric tests when features not present\n\nThis patch skips asymmetric tests, when features are not present\nand will split them into separate tests.\n\nThe problem with the previous test structure was that you can\u0027t\ndistinguish between a trap to EL2 and an undef injection. This meant\nthat on some platforms, the tests would pass even without the\nasymmetric support patches. In these cases, it would be better if the\ntest was skipped, since there\u0027s no situation where it fails.\n\nFor example, if FEAT_SPE wasn\u0027t present on any cores, and the\nasymmetric support patches weren\u0027t applied, then the test would pass.\nThis is because the register accesses would trap to EL2.\n\nThis patch skips the test on every core that doesn\u0027t have the feature\nimplemented. It also splits the test into separate test functions.\nThis allows us to display a separate test result for each asymmetric\ntest. It also allows us to skip the whole test if the feature isn\u0027t\npresent on any cores, since in these cases the test would always pass.\n\nThe structure of the test is similar to\ntftf/tests/runtime_services/standard_service/psci/api_tests/cpu_suspend/test_suspend.c.\nThe run_asymmetric_test function takes a function as an argument, and\nruns it on all CPUs.\n\nThe whole test should only be skipped if the test was skipped on all\nCPUs. The test on each CPU can\u0027t return TEST_RESULT_SKIPPED, because\nthe whole test is skipped if any of the CPUs return\nTEST_RESULT_SKIPPED. Instead, to skip a test, the test returns\nTEST_RESULT_SUCCESS, then sets a flag in the test_skipped array. This\narray is checked at the end by the run_asymmetric_test function.\n\nChange-Id: I802431714de3eb8b059e8fc56f7e19fc94e3e8fb\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "70de3ff58e06f66819e98a25a9167c6751f87330", "tree": "2823ae213e5f1a81ffbc15db0e3a8c1f508ad941", "parents": [ "4397e4444950fcb138122d5fa047fc2250fcc375" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Tue Aug 20 11:27:25 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "refactor: clarify which kind of exceptions it catches\n\nThe function that was called \"undef_injection_handler\" doesn\u0027t just\ncatch undef injections. It also catches traps to EL2 due to registers\nnot being present. Both cases have the same EC value, so it is\nimpossible to distinguish between them.\n\nThis patch edits variable names and adds a comment to clarify this.\n\nChange-Id: Ie7405d7611afc1d2ff2207cfa4a08de3cbc9dff7\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "4397e4444950fcb138122d5fa047fc2250fcc375", "tree": "b8e9c43197838f4128523feda90644836e5085e5", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Tue Aug 20 10:17:38 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "refactor: only register undef_injection_handler during register accesses\n\nBefore, the undef_injection_handler was registered at the start of the\ntest, and unregistered at the end. This patch makes it so the\nundef_injection_handler is only registered where a register is being\naccessed. This gives us more control in which exceptions we catch.\n\nChange-Id: I4262288543cac6b1f9ab0e6fd5092d7e3a31fb75\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "7dbb6c110477adaca32d3afce88135ec76dac6e7", "tree": "26bd19cda1226669eb5c8abe0e5b4995fcb606be", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Oct 04 03:22:30 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Oct 22 04:39:42 2024 +0000" }, "message": "feat(versal2): add support for AMD Versal Gen 2 platform\n\nIntroduce platform support for AMD Versal Gen 2.\n\nSummary:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 194\nTests Passed : 29\nTests Failed : 0\nTests Crashed : 0\nTotal tests : 223\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nNOTICE: Exiting tests.\n\nChange-Id: I608dd556be402f97f9960c688b7d0caa6f17c5c3\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nSigned-off-by: Michal Simek \u003cmichal.simek@amd.com\u003e\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "dadd2e26e3edb16903c0e5679a4388f2202537a8", "tree": "6f931efd4b82f48ffedde56e79997aa466a96ea9", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Oct 16 22:25:58 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Oct 17 16:29:19 2024 +0200" }, "message": "Revert \"fvp: skip cpu cluster power-on check\"\n\nThis reverts commit 11f6ee85b015635021083db0f494a2c2957566ef.\nThis now addressed through a TF-A patch -\nhttps://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/31902\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: Icea0cefb93723343586e5b3a57a2c9b90a9bf5c6\n" }, { "commit": "0db147aecaec8d10aff6103d038dc149710b25f7", "tree": "b21bf750fe12bc45bc707d1665459a088db4e8ef", "parents": [ "93d4df58e20da38742613eb1fe2fe401289aeaf2" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 16:46:35 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 17:06:06 2024 +0100" }, "message": "feat(realm_payload): use random start REC\n\nThis patch modifies tests below\nhost_test_realm_create_enter\nhost_test_multiple_realm_create_enter\nhost_realm_multi_rec_single_cpu\nto start Realm execution with a random REC number.\n\nChange-Id: I5961f953efc4dab25d301a7026d0c3949701df4a\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "93d4df58e20da38742613eb1fe2fe401289aeaf2", "tree": "2de78b803f816449d34ce2ec0f869be3dcbd7ffb", "parents": [ "2fe9ef36da3f6d0b2a02423f7892739129c6a3b2" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 09:44:52 2024 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 17:57:08 2024 +0200" }, "message": "feat(realm_payload): increase maximum number of RECs\n\nThis patch changes maximum number of RECs per realm\nMAX_REC_COUNT from 8 to 17. This makes possible to\ntest calculation of REC\u0027s linear index from RmiRecMpidr\ntype which has [7:4] SBZ.\n\nChange-Id: I9ab3d94f25b263b2672012ccbd6e632265a2a745\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "5467cb50ac44eb4d3248c0cf70eaf1fd6a034c8b", "tree": "1e35ba50c44808b5b946e98fd32aa02c4723b7b3", "parents": [ "19cfac8b0cbbc1dfffc58f28a4cacb925eb4c8c9" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Oct 02 18:21:43 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 07:14:34 2024 +0200" }, "message": "fix(realm): cater for removal of SH from rtte\n\nThe RMM v1.0 REL specification removes the SH field from host_controlled\nparameters. Fix up TFTF for this change.\n\nChange-Id: Id032d4555da4b200bb9a355085b8a7f0709884fb\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "19cfac8b0cbbc1dfffc58f28a4cacb925eb4c8c9", "tree": "0ac8d741cacb43841f8d2a4263bb9b03ed1624c3", "parents": [ "9a60ecbf209d2faf117420b9013c52216106d157" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Aug 30 16:36:42 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 01 16:55:17 2024 +0100" }, "message": "feat(realm): set number of num_bps and num_wps\n\nAs per RMM Specification number of breakpoints and\nwatchpoints passed to RMI_REALM_CREATE cannot be 0.\nThese values are passed to host_prepare_realm_payload()\nin feature_flag parameter fields which are set to 0\nby default by callers to this function.\nThis patch modifies the logic for setting num_bps\nand num_wps Realm parameters to avoid 0 values.\n\nChange-Id: Ib5420db959866620005c404c494c4ec1904b010c\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "3a137fc469a3241cfda137975dd8c9805331023b", "tree": "9dc78c63eb41d008e8c161917482ac3794c7205d", "parents": [ "0ac547da8dd6c2be4313f945a7731548b7c238c2", "eb37879238d7a63b395e6795d2d4dc6cfea265e2" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Sep 18 10:50:20 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 18 10:50:20 2024 +0200" }, "message": "Merge \"test(spm): using SRI delay flag from NWd\"" }, { "commit": "0ac547da8dd6c2be4313f945a7731548b7c238c2", "tree": "f9729d0a5a043a2f7eb54b1f887074223280491e", "parents": [ "f2ed78567ac1df53fc28c3f46dde45dda86a2819", "408a89df20c6345fbeff60364f674bb61bfd2ff8" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Sep 16 14:08:22 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 16 14:08:22 2024 +0200" }, "message": "Merge \"fix(realm): separate pool creation from realm creation helpers\"" }, { "commit": "408a89df20c6345fbeff60364f674bb61bfd2ff8", "tree": "eacbc5e870296a7fa23ef831c2f970a4b016169c", "parents": [ "31a6f6499c5e558a9ef13ff53922f031d18a48b9" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Aug 06 12:33:29 2024 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Sep 16 12:17:11 2024 +0100" }, "message": "fix(realm): separate pool creation from realm creation helpers\n\nInitialize only one pool per testcase.\nSeparate pool creation from realm creation helpers.\nThis fixes the bug where testcase creates 2 realms\nand 2 pools, and first pool is lost and not cleaned up.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I817e97ea5ef15510c18261689c5f5d4e0e65b054\n" }, { "commit": "f2ed78567ac1df53fc28c3f46dde45dda86a2819", "tree": "9ba4b538191a399bdd9e091db3925cdd22d04f6d", "parents": [ "060d31853a5e3a5e6bce744e0934aa22ebfbb8e1", "9f2de630d5d2472e8ec7348507e343738934940d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 13 18:21:28 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 13 18:21:28 2024 +0200" }, "message": "Merge changes I8db1048d,If47077da,Ic2ab11af\n\n* changes:\n feat(doe): add PCIe DOE tests\n feat(pcie): add PCIe support to FVP platform\n feat(pcie): add PCIe DOE library\n" }, { "commit": "9f2de630d5d2472e8ec7348507e343738934940d", "tree": "4905c2ec19086fbdecde033abd1f2f766d98f692", "parents": [ "36ed009a073c64a422c769b46eede6538fa42667" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 11:48:22 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 13 18:20:18 2024 +0200" }, "message": "feat(doe): add PCIe DOE tests\n\nThis patch adds PCIe DOE tests for\n- DOE discovery protocol\n- SPDM get version\nTo build this test suite use \u0027TEST\u003dpcie-doe\u0027\noption.\n\nThe spdm.h is imported from https://github.com/DMTF/libspdm\nproject.\n\nChange-Id: I8db1048d01b4f8061d8a4ddccc198159ed61e6b7\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "f09c77af164cb1332a4db3d141ffc5d60625967b", "tree": "4d5f1085a718618101a75d36e503d0da4aba0b1d", "parents": [ "f30108d8427112a11fbcd3561bdb0bed425f8896" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 15:50:44 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Sep 12 11:59:53 2024 +0100" }, "message": "fix(realm): fix calculation of Realm\u0027s REC index\n\nThis patch fixes the issues related to the calculation of\nRealm\u0027s REC index based on the read value of MPIDR_EL1 register\nand REC\u0027s mpidr parameter from the REC\u0027s index.\nRMM reports MPIDR_EL1.Aff0 field matching RmiRecMpidr type\nwith [7:4] bits RES0, making MPIDR_EL1\u003d0x80000100 represent\nREC 16, but not 256 as it is implemented in the existing code.\nThe patch adds the following macros:\n- RMI_REC_MPIDR(idx) which calculates RmiRecMpidr value based\non REC index.\n- REC_IDX(mpidr) gets REC index from MPIDR_EL1.\n\nChange-Id: Ieac473984f3a50d2815dcfe8d291d31bd70ebae7\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "435c27e58850dc946b37d4af5271b5fc3ecc2399", "tree": "ba921595c125dd787e93dee8d3d57c54f04cd8f7", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Wed Aug 07 15:32:02 2024 +0100" }, "committer": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Wed Aug 21 11:39:41 2024 +0100" }, "message": "test(sdei): add test for attempting to bind too many events\n\nThe test makes sure that if you attempt to bind more events than are\navailable, it will return an error code instead of crashing.\n\nChange-Id: Ib74589a04ed7cbd0d1a9de355a9bf3c99f945ae5\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\n" }, { "commit": "3ca234295ae5802cd684ba56cdec018bde26d2d2", "tree": "42471b88543cc40597fb0fffdd306dbb362fac34", "parents": [ "6f7344b97ab42d045b7a2f502bf9c80100ae8a44" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jul 05 16:26:12 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 19 11:25:51 2024 -0500" }, "message": "feat: introduce a new test suite supported by EL3 SPMC\n\nA new test suite is being created which is supported by Cactus SP. It\naims to exercise the SIMD context management support in EL3 SPMC.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I2a65da8c098b40858a2af0f9012cc225a24e6fcb\n" }, { "commit": "e4f2eaa6f626646cfa3e439086966ac114540cbc", "tree": "ebb5c60c417e4393c160b78f1c31b780a3c48d2f", "parents": [ "eeac9d97edaf45041b7325f9aade1ad7bfeb6828" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Mon Aug 12 17:59:54 2024 +0100" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 12:07:48 2024 -0500" }, "message": "feat: introduce asymmetric feature testing for feat_spe\n\nChange-Id: Ide9bda1b5f1cabc63241f42b93a672d8e04b8119\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "eeac9d97edaf45041b7325f9aade1ad7bfeb6828", "tree": "3cd50819f0a22bcc8ad0d8d8271f9a29dc3ccf2b", "parents": [ "8191621885dfc65789a19ef0eb590b8639ed87d1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Aug 16 12:34:58 2024 +0100" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 09:08:00 2024 -0500" }, "message": "feat: skip TRBE extension test if ERRATA applies\n\nFor Cortex-A520(2938996) and Cortex-X4(2726228) erratums TRBE feature is\ndisabled by EL3.\n\nCheck and skip TRBE test if the core is affected.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Iaa394ae79dec38d0b369012e149abbc65b0cf0f8\n" }, { "commit": "8191621885dfc65789a19ef0eb590b8639ed87d1", "tree": "8fbbf09517a4e7de5976e8912a594be10cfb1f04", "parents": [ "0145ec3459750f35a6546b3f015906356b7dc6cd" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Aug 15 15:08:23 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 09:07:55 2024 -0500" }, "message": "feat: test if errata 2938996 and 2726228 workaround is applied\n\nThis patch confirms if access to trbe el1 register generates an undef\ninjection in affected cores. If a core is affected by errata 2938996/\n2726228 and it generates an undef injection on access to trbe el1 register then\nthe test passes. If it is an unaffected core then the test passes , but\nwhen undef injection doesn\u0027t happen in affected core, the test fails.\n\nChange-Id: I515a9aa4613c6d99ee73e579206089ebf89ffae8\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "0145ec3459750f35a6546b3f015906356b7dc6cd", "tree": "4cb24cf11b7177ae3af728007d27a328f5c636df", "parents": [ "cea63b2bbd871a6664b54af325f6a739e8746ff7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Aug 12 17:59:54 2024 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Aug 16 11:39:26 2024 +0100" }, "message": "feat: skeleton for asymmetric feature testing capability\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I6da831043c9485de00ba29a22ebaea6e9cdb5f57\n" }, { "commit": "7a3c1dc2dc559814882ebf47265e57c31bf05afc", "tree": "85926f08919ea8e44916e0c7da67835cd85275d0", "parents": [ "5dd2a3812bd24b9526dfbaa00a0c3dc3aeb24659" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed Aug 14 10:34:03 2024 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed Aug 14 10:37:16 2024 +0100" }, "message": "refactor(memory share): use UART macro in device mem share\n\nRemove hard coded UART address in the device memory sharing\ntest by using the PLAT_ARM_UART_BASE macro.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ie83e2ff7a41379361018e44d4c6f71198c07e15a\n" }, { "commit": "3d8cd68cffa9709895f1758ea144046bf18b896a", "tree": "388308d2e41b5994b4d0931c0eded8f38094234d", "parents": [ "e95e53f8607b98d06afdd1302722d3f23dca3591" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Jul 23 14:28:15 2024 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Aug 13 12:03:07 2024 +0100" }, "message": "test(memory share): lend device memory region to sp\n\nAdd test to check that a device memory region can be successfully\nlent to an sp.\n\nThis requires some refactoring of the memory sharing test flow so\nas to use the correct memory type and cachebility attributes for\nthe memory being lent. Also limit the words being written to 1\nword for device memory so we only write to the data register of the\ndevice.\n\nAlso only map device regions from UART2 so that UART0 can be used\nby TFTF in the device sharing test.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: I9f31769679883f34e0444db75a873765776a85e9\n" }, { "commit": "eb37879238d7a63b395e6795d2d4dc6cfea265e2", "tree": "aae988be1985ba4194c7caed63b11f8b8194b0fd", "parents": [ "e95e53f8607b98d06afdd1302722d3f23dca3591" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jun 19 13:17:44 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Aug 06 16:21:31 2024 +0100" }, "message": "test(spm): using SRI delay flag from NWd\n\nAttest that the SPMC returns FFA_ERROR_INVALID_PARAMETER\nif the delay SRI flag is set on FFA_NOTIFICATION_SET from\nthe NWd.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I9375f198d0ac6722b676d1a923caef165410920d\n" }, { "commit": "6043eaf8e2aad4727f6e3f7199e88b59787d3ad4", "tree": "0bef58a1a1ac541c6d73fe59773d8f9701f87f93", "parents": [ "277925bbfc6bd1caf47f573dd17569b9a30d7844" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Mar 08 14:14:12 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:22:31 2024 +0200" }, "message": "feat(spm): probe SVL for SME related tests\n\nFor world switch SPM tests checking the SME context, probe the possible\nSVL values in streaming SVE and run tests with each possible SVL.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I5157fc896168f7ea2df131a86acdb1d1f1bb795e\n" }, { "commit": "277925bbfc6bd1caf47f573dd17569b9a30d7844", "tree": "919efe209c396822e0049ce4a02cac8121769047", "parents": [ "e713f655c81cd293ed03211437281c00da444171" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Oct 12 14:56:14 2023 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:22:28 2024 +0200" }, "message": "test(spm): add three SME related tests\n\nSME enter SPMC with SSVE enabled.\nSME enter SPMC with ZA enabled.\nSME enter SPMC with SSVE+ZA enabled.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I092c7618e8de22125b3e957ed557e8177acc2b1f\n" }, { "commit": "e713f655c81cd293ed03211437281c00da444171", "tree": "2ec8d0258d90be8bf17449431855e84078e8f7a4", "parents": [ "57b94c4410d3568754feb1aede059ad794a345a7" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Mar 27 17:09:53 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:21:28 2024 +0200" }, "message": "refactor(spm): rename FF-A SIMD test suite\n\nRename \"SIMD,SVE Registers context\" test suite to \"SIMD context\nswitch tests\".\nRename test case \"Check that SIMD registers context is preserved\" to\n\"Check that Adv. SIMD registers context is preserved\".\nUpdate platform tests_to_skip files accordingly.\nRemove redundant \"SIMD,SVE Registers context\" instance from\ntftf/tests/aarch32_tests_to_skip.txt\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ida5f46a8d0ec822a6629b660c41dfcf9c7e200e7\n" }, { "commit": "57b94c4410d3568754feb1aede059ad794a345a7", "tree": "9c844f15c0f074ac84cc1b27d5f2ccb12873efaa", "parents": [ "2661ba526090e7217d8a334f6f7280c56296f37b" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed May 17 16:41:47 2023 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:21:28 2024 +0200" }, "message": "refactor(spm): test_sve_vectors_preserved\n\nRefactor test_sve_vectors_preserved to probe the possible vector length\nthat the platform implements.\nPerform normal/secure world switches and check that SVE state is\npreserved for all possible vector lengths.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I90f56d9ae97624ceaaae5a4818045922961e5066\n" }, { "commit": "d0704f69f4824d6100faabd19522e0205c926e92", "tree": "cbc56389b7c54fe0021fcfab729b9f5c48f9c5d2", "parents": [ "65442a9ca6fd1062f0eb34c4ac9f62f781dcf352", "c3cf2daed819a9d01feba31832544309c9da8d70" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Jul 29 18:54:59 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 29 18:54:59 2024 +0200" }, "message": "Merge \"feat(amu): test AMU counter restriction (RAZ)\"" }, { "commit": "65442a9ca6fd1062f0eb34c4ac9f62f781dcf352", "tree": "7c4a6528edfddbbcfa4513549244e6e759b16e19", "parents": [ "3d88db7691467351726d05b20d629b94c1fb1b59", "b47ccd0519d2b26fb89bd3434113a17b97e9cc05" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 24 20:04:49 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 24 20:04:49 2024 +0200" }, "message": "Merge \"test(handoff): fix register convention value on test_firmware_handoff()\"" }, { "commit": "3d88db7691467351726d05b20d629b94c1fb1b59", "tree": "10f847b91327aae17ae91a2d6a5342b0a1575e03", "parents": [ "b1ab5854ad384dd1e3abbe760a6b35d6cae9a0bc", "94963d4e739f3fb1accefddd4105cf9140989889" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 24 17:26:44 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 24 17:26:44 2024 +0200" }, "message": "Merge \"feat(fgt): add support for FEAT_FGT2 testing\"" }, { "commit": "cd6c94b20e7450e27254856a82008ca0595d84d1", "tree": "6a8146d2ef87f4c5a0f72f84b850e1577c57a4a4", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Feb 15 17:19:05 2022 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jul 23 14:06:14 2024 +0100" }, "message": "feat(ls64): add a test for 64byte loads/stores instructions\n\nThis patch adds a test to verify the 64 byte load and store\ninstructions introduced by FEAT_LS64.\nThe test primarily executes instructions:\n1. LD64B\n2. ST64B\nand ensures that the NS-EL2 has no dependency on EL3 while\nrunning them.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I7a4ca0ee4a2c18bf0de030c72e35eb218bc6364c\n" }, { "commit": "94963d4e739f3fb1accefddd4105cf9140989889", "tree": "904e5a3428384fae10f4cae54fd91589fc47da8c", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jun 13 17:19:56 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Mon Jul 22 16:21:01 2024 -0500" }, "message": "feat(fgt): add support for FEAT_FGT2 testing\n\nThis patch adds testcase that validates FEAT_FGT2 support\nby reading Fine-grained trap registers that are part of FEAT_FGT2.\nThese registers are only present when FEAT_FGT2 is implemented\n\nChange-Id: Ifc1106d12dbe03b956310d364600368d3f035491\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "72b56754be783ab84ae57a867a6495a4cbfcace6", "tree": "eb7299d596c722a140043073a7cade7d9f50e852", "parents": [ "994e6956079c58766cefac29aaa0f97af10cd73c", "2f2c959871723c303a833778271cd923910deaca" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jul 22 18:08:11 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 22 18:08:11 2024 +0200" }, "message": "Merge \"feat(debugv8p9): test if EL3 has properly enabled FEAT_Debugv8p9\"" }, { "commit": "b47ccd0519d2b26fb89bd3434113a17b97e9cc05", "tree": "81c6baf940af8d9cb028aad04265d872b3cd48ae", "parents": [ "994e6956079c58766cefac29aaa0f97af10cd73c" ], "author": { "name": "Levi Yun", "email": "yeoreum.yun@arm.com", "time": "Wed Jul 10 16:18:47 2024 +0100" }, "committer": { "name": "Levi Yun", "email": "yeoreum.yun@arm.com", "time": "Mon Jul 22 12:03:28 2024 +0100" }, "message": "test(handoff): fix register convention value on test_firmware_handoff()\n\nAccording to recently firmware handsoff spec [1]\u0027s \"Register usage at handoff\nboundary\", Transfer List\u0027s signature value was changed from 0x40_b10b\n(3 bytes) to 4a0f_b10b (4 bytes).\n\nAs updating of TL\u0027s signature, register value of x1/r1 should be:\n\nIn aarch32\u0027s r1 value should be\n R1[23:0]: set to the TL signature (4a0f_b10b -\u003e masked range value: 0f_b10b)\n R1[31:24]: version of the register convention \u003d\u003d 1\nand\nIn aarch64\u0027s x1 value should be\n X1[31:0]: set to the TL signature (4a0f_b10b)\n X1[39:32]: version of the register convention \u003d\u003d 1\n X1[63:40]: MBZ\n(See the [2] and [3]).\n\nTherefore, it requires to separate mask and shift value for register\nconvention version field when sets each r1/x1.\n\nCurrently, TRNASFER_LIST test runs only in aarch64.\nSo, change the assert value in test_firmware_handoff() as\naarch64\u0027s x1 value when transfer list deliver.\n\nLink: https://github.com/FirmwareHandoff/firmware_handoff [1]\nLink: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]\nLink: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]\n\nChange-Id: Ibc86963cc5abda3aae4cb8fe34533be250e3dd95\nSigned-off-by: Levi Yun \u003cyeoreum.yun@arm.com\u003e\n" }, { "commit": "09d34fc7045099a04fc3b5a16b1a6ff7249f0f77", "tree": "ab3c2ed5b796e99da0c12ebb8264935f193d6baf", "parents": [ "de531d27a8cf9222463fa564fa8cbc39ba5d907d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jul 17 14:35:26 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jul 17 14:51:54 2024 +0100" }, "message": "fix(rme): tests pass with trp but not with rmm\n\nThe newly added tests to validate the SPMC can recover\nfrom a GPF are passing with TRP but not with RMM.\n\nThe tests are:\n1- initialising memory descriptors;\n2- changing the TX buffers to realm PAS;\n3- causing SPMC to handle GPF;\n4- check it returned expected error code;\n5- reset the TX buffer PAS;\n6- invoking the FF-A call that failed priorly, expecting\nit would this time pass.\n\nStep 6 was failing because the content of the descriptor in\n1 was not preserved, due RMM sanitising them.\nAdding the reinitialisation of the descriptors before\nstep 6.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ic80151c8782cd360eeac1775429b68a1310e1259\n" }, { "commit": "de531d27a8cf9222463fa564fa8cbc39ba5d907d", "tree": "0f59873f9a6d366fe95fe693952cfc257600a001", "parents": [ "8a8536e4d55459f835625d305300d7ba234f8801", "06f430a8d5b52c4b5a176c150acabcad8c4df529" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jul 15 17:58:14 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 15 17:58:14 2024 +0200" }, "message": "Merge changes from topic \"ja/rxtx_protect\"\n\n* changes:\n test(memory share): hypervisor retrieve request fails\n test(memory share): relinquish fails if TX is in realm\n test(memory share): hypervisor\u0027s RX is realm on retrieve\n test(memory share): hypervisor\u0027s TX is realm on retrieve\n test(memory share): retrieve request from VM\n test(memory share): make TX buffer realm\n" }, { "commit": "06f430a8d5b52c4b5a176c150acabcad8c4df529", "tree": "fd3999753c86d8e728d1606a512f81a1c3dc2697", "parents": [ "4e6fa5b68bbf0ae3be536ec90022db38eb3d4012" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 26 19:09:33 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 16:12:15 2024 +0100" }, "message": "test(memory share): hypervisor retrieve request fails\n\nTest that an hypervisor retrieve request fails smoothly\nif either the TX or the RX buffer are in the realm PAS.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I07e4aa2e07cfd1b5132e82bfbf5a2f76a6f34c14\n" }, { "commit": "4e6fa5b68bbf0ae3be536ec90022db38eb3d4012", "tree": "689338a6be4c08c2eaf7bc980c6c0ab0f6d74df8", "parents": [ "8d6843a473dbd32b80c9b9abfdb4b45341a94033" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 26 16:24:07 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 16:12:15 2024 +0100" }, "message": "test(memory share): relinquish fails if TX is in realm\n\nTest that if there is a GPF when the SPMC copies the relinquish\ndescriptor from Hypervisor\u0027s TX buffer, the handling fails\nsmoothly with error FFA_ERROR_ABORTED.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I45b41a6bdd0efa1f0b01645c944d482ecf993a73\n" }, { "commit": "8d6843a473dbd32b80c9b9abfdb4b45341a94033", "tree": "36324135b3e89f2a632f139f9a435e7f3403eeef", "parents": [ "14c4a326e24ccf2563554d7ea0f282c97cef2ae7" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Apr 25 14:17:52 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 16:11:19 2024 +0100" }, "message": "test(memory share): hypervisor\u0027s RX is realm on retrieve\n\nThe test validates that the SPMC is able to recover from a trapped\naccess to a realm RX buffer during the retrieve response. The\ncall to FFA_MEMORY_RETRIEVE_REQ should return FFA_ERROR_ABORTED.\n\nFollowing, reset the RX buffer\u0027s PAS back to NS, and repeat the\nretrieve request. This time the operation should succeed.\nRelinquish the memory to allow the reclaim.\n\nAt the end of the operation, the sender shall still be able to reclaim\nas the retrieve request should have failed to update any of the structures.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I5d0f2a3e5716a3ed27dda4b6592682c34841ed63\n" }, { "commit": "14c4a326e24ccf2563554d7ea0f282c97cef2ae7", "tree": "cc0dd28c1ccb60507544c3f397e8bb6f3a6400d8", "parents": [ "3aa08bc358d4fde60879a652963d5c394b375286" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Apr 25 13:57:09 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 16:11:03 2024 +0100" }, "message": "test(memory share): hypervisor\u0027s TX is realm on retrieve\n\nRecreate a memory share with multiple borrowers, in which one of the\nborrowers is a VM. The Hypervisor\u0027s TX buffer was moved into realm PAS.\nThe retrieve request is expected to fail with FFA_ERROR_ABORTED.\nReset the TX buffer\u0027s PAS back to non-secure, and redo the retrieve\noperation.\nThis time around, the test is expected to pass.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Id60f17804df4e200533dc1cd8066e64121e04dfd\n" }, { "commit": "3aa08bc358d4fde60879a652963d5c394b375286", "tree": "9132e6a44d4c328d9eda4d6ccfd4efde21106ae2", "parents": [ "d8e2fcd3d125f0d49a59d5db8cfc54c32b89602d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Apr 24 22:20:23 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 14:32:40 2024 +0100" }, "message": "test(memory share): retrieve request from VM\n\nThe SPMC supports the case in which the hypervisor doesn\u0027t\ntrack the operation. This is usable for multiple borrower operations,\nwith a VM. In this case, hypervisor/OS Kernel shall forward the\nrequests to retrieve memory into the SPMC. This patch adds such\ncase, as we lost this coverage in the Hafnium tests.\n\nChange-Id: Ia217ababd6e4ae0a82bed781b6f217a52a0909e0\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "d8e2fcd3d125f0d49a59d5db8cfc54c32b89602d", "tree": "55015474b85830d668de9edeabe2ab36245ac76d", "parents": [ "c95644b4802477edceec51af85c9b12d00ac3a98" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Mar 28 15:53:51 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 08 14:23:28 2024 +0100" }, "message": "test(memory share): make TX buffer realm\n\nTest case scenario in which the NWd changes the PAS of the TX\nbuffer to realm, and invokes FFA_MEM_SHARE ABI.\nSPMC should be able to recover and return FFA_ERROR_ABORTED.\n\nChange-Id: I0f0d833f6a7dcf019deaa5ac661f12060c3427c2\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "f1738b386adba8369bb7ef9344fabac9b5cd1aab", "tree": "4c570f3632ddb08a2c376055d9c518a1ec5e19d2", "parents": [ "c95644b4802477edceec51af85c9b12d00ac3a98" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Oct 11 14:09:46 2023 +0200" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jul 04 12:36:06 2024 +0100" }, "message": "test(realm): unify SIMD test cases\n\nThere are two testcases host_realm_fpu_access_in_rl_ns_se and\nhost_and_realm_check_simd which verifies SIMD state across different\nworld switch. This change unifies both these testcases to one test case\nhost_realm_swd_check_simd so that new enhancements or fixes can be done\nin one place.\n\nThis change also increases the code coverage by removing the restriction\non the need for both secure partition and realm payload as a\nprerequisite.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I210acdff9e584cb392a2f1919dce04971fd2fc7a\n" }, { "commit": "33a7ea4c7e1b31569dbc00768e61784dc54df221", "tree": "15c6d82c45833c621caefd8cdd937537cc51f299", "parents": [ "2a426e74d71bd82c360ac4bdd77c8c164b50ac16" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jul 03 15:11:41 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jul 03 15:11:41 2024 +0100" }, "message": "fix: remove `test_ffa_partition_info_v1_0`\n\nThe test `test_ffa_partition_info_v1_0` relies on being able to change\nthe FF-A version after it has been negotiated. That is no longer\nallowed, so the test will fail. It will be moved to the Hafnium test\nframework, where each test runs in its own session.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I377b40b88d26246e9a584d65c7e12bab3050fde7\n" }, { "commit": "2a426e74d71bd82c360ac4bdd77c8c164b50ac16", "tree": "45de78974518c59f994c4a89df562f786e320e30", "parents": [ "1abd8df96be1f7c5efd73ff38e8044bc5c1b6363" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jul 03 15:03:45 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jul 03 15:03:45 2024 +0100" }, "message": "fix: fix test_smccc_callee_preserved\n\nThe `test_smccc_callee_preserved` test was calling `FFA_VERSION` with an\nold FF-A version, which is no longer allowed. Fix it by calling\n`FFA_VERSION` with the current version.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I85b7c2c1bf54719f84fb737fce770f7f5073580b\n" }, { "commit": "2f2c959871723c303a833778271cd923910deaca", "tree": "a3b777765c3959ea183de411cbe73d18e45578b1", "parents": [ "b5103df4af352c9409fb0756579788d6c0732b87" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jun 06 16:34:28 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Jun 28 14:55:27 2024 -0500" }, "message": "feat(debugv8p9): test if EL3 has properly enabled FEAT_Debugv8p9\n\nWhen FEAT_Debugv8p9 is not enabled, access to MDSELR_EL1\ntraps to EL3. Access to FEAT_DEBUGV8P9 control registers\nmust be explicitly enabled in EL3,\n\nThis testcase uses this behavior to test if\nFEAT_Debugv8p9 is enabled or not.\n\nChange-Id: I2f9a0158e9f38eaffac2e27c40d44d3c520d508d\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "7308b12df02634ca78f0e1ea6e4f758a8b3d8e2a", "tree": "5bd75867d077a40ebd30f5245ae7d5126524220f", "parents": [ "c884d6bf9e3aca4dc63d318eb99d6141c9353363" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Apr 16 14:02:25 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jun 27 10:57:30 2024 +0100" }, "message": "refactor: FFA_VERSION related refactors\n\n* Use an enum for FF-A versions.\n* Replace `MAKE_FFA_VERSION` macro with `make_ffa_version` function.\n* Add `ffa_version_is_valid` helper function.\n* Add `ffa_version_get_major` and `ffa_version_get_minor` helper\n functions.\n\nChange-Id: Icbc4b1fa16e826c2ec541add65aa7c14fb397f95\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "11f6ee85b015635021083db0f494a2c2957566ef", "tree": "14a2c57f6af3ce5453e364e35490c115feba89cf", "parents": [ "07f9671ac3f4b89bda1b9c058c60e7fc39470939" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Jun 04 14:15:17 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Jun 18 14:13:19 2024 +0200" }, "message": "fvp: skip cpu cluster power-on check\n\nOn newer FVP models there is known issue which would report\ncluster power-on check with incorrect bits causing this test to\nfail.\n\nSo skip this test for FVP, the issue is expected to fixed in 11.27\nFVP models we could enable it back then.\n\n\nChange-Id: I7f4e7ba1f4b7473736276958663622a9436fcadb\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "07f9671ac3f4b89bda1b9c058c60e7fc39470939", "tree": "a65a8925f6b949d4297c35da834c51e9813c1394", "parents": [ "6316e359865d3fd00f1c782c25089f974b852875", "a45649a48865a609ce854f3dda51b19517b4cbc0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jun 14 22:46:08 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 14 22:46:08 2024 +0200" }, "message": "Merge changes from topic \"ja/memory_share_64\"\n\n* changes:\n test(ff-a): add SMC64 abi to FFA_FEATURES\n test(memory share): use SMC64 rather than SMC32\n" }, { "commit": "9eb1eaa78ba579295df8876a2480274392ffaa6a", "tree": "fac0fc93aaadd6a30030a514bb6d958bfc1b7e66", "parents": [ "7efea19cd6c832ea8a595ef5dc057cca721ca237" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Sep 19 16:07:09 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jun 13 23:09:38 2024 +0100" }, "message": "feat(rmi): add specific tests for FEAT_LPA2 on RMI tests\n\nThis patch also adds four new tests for RMM:\n\n * Test realm creation with no FEAT_LPA2 and -1 RTT starting level\n * Test realm creation with no FEAT_LPA2 and S2SZ \u003e 48 bits\n * Test creating a realm with FEAT_LPA2 disabled but\n FEAT_LPA2 is present on platform\n * Test creating a realm with FEAT_LPA2 enabled but FEAT_LPA2\n is not present on platform.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c017a16cb5511977bb37f5e146afd5e60b06b97\n" }, { "commit": "7efea19cd6c832ea8a595ef5dc057cca721ca237", "tree": "5f387e91703069d63085e874b0c7727b15d2be80", "parents": [ "6d833ef005af59119dbbc9794a3bbfc191eb4f60" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Sep 19 16:07:09 2023 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Jun 13 13:17:35 2024 +0100" }, "message": "feat(rmi): add support for FEAT_LPA2 to the Realm Extension tests\n\nThis patch adds support to the current Realm Extension tests to\nenable and use 52 bit address size with 4KB granularity when\nFEAT_LPA2 is present.\n\nIn addition, this patch also introduces changes to support passing the\nstarting RTT level and the FEAT_LPA2 enable flag during realm creation\nso they can be used later to implement tests for FEAT_LPA2 on RMI.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I0a930735a44772e5e76d6608c969759f27129917\n" }, { "commit": "a45649a48865a609ce854f3dda51b19517b4cbc0", "tree": "e8f1d835a7974b2215da25148981e9c7d48bfe49", "parents": [ "8984e729cce2c9a1ac8b87fe4e0df886a6ccd6c7" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 08 17:55:35 2024 +0100" }, "committer": { "name": "Joao Alves", "email": "joao.alves@arm.com", "time": "Tue Jun 11 14:52:11 2024 +0200" }, "message": "test(ff-a): add SMC64 abi to FFA_FEATURES\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I387f4fd100462235ecbd298d3921ebab1a004d79\n" }, { "commit": "8984e729cce2c9a1ac8b87fe4e0df886a6ccd6c7", "tree": "1e2546ecd80740da5bfcb7d21bf1f03c2bdc50d2", "parents": [ "6d833ef005af59119dbbc9794a3bbfc191eb4f60" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 07 22:21:54 2024 +0100" }, "committer": { "name": "Joao Alves", "email": "joao.alves@arm.com", "time": "Tue Jun 11 14:52:02 2024 +0200" }, "message": "test(memory share): use SMC64 rather than SMC32\n\nThe SPMC supports memory sharing interfaces to use the\nSMC64 or SMC32 abis.\nThere was not functional change with this. However, making\nTF-A-Tests use SMC64 to validate that they both work.\nHafnium tests will remain using the SMC32 version of the\nABIs.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I31e275ca50973774928591eef0128f0cf0f5be8b\n" }, { "commit": "b324f4d2251094094b32c3138d9313addf443e6b", "tree": "78a6d6800935c6e1cda1a3156ab6facad65383aa", "parents": [ "6c0be80b887f8accf6908b39a7f7b41eda7327d1" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Feb 26 11:06:03 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue May 14 15:38:56 2024 +0200" }, "message": "test(realm): test for rtt_fold assigned\n\nTest for RTT_FOLD for assigned ram, assigned empty\nand assigned ns rtt entries\nFix helper to allow creating L1 block entry for unprotected IPA\n\nChange-Id: I77693f76722d60427edcb112ca58bf772c194b06\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "6c0be80b887f8accf6908b39a7f7b41eda7327d1", "tree": "267f467f11d91951f6a12ad2fae9b079f31ab3f5", "parents": [ "ecc32844365ca4745dfd92d1adeaab2f39fdeeb2" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 20 11:52:57 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue May 14 15:38:51 2024 +0200" }, "message": "test(realm): add test for rtt_fold unassigned\n\nAdd testcase for RMI_RTT_FOLD,\nfor protected IPA unassigned empty and unassigned ram RTTs.\nHost attempts to fold till max level permitted by Arch.\nFix helper to align with RMI call, remove unused code.\n\nChange-Id: Ib94efa7ba60e028bb9f765e769fe377c101a71fc\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "9668ba5730d9607609879667a19f3249a10f2c99", "tree": "812a321c9182243b86010e63d655769764e64b98", "parents": [ "b44b4753d698bb7b703198a458e78746cff0ed23" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 11:49:45 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 14:04:21 2024 +0100" }, "message": "fix(ff-a): tests for FFA_FEATURES\n\nThere are different expectations to the result to the FFA_FEATURES\ncall, provided the feature IDs for ME, SRI and NPI interrupt from\ntftf or cactus.\n\nThis patch refactors the test to keep the common part equal.\nFor the differences, locally define the expected test target\nfor the FFA_FEATURES call.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I96f18487c80d789cf4e10ceee0591786708bce51\n" }, { "commit": "b44b4753d698bb7b703198a458e78746cff0ed23", "tree": "67f3fff875a629fa8d8f0d9778126fefb3430ee9", "parents": [ "caff038b3f0b261b1fcc14f7918a80fa515202c1" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 10:15:51 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 10:15:51 2024 +0100" }, "message": "fix(ff-a): check for presence of SPMC\n\nCheck for the presence of the SPMC in the setup before running\nthe tests.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I4faaf8a169f58a34dda910fd7e00a6844826c17e\n" }, { "commit": "c3cf2daed819a9d01feba31832544309c9da8d70", "tree": "d47120e316a97ea94409e1a61594ec6da1f5a71b", "parents": [ "caff038b3f0b261b1fcc14f7918a80fa515202c1" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Apr 01 13:57:19 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri May 10 13:40:04 2024 -0500" }, "message": "feat(amu): test AMU counter restriction (RAZ)\n\nWhen using AMU counters, there is risk of exposing information to\nlower exception levels. In order to prevent this, counters are\nrestricted, so they are read as zero (RAZ) at a lower EL. This\ntest verifies that counters are read as zero after forcing counting\nthrough instructions that trigger MPMM \"gear shifting\" (e.g.: by\nexecuting SVE instructions).\n\nNote: This test applies to TC2 only, as it is the only platform that\n supports MPMM currently.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ic32ba19fa489cf479947d4467ddb84e6abd1b454\n" }, { "commit": "caff038b3f0b261b1fcc14f7918a80fa515202c1", "tree": "6b62c315921ae23374ba8eb6c1ad26dd7a9fd929", "parents": [ "3202b1a27c5316292c893be1af3cd9cee1bc8738", "0569cc02f6effc7e44f39844ef9ffb9b24a823ca" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri May 10 12:51:50 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 10 12:51:50 2024 +0200" }, "message": "Merge \"test(spm): test FFA_FEATURES with NPI, SRI, MEI\"" }, { "commit": "3202b1a27c5316292c893be1af3cd9cee1bc8738", "tree": "2c201ceff7581f93a28f39746bb91dde9d5d472f", "parents": [ "5e44ee68b6cdce5a40137dac562906c7e43cde41", "e533478ae2a0374e25d1eaff68eb5381a33ed345" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri May 10 07:54:23 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 10 07:54:23 2024 +0200" }, "message": "Merge \"feat(smc): add test for pmf version check\"" }, { "commit": "c83b17bcd0cfcb2dff8b64c8895bc9684f468b71", "tree": "05cfb8d43bf7ecbe2c254c9bf4ef4dccfe3dffb9", "parents": [ "ffdfafbd49bbe0c6212c00ca4fd910574cac538d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Apr 09 12:09:12 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "test(indirect message): aborted send from vm to sp\n\nThe SPMC shall copy the message from the VM\u0027s buffer into\nthe SP\u0027s when VM sends indirect message.\nTest that if TX buffer of the VM is added to the realm\nPAS, the operation fails smoothly with FFA_ERROR_ABORTED.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I375d1987429ed38349c25764262f386b6a4cde57\n" }, { "commit": "ffdfafbd49bbe0c6212c00ca4fd910574cac538d", "tree": "d09165edc985faeeaa800aca2570d9a03843fa26", "parents": [ "807822927033f07e272eae2222f78a878a23bbb0" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Apr 09 12:07:11 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(ff-a): FFA_MSG_SEND2 helper with sender ID\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Idaf866a342f2127172b46f7a7a44a599723db7cf\n" }, { "commit": "807822927033f07e272eae2222f78a878a23bbb0", "tree": "7742e64211e9d61a03a34eb2c66edc660a073400", "parents": [ "df2deb36bc477d46e70704e771061dedd64ae996" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 08 18:04:20 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "test(indirect message): aborted send from SP to VM\n\nTest that if the RX buffer of VM is put on the realm\nPAS and an SP attempts to send a message to it, the\noperation terminates smoothly.\n\nChange-Id: Ie7fd316a6256b1c3445dfb7cb8fe1bbd09fffb6e\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "df2deb36bc477d46e70704e771061dedd64ae996", "tree": "2b5e7872bf9a7a094b19c13e413150357290b381", "parents": [ "cd779f49d89524f5236f4f671e3d566c7d333166" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 22 15:17:45 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "fix(notifications): destroy VM\u0027s bitmap\n\nThe last test in the notifications test suite was not\ncleaning up after itself. This change makes the test destroy\nthe bitmap for the receiver VM in the SPMC.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ia96b8d6e680dd0af99a2c767cd35efe38cf10011\n" }, { "commit": "cd779f49d89524f5236f4f671e3d566c7d333166", "tree": "a132844b98b4c5a8865f9d621b01507446026058", "parents": [ "58cc4dad0451ab4669072c654dbc0603932baa94" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 22 14:31:06 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "test(indirect message): request SP to message VM\n\nAdd test for SP to message a normal world VM.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I4c2f3e8995163024453b6f51900599a5f6e60b19\n" }, { "commit": "907fcef5cc7b2c09679f7ebf99fd92426c544efc", "tree": "f33cc7fda4a2cd7fb4992e2956062ee474624691", "parents": [ "c6b92d5e73a19a9aeeb28d7ac8103cd2dc5adca8" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 08 17:32:58 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(indirect message): send and receive messages\n\nAdded helpers to receive and send indirect messages, respectively:\n- `receive_indirect_message`;\n- `send_indirect_message`;\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I396870f15172f841167627b14c18b1504e0efbee\n" }, { "commit": "c6b92d5e73a19a9aeeb28d7ac8103cd2dc5adca8", "tree": "ee1d3de9d246f6d5abc62170a7b01b656cad09aa", "parents": [ "779fba660d61c8d95adbc66cb5b7086d681e1eaf" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 05 14:16:00 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(ff-a): define framework notification helpers\n\nDefined the helpers to process framework notifiactions.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I979162363898b4f9bf1a3d57327078364883b896\n" }, { "commit": "779fba660d61c8d95adbc66cb5b7086d681e1eaf", "tree": "09298958223dd797fff83fb116e1c76557001137", "parents": [ "2921fba58bd4535f8e944620273ade51f69db63f" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 05 14:14:40 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:34 2024 +0100" }, "message": "feat(ff-a): add helpers for indirect message\n\nAdd the header structures for the rxtx buffers, other\nhelper macros, and the FFA_MSG_SEND2 ABI caller.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ie5c735aa0b33dbf0288b6494362b6e7dc84c6db7\n" }, { "commit": "e533478ae2a0374e25d1eaff68eb5381a33ed345", "tree": "610a7160c96b43e96c00fafcbf9f4676ad6c222c", "parents": [ "dfc4d7f46fb95441443066f60d1b855f7ef9c364" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed May 08 20:33:20 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed May 08 20:33:20 2024 -0500" }, "message": "feat(smc): add test for pmf version check\n\nPMF is moved under vendor specific EL3 range, part of this\nwe have introduced each sub-service have an version scheme[1].\n\nAdd a simple test to check if the sub-service version\nis probed.\n\n[1]:\nhttps://trustedfirmware-a.readthedocs.io/en/latest/components/ven-el3-service.html\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: I885cd1378a8025371172e5cd82fdd111d6832619\n" }, { "commit": "2921fba58bd4535f8e944620273ade51f69db63f", "tree": "5cc656109e7ba43327e00da2b4b34e7658b8bbd2", "parents": [ "a23b8ffefeafc1b5dab19fa2fc78e9596739cbc1" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Apr 24 10:30:35 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 08 16:30:21 2024 +0100" }, "message": "chore: move test from xml file\n\nMove test suite \"SP exceptions\" from \u0027tests-spm.xml\u0027\ninto \u0027tests-memory-access.xml\u0027.\n\nChange-Id: Ia312007cd3c6c6b98ac62cdd7e2b762669fa8e71\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "a23b8ffefeafc1b5dab19fa2fc78e9596739cbc1", "tree": "7cabe04b2079369f331677c84fe442b71408b707", "parents": [ "067daca6eea89d0ac95fcedc12750521ea09b952" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Feb 23 14:50:14 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 08 16:30:16 2024 +0100" }, "message": "test(rme): rxtx buffers are in the realm PAS\n\nAdded a test for which the SPMC attempts to use the RXTX\nbuffers, in an RME enabled platform and in which the buffers\nwere changed to realm PAS.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Idb29f8687fbe5885c00e61155a5ebbdd8908d688\n" }, { "commit": "067daca6eea89d0ac95fcedc12750521ea09b952", "tree": "3372bfa2adc9c32b54417f547de0a78cb141909e", "parents": [ "dfc4d7f46fb95441443066f60d1b855f7ef9c364" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 08 17:31:54 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 07 15:46:16 2024 +0100" }, "message": "feat(ff-a): add helper FFA_RX_RELEASE with ID\n\nAdd the helper `ffa_rx_release_with_id` for TFTF\nto mimic the releasing of RX buffer from a hypervisor.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I1edcc1568fd84af72454f3b755ccf16eca321a17\n" }, { "commit": "dd8025c73f9c2f73c663629b30508b96f04194e1", "tree": "d476fff8d3bc87d11f8b132b4b55698638792f4a", "parents": [ "951d5fbe6641ed58747fed557e462dd3f3508ce4" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Mar 14 09:47:24 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Apr 24 13:29:10 2024 -0500" }, "message": "feat(smc): add test for vendor-specific service\n\nAdd test to check vendor-specific el3 service calls.\n\nChange-Id: I981d1cacec8690f57e51a5f05d51b6e437d1eb6a\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "951d5fbe6641ed58747fed557e462dd3f3508ce4", "tree": "b086b0ade6129b8294017dcaba03c0ebc5b4da9a", "parents": [ "f33112d50b18143421d3f3eac02a615f821ec284" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Mar 14 09:50:37 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Apr 24 13:29:10 2024 -0500" }, "message": "refactor(smc): group all smc tests\n\nMove and group all smccc related tests to tests-smc*\nfile.\n\nChange-Id: I34eb4dc906b558badab2c9356bb316d92f40914a\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "f33112d50b18143421d3f3eac02a615f821ec284", "tree": "eacae716d87f7883d56bbdf8b533a8c068a0c00a", "parents": [ "3eb25fb886ece03d872eaba4bbd31cf80edda6af" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Feb 26 09:44:36 2024 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Apr 24 13:29:10 2024 -0500" }, "message": "refactor: make debugfs and pmf as vendor el3 services\n\nMove Debugfs and PMF support to vendor-specific el3 space.\nSMCCC 1.5 introduces vendor-specific el3 space.\n\nRef: https://developer.arm.com/docs/den0028/latest\n\nChange-Id: Ie6679dbb2ca2434ebd4fc19c2cc21cf5a84f97ab\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "0569cc02f6effc7e44f39844ef9ffb9b24a823ca", "tree": "69a44448fc7538e54ce588b55a6d9af5c19ed87e", "parents": [ "bbd609b99b23da41b997415980065be5849aeea9" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Apr 17 17:32:35 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Apr 23 14:17:32 2024 +0100" }, "message": "test(spm): test FFA_FEATURES with NPI, SRI, MEI\n\nChange-Id: I3cd376e4594e49c984ad6563d36928cee47a0897\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "3eb25fb886ece03d872eaba4bbd31cf80edda6af", "tree": "5de8b9d866ae31762bec44e6d2264ed47bc59d1e", "parents": [ "bbd609b99b23da41b997415980065be5849aeea9", "f2bb5d0f502955caf58192c6d9c9e0a051817b5d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 23 14:48:41 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Apr 23 14:48:41 2024 +0200" }, "message": "Merge \"test(ff-a): FFA_FEATURES returns max RXTX buffer size\"" }, { "commit": "42487ce271ed8de49625bcec731661b6b790953d", "tree": "9dbccf61a20c85ca92fbf81fbfef005ebb67519d", "parents": [ "eaf60b4cad7d34afedb3259a4dd6164b39cb9c0e", "bff9b3ca375d40753a3212dbf178bcdfc7784841" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Apr 15 15:56:34 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Apr 15 15:56:34 2024 +0200" }, "message": "Merge changes from topic \"km/rxtx_map_unmap\"\n\n* changes:\n test(spm): tests for RXTX_MAP/RXTX_UNMAP\n feat(ffa-svc): add `ffa_func_name` and `ffa_error_name`\n" }, { "commit": "bff9b3ca375d40753a3212dbf178bcdfc7784841", "tree": "d46e017d6c35e04582c340fbd1c433680fbc22c9", "parents": [ "e3e570653471af3506846f06b5fe0421970adce4" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 18 16:08:35 2024 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Fri Apr 12 17:24:23 2024 +0100" }, "message": "test(spm): tests for RXTX_MAP/RXTX_UNMAP\n\nTests to check that RXTX_MAP and RXTX_UNMAP properly unmap/map the RX\nand TX pages from the NWd stage 2 page tables.\nSpecifically:\n* RXTX_MAP should fail when using secure memory\n* RXTX_MAP should fail when using non-secure memory outside the regions\n specified in SPMC nodes\n* Memory sharing functions (lend, share, donate) should fail when using\n memory that has been mapped by RXTX_MAP\n* RXTX_UNMAP should fail when using different VM IDs\n* Forwarded RXTX_MAP should succeed when the region is not mapped\n* Two consecutive forwarded RXTX_MAPs should succeed when the regions\n don\u0027t overlap and the endpoint IDs are different\n* Forwarded RXTX_MAP should fail when the region is already mapped\n* Memory sharing functions (lend, share, donate) should fail when using\n memory that has been mapped by forwarded RXTX_MAP\n\nChange-Id: I006681ab54f5ff602e862ae09438d0d174c8d0b0\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "e3e570653471af3506846f06b5fe0421970adce4", "tree": "f1a6c8a23f0a06e442d058b2ad22034f6e0febb5", "parents": [ "52f0b0ac70de3701d642cd59044aa70ffa342e40" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 18 14:28:36 2024 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Fri Apr 12 17:16:00 2024 +0100" }, "message": "feat(ffa-svc): add `ffa_func_name` and `ffa_error_name`\n\nAdds helper functions for getting string representations of function\nidentifiers and error codes. This makes debug logs more readable than\nprinting the integer value.\n\nChange-Id: I9e74c197686dc08e0c71886f641c60829587bad6\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "b21ee3e7c8e796f918e59205dd4184aa7732a3e6", "tree": "4c109838a31cfe3375936a4685973af32d39a30b", "parents": [ "52f0b0ac70de3701d642cd59044aa70ffa342e40" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 20 16:32:56 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Apr 05 11:25:54 2024 -0500" }, "message": "test: ensure mte registers are restored upon context switch\n\nThis test aims to validate MTE system registers are restored to\ncorrect values upon world switch triggered by an FF-A direct message\nrequest to an SP.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I9b01d349a0cf0ce557e74cfc70ed5208468e7919\n" } ], "next": "b1b37926917b265ef8a3f6caf59b6a20fe8b636c" }