)]}' { "log": [ { "commit": "ad8e3c9506abc6fd093c9753c8e201ddc2daa270", "tree": "30316e9c4809c4e9b993c8fdbbcfdf94ddfdb2d2", "parents": [ "42c6a147d6f8957ff0b6e9eec4591b0927b8769f", "abee7af011b843681bcb0ac8ce00f383df6df899" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Oct 03 16:08:22 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 03 16:08:22 2025 +0000" }, "message": "Merge \"feat(mbedtls): update mbedtls to version 3.6.4\" into lts-v2.10" }, { "commit": "abee7af011b843681bcb0ac8ce00f383df6df899", "tree": "30316e9c4809c4e9b993c8fdbbcfdf94ddfdb2d2", "parents": [ "42c6a147d6f8957ff0b6e9eec4591b0927b8769f" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Sep 29 10:06:16 2025 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Sep 29 10:06:16 2025 +0200" }, "message": "feat(mbedtls): update mbedtls to version 3.6.4\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I3ed56c27d7c67f5386d9c9a69b45b90a4a5f4b60\n(cherry picked from commit caca5cc7406eea453bcd93df1639ba2407ae80ef)\n" }, { "commit": "42c6a147d6f8957ff0b6e9eec4591b0927b8769f", "tree": "5532a4c79c2b1d7550affa100cbaf133df99f3a4", "parents": [ "8e09c3954c76fa1232fc80331210b84572abcec8", "6e6cdb0f0c904a9d56f0cecf9834a5959d360369" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Apr 15 17:17:27 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Apr 15 17:17:27 2025 +0200" }, "message": "Merge changes from topic \"for-lts-v2.10.15\" into lts-v2.10\n\n* changes:\n feat(mbedtls): update mbedtls to version 3.6.3\n feat(mbedtls): update mbedtls to version 3.6.3\n feat(mbedtls): update minimum version to latest MbedTLS v3.6.2\n feat(lib): add mbedtls support\n feat(realm): add MbedTLS as submodule\n" }, { "commit": "6e6cdb0f0c904a9d56f0cecf9834a5959d360369", "tree": "5532a4c79c2b1d7550affa100cbaf133df99f3a4", "parents": [ "e04fce4d6420bc25b889d33dd678889978209956" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Mon Apr 07 13:18:19 2025 -0500" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Apr 10 17:08:40 2025 +0200" }, "message": "feat(mbedtls): update mbedtls to version 3.6.3\n\nUpdate additional mbedtls submodule to version 3.6.3.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I69814f9a5e7e0c260169111a7ec1dd42dbc3679c\n(cherry picked from commit 69a9c4027085d4331f54aa1cc753626749812168)\n" }, { "commit": "e04fce4d6420bc25b889d33dd678889978209956", "tree": "cd7d8c82285cc5ffd42b99f9f0e1661174689e61", "parents": [ "4bc0b124a708f7187839e8658bf65b4045396304" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 03 12:49:06 2025 -0500" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Apr 10 17:08:29 2025 +0200" }, "message": "feat(mbedtls): update mbedtls to version 3.6.3\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I4bfb546c351c30a6fc4d22f29bc03efad316df7d\n(cherry picked from commit d5bb5f6c82f7ebcf28dccbbfad058e27e207c14f)\n" }, { "commit": "4bc0b124a708f7187839e8658bf65b4045396304", "tree": "d327cf40a16d76c027e1f5fc314b2b2fe625bb02", "parents": [ "37b1037dbed1dec729f02e8d319a9d5ffafee38a" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Dec 17 09:14:50 2024 +0000" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Apr 10 17:08:18 2025 +0200" }, "message": "feat(mbedtls): update minimum version to latest MbedTLS v3.6.2\n\nUse the latest MbedTLS version 3.6.2 as the minimum to stay in\nsync with TF-A.\n\nChange-Id: I4c70ec87805a99ba0cfaf2c23cfea51133d0daf7\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n(cherry picked from commit d8092a550b85c6369aabf96430c9b06cc8444298)\n" }, { "commit": "37b1037dbed1dec729f02e8d319a9d5ffafee38a", "tree": "5b2eee768f2145f2d49840d5c7edee59a3695a34", "parents": [ "5066338f8b05659a7a86e3851b310dae33c18602" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 12:19:32 2024 +0000" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Apr 10 17:08:07 2025 +0200" }, "message": "feat(lib): add mbedtls support\n\nAdd support for compiling Mbed TLS from external source.\n\nThe Mbed TLS library is compiled from source pointed by MBEDTLS_DIR\nenvironment variable. Any TFTF test that includes mbedtls.mk will have\nsupport for mbedtls library. Note that by default the MBEDTLS_DIR will\npoint to the default submodule directory (ext/mbedtls).\n\nThis support is added for testing RMM capabilities related to\nDevice Assignment in RMM.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I0e386334078812e5ff5bdcffd4143732e0478b64\n(cherry picked from commit 23788fa84220f873a21f8bca53d973e240ae8740)\n" }, { "commit": "5066338f8b05659a7a86e3851b310dae33c18602", "tree": "6b1ed9e20ff458f50aab92dac100927e67205e30", "parents": [ "8e09c3954c76fa1232fc80331210b84572abcec8" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 04:39:38 2024 +0000" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Apr 10 17:07:58 2025 +0200" }, "message": "feat(realm): add MbedTLS as submodule\n\nThis patch adds MbedTLS repository as a git submodule.\nThe version of MbedTLS added is v3.6.2.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I744ef44e61c85ade3d56920cfc1b8fd1a27bb045\n(cherry picked from commit c5f75b914824a6c3cb992596b44f1c2a116eb7d3)\n" }, { "commit": "8e09c3954c76fa1232fc80331210b84572abcec8", "tree": "5ab1d933b39fa0b0407591dd3b134ac260715d75", "parents": [ "c4f53cd7820cbbcbf7fb5e6a5393b199c30077a2", "9a21efb69db15b3a6ccf85358b4c362554607833" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Feb 12 20:42:15 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 12 20:42:15 2025 +0100" }, "message": "Merge \"test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\" into lts-v2.10" }, { "commit": "9a21efb69db15b3a6ccf85358b4c362554607833", "tree": "5ab1d933b39fa0b0407591dd3b134ac260715d75", "parents": [ "c4f53cd7820cbbcbf7fb5e6a5393b199c30077a2" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Feb 06 09:46:56 2025 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Feb 06 09:51:36 2025 +0100" }, "message": "test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\n\nTesting was conducted using FVP Version 11.26.11\non Cortex-X3, Cortex-X4, Neoverse-V2, Neoverse-V3\nand Cortex-X925. Additionally, negative testing\nwas performed on Cortex-X2.\n\nThis patch tests SMCCC_ARCH_WORKAROUND_4 [1] for CVE_2024_7881 [2]\n[1]: https://developer.arm.com/documentation/den0028/latest\n[2]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881\n\nChange-Id: I4c33b7a9372236ce3ef38f9d1786d5794bb7ddbc\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n(cherry picked from commit 43d421bb292984fdc56269fb3e87e619ca0892d3)\n" }, { "commit": "c4f53cd7820cbbcbf7fb5e6a5393b199c30077a2", "tree": "a746ebbe5d6b9dd4896a6cb03ff2f741a99975e5", "parents": [ "35688173f75776a57e9516ddd9363e2ed1f4d86d", "e154bb4fa9801b76d5496b191d53193c9d109fc2" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Oct 23 10:27:48 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 23 10:27:48 2024 +0200" }, "message": "Merge \"fix: cactus_mm is too verbose on some tests\" into lts-v2.10" }, { "commit": "e154bb4fa9801b76d5496b191d53193c9d109fc2", "tree": "a746ebbe5d6b9dd4896a6cb03ff2f741a99975e5", "parents": [ "35688173f75776a57e9516ddd9363e2ed1f4d86d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 07 14:44:56 2024 +0100" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Oct 22 17:30:27 2024 +0200" }, "message": "fix: cactus_mm is too verbose on some tests\n\nChanging logs printed with \"INFO\"/\"NOTICE\" to\n\"VERBOSE\".\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I89ff56fb631b1a1f393b6d3cdc59bbc7c43cee0a\n(cherry picked from commit 66ee63286f790f61c56dfb8765b5668ccd8991aa)\n" }, { "commit": "35688173f75776a57e9516ddd9363e2ed1f4d86d", "tree": "c6ff3590691a48569eb5d7b63fbc89d19ba6aa56", "parents": [ "8917cf8b5eeb409b63256076d0dc35c60930ce18", "d84e33e4d78936e13f6e4c48efe40a3931063835" ], "author": { "name": "Paul Sokolovsky", "email": "paul.sokolovsky@linaro.org", "time": "Sat Aug 31 14:30:28 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Aug 31 14:30:28 2024 +0200" }, "message": "Merge \"fvp: skip cpu cluster power-on check\" into lts-v2.10" }, { "commit": "d84e33e4d78936e13f6e4c48efe40a3931063835", "tree": "c6ff3590691a48569eb5d7b63fbc89d19ba6aa56", "parents": [ "8917cf8b5eeb409b63256076d0dc35c60930ce18" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Jun 04 14:15:17 2024 -0500" }, "committer": { "name": "Paul Sokolovsky", "email": "paul.sokolovsky@linaro.org", "time": "Sat Aug 31 14:29:08 2024 +0200" }, "message": "fvp: skip cpu cluster power-on check\n\nOn newer FVP models there is known issue which would report\ncluster power-on check with incorrect bits causing this test to\nfail.\n\nSo skip this test for FVP, the issue is expected to fixed in 11.27\nFVP models we could enable it back then.\n\n\nChange-Id: I7f4e7ba1f4b7473736276958663622a9436fcadb\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n(cherry picked from commit 11f6ee85b015635021083db0f494a2c2957566ef)\n" }, { "commit": "8917cf8b5eeb409b63256076d0dc35c60930ce18", "tree": "20eba7d7d86e0dc08e004aeaf710961315b29f0b", "parents": [ "4c492ac1d4cdbc751853c647e6a52991d065c31f", "4a8d758de2dc0d1f976c47e10ae62845fcb26058" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Apr 05 18:08:57 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 05 18:08:57 2024 +0200" }, "message": "Merge \"docs(release): changelog for lts-v2.10.3 release\" into lts-v2.10" }, { "commit": "4a8d758de2dc0d1f976c47e10ae62845fcb26058", "tree": "20eba7d7d86e0dc08e004aeaf710961315b29f0b", "parents": [ "4c492ac1d4cdbc751853c647e6a52991d065c31f" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Fri Apr 05 09:55:25 2024 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Fri Apr 05 09:59:27 2024 +0200" }, "message": "docs(release): changelog for lts-v2.10.3 release\n\nThis is the first LTS release in TF-A-tests. But its numbering is\nv2.10.3 to aligned with TF-A LTS it depends on.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I6b339924208e338595987e17980bfd593e4ad66f\n" }, { "commit": "4c492ac1d4cdbc751853c647e6a52991d065c31f", "tree": "be9b8d9137e426bc6b447ed4e5b3ec37ac7638d3", "parents": [ "5b8229cd99830d4d98671c96153d54f03c3dbcd4", "2162802763be49ffc68a4c23ae2663a67d50e22e" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Apr 05 09:08:55 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 05 09:08:55 2024 +0200" }, "message": "Merge \"refactor(errata_abi): update the cpu structs for errata ABI\" into lts-v2.10" }, { "commit": "2162802763be49ffc68a4c23ae2663a67d50e22e", "tree": "be9b8d9137e426bc6b447ed4e5b3ec37ac7638d3", "parents": [ "5b8229cd99830d4d98671c96153d54f03c3dbcd4" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Feb 15 14:14:59 2024 -0600" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Mar 27 18:59:10 2024 +0100" }, "message": "refactor(errata_abi): update the cpu structs for errata ABI\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I4650a88003db2ded9277b35c7fc521026fe4a5d7\n(cherry picked from commit 7bb1c84eca3a7dc46051b75b6b1cf13046b88c92)\n" }, { "commit": "5b8229cd99830d4d98671c96153d54f03c3dbcd4", "tree": "c2072b00fd5ee7d267162e42f3eb26d1a8f0cfb7", "parents": [ "42b99719d5dde58bdde07712bcb70a20d87f9067", "9135090d057b3f220ae26234ac195f3ffda657d6" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Mar 18 15:26:48 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 18 15:26:48 2024 +0100" }, "message": "Merge \"refactor(errata_abi): add the Cortex-X4 cpu struct\" into lts-v2.10" }, { "commit": "9135090d057b3f220ae26234ac195f3ffda657d6", "tree": "c2072b00fd5ee7d267162e42f3eb26d1a8f0cfb7", "parents": [ "42b99719d5dde58bdde07712bcb70a20d87f9067" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Feb 29 15:18:50 2024 -0600" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Mar 12 14:32:16 2024 +0100" }, "message": "refactor(errata_abi): add the Cortex-X4 cpu struct\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I8421dcc98eea85d038070f90e819e91bb2652727\n(cherry picked from commit cd6128d479033c7ac4cff8e932415b5c04bbde67)\n" }, { "commit": "42b99719d5dde58bdde07712bcb70a20d87f9067", "tree": "4dd511e9cf7010fd3a1007024b0ca35c91cc1338", "parents": [ "5097423f3849187e70e1a1672957579042c51dc4", "67fc3705dd951e5eb76b33e7248113ce71a0a0e1" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Mon Nov 20 21:25:36 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 20 21:25:36 2023 +0100" }, "message": "Merge \"docs(release): changelog for v2.10 release\"" }, { "commit": "67fc3705dd951e5eb76b33e7248113ce71a0a0e1", "tree": "4dd511e9cf7010fd3a1007024b0ca35c91cc1338", "parents": [ "5097423f3849187e70e1a1672957579042c51dc4" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Nov 13 17:46:50 2023 -0600" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Nov 20 10:59:23 2023 +0000" }, "message": "docs(release): changelog for v2.10 release\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I20216a4b6114a89187e4d88d23542592b78bfbff\n" }, { "commit": "5097423f3849187e70e1a1672957579042c51dc4", "tree": "3b0f6ae723a885a26055d2c2d92457995cdf1bc6", "parents": [ "e445efcaa5e9320358ad9a516fdcba98af5c8980", "3be754edfc84d8d66420f4f37dcc2df2825d2737" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Nov 07 10:30:26 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 07 10:30:26 2023 +0100" }, "message": "Merge \"docs: fix broken links in landing page\"" }, { "commit": "3be754edfc84d8d66420f4f37dcc2df2825d2737", "tree": "3b0f6ae723a885a26055d2c2d92457995cdf1bc6", "parents": [ "e445efcaa5e9320358ad9a516fdcba98af5c8980" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Oct 31 13:27:26 2023 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Nov 06 11:42:37 2023 -0600" }, "message": "docs: fix broken links in landing page\n\nUpdated the URL for the SPM documentation.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I35f386a78620888ace3f83b065f28f6f9bfecfce\n" }, { "commit": "e445efcaa5e9320358ad9a516fdcba98af5c8980", "tree": "bee421ee4ad87734d661b3dcf6cb36f61e0d92c0", "parents": [ "092189660673eeac7de4514035033240fde95b42", "c6a3abf980d69e59c08a66a0f4743958c1de6092" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Nov 06 18:12:32 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 06 18:12:32 2023 +0100" }, "message": "Merge \"fix(interrupts): check support for ESPI before testing it\"" }, { "commit": "c6a3abf980d69e59c08a66a0f4743958c1de6092", "tree": "bee421ee4ad87734d661b3dcf6cb36f61e0d92c0", "parents": [ "092189660673eeac7de4514035033240fde95b42" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Oct 25 16:47:23 2023 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 02 21:36:07 2023 -0500" }, "message": "fix(interrupts): check support for ESPI before testing it\n\nIt is possible for extended range interrupts to be enabled by software\nbut the underlying hardware (GIC) may not support it. In such,\nscenarios check if the support exists before exercising the\nESPI functionality.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ibdf18be8403539c0ae9204309adc8a81dd0382d3\n" }, { "commit": "092189660673eeac7de4514035033240fde95b42", "tree": "8f9c6a3e27ea23dc14061bd635c917e0519ab80a", "parents": [ "f3aa070f69debb2aa9b6480cbf4c2d67b5a4f68c", "87ce0a2f16c477e209a19a5d0458e4bf9518933e" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Nov 02 14:35:42 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 02 14:35:42 2023 +0100" }, "message": "Merge \"feat(ras): test to verify SErros synchronized at EL3 boundry\"" }, { "commit": "87ce0a2f16c477e209a19a5d0458e4bf9518933e", "tree": "8f9c6a3e27ea23dc14061bd635c917e0519ab80a", "parents": [ "f3aa070f69debb2aa9b6480cbf4c2d67b5a4f68c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jun 16 16:53:16 2023 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Nov 02 10:40:28 2023 +0100" }, "message": "feat(ras): test to verify SErros synchronized at EL3 boundry\n\nTests to verify SErrors which gets triggered as part of error\nsynchronization at EL3 entry.\nIn FFH mode, EL3 does nested exception handling while in KFH it\nreflectes it back to TF-A Tests.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I5a980ed49ee47ea2f0d5685ba8378d48393ad157\n" }, { "commit": "f3aa070f69debb2aa9b6480cbf4c2d67b5a4f68c", "tree": "4d127ea733e9fb218803c3d448543b06f78ea4a0", "parents": [ "1a7a9832a1725168ba0476017ede051e375b8ed5", "11320699cb58d75e5821d0938403efabaffda21d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Nov 01 13:16:31 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 01 13:16:31 2023 +0100" }, "message": "Merge \"test(rme): add SME registers to SIMD state test\"" }, { "commit": "11320699cb58d75e5821d0938403efabaffda21d", "tree": "4d127ea733e9fb218803c3d448543b06f78ea4a0", "parents": [ "1a7a9832a1725168ba0476017ede051e375b8ed5" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Sep 07 17:05:48 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Nov 01 11:50:59 2023 +0000" }, "message": "test(rme): add SME registers to SIMD state test\n\nRandomly verify SVE registers or SME registers if the system supports\nboth SVE and SME.\n\nWithin SME, randomly select below configs\n- enable/disable streaming mode\n- enable/disable FA64\n- select random streaming vector length\n\nWith this change \u0027host_and_realm_check_simd\u0027 test will support below\nconfigs:\n* SVE only\n* SME only\n* with SVE and SME\n* without SVE and SME\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2895135eeecd3f3e895de3ed7aa2864fb35fd4b1\n" }, { "commit": "1a7a9832a1725168ba0476017ede051e375b8ed5", "tree": "bd748e06b84078b509ca21320e7860a8aa7746d4", "parents": [ "b7cf9d0006e631a31f48253c97ee5971af81622a", "1b327c2f7cf7e20172a79fa370d71efc0e84770d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Nov 01 11:01:45 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 01 11:01:45 2023 +0100" }, "message": "Merge changes from topic \"rmm_sme\"\n\n* changes:\n test(rme): intermittently switch to Realm while NS doing SSVE ops\n feat(rme): add tests to check NS SME ID registers and configurations\n feat(sme): add sme helper routines and add streaming sve support\n fix(sme): use rdsvl instead of rdvl\n fix(sme): enable SME/SME2 during arch init\n" }, { "commit": "b7cf9d0006e631a31f48253c97ee5971af81622a", "tree": "e5626ebd9099c28d7c188f688f623670fca5b041", "parents": [ "3dc2d746aa4bc44174a9981fa082c1473d0006a4", "292a48a054e757237412b0955e7bba674bbc586c" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 18:21:37 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 31 18:21:37 2023 +0100" }, "message": "Merge \"fix(build): fix incremental build issue with realm payload\"" }, { "commit": "292a48a054e757237412b0955e7bba674bbc586c", "tree": "e5626ebd9099c28d7c188f688f623670fca5b041", "parents": [ "3dc2d746aa4bc44174a9981fa082c1473d0006a4" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Fri Oct 27 16:46:36 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 18:20:02 2023 +0100" }, "message": "fix(build): fix incremental build issue with realm payload\n\nOn incremental build the tftf.bin gets appended again with realm payload\ncausing the old realm payload to be loaded during boot. This fix\nrecreates base tftf.bin for every build before appending it with the\nrealm payload.\n\nThis also fixes makefile warnings seen when ENABLE_REALM_PAYLOAD_TESTS\u003d1\nby removing duplicate MAKE_IMG,realm calls.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Iaedfb27572a034d70ec2a402dc3074b0d4b8c660\n" }, { "commit": "1b327c2f7cf7e20172a79fa370d71efc0e84770d", "tree": "580dc95a4ed5b9394be66040dd79048e34e2f648", "parents": [ "1768e59c3a6ac8d727ac012719b4b09947c8400d" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 06 15:39:47 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:57 2023 +0000" }, "message": "test(rme): intermittently switch to Realm while NS doing SSVE ops\n\nInterleave NS Streaming SVE operations with Realm SVE operations and\ncheck whether Streaming SVE vectors are not affected.\n\nThis commit extends the existing SVE test case to work on both Normal\nand Streaming SVE mode.\n\nThis testcase runs for SVE+SME config and for SME only config.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I70fe20f980866cbdd5dadf85804a9e5738227846\n" }, { "commit": "1768e59c3a6ac8d727ac012719b4b09947c8400d", "tree": "cc6ad04618bb60fb861bf3e7e4da2538c1a5cf42", "parents": [ "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue May 23 13:28:38 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:54 2023 +0000" }, "message": "feat(rme): add tests to check NS SME ID registers and configurations\n\nThese tests checks the functionality of RMM for NS SME support.\n- Create Realm and test ID registers specific to SME\n- Check if Realm gets undefined abort when it accesses SME\n- Check whether RMM preserves NS SMCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ia8ffd0188297a74c095dbadfb389add50c548e10\n" }, { "commit": "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581", "tree": "3e0552b2dae1f333abe34bddd7a4ea63c40f985f", "parents": [ "47b702c49a622e895d70104d78a20bb979dae229" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 06 16:31:19 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "feat(sme): add sme helper routines and add streaming sve support\n\nThis patch adds a few helper routines to set the Streaming SVE vector\nlength (SVL) in the SMCR_EL2 register, to enable/disable FEAT_SME_FA64\nand to get CPU\u0027s Streaming SVE mode status.\n\nThis patch also makes SVE compare routines compatible for both normal\nSVE and streaming SVE mode.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7294bb17a85de395a321e99241704066662c90e8\n" }, { "commit": "47b702c49a622e895d70104d78a20bb979dae229", "tree": "0d8eb64935c78a960998a4163c996f418c0fd96b", "parents": [ "92f1868013792ac13497d1045078b7e8a12d4f02" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 06 13:31:46 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "fix(sme): use rdsvl instead of rdvl\n\nUse rdsvl instruction to get Streaming SVE vector length instead of rdvl\ninstruction. When the CPU is in Streaming SVE mode both rdvl and rdsvl\ninstruction returns the same value but that is not true when the CPU is\nin Normal SVE mode. So it\u0027s preferred to use rdsvl to get SVL.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ieb6226f4fc275ee8a81eb359af465c26e307bc75\n" }, { "commit": "92f1868013792ac13497d1045078b7e8a12d4f02", "tree": "c94edb176be497ef790dfeaf98bb7b1e49cef824", "parents": [ "3dc2d746aa4bc44174a9981fa082c1473d0006a4" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Sat Sep 02 01:41:28 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "fix(sme): enable SME/SME2 during arch init\n\nThis change enables SME/SME2 for nonsecure use at EL2 for TFTF cases\nduring arch_setup. This removes dependency on testcases to explicitly\ncall sme_enable or sme2_enable to access SME or SME2 functionality.\n\nThis change also adds CPTR_EL2 register in suspend context. CPTR_EL2\nregister is saved/restored in CPU suspend entry/exit path.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2c99fd49c48c1a9ff2110747714db858a78d3a32\n" }, { "commit": "3dc2d746aa4bc44174a9981fa082c1473d0006a4", "tree": "e62c636478dc937e944d7f236837096b535d3551", "parents": [ "ab2fe6b01abef3c4b17ffb2c6ee4759f6801e095", "40de8ec10f4d9925c24d2b9dd22822e0c8fd4224" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 12:08:26 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 31 12:08:26 2023 +0100" }, "message": "Merge changes from topic \"rmm-eac5\"\n\n* changes:\n feat(rmm-eac5): update RSI_VERSION, RMI_VERSION\n feat(rmm) : add api for rec force exit\n test(rmm-eac4): add testcase for CPU_ON denied\n" }, { "commit": "40de8ec10f4d9925c24d2b9dd22822e0c8fd4224", "tree": "30347a76b3f2429f8ab3d0f124526d860ee77503", "parents": [ "6bb95105b289a4d9015d74af7cb7254455b2344e" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Oct 12 21:45:12 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "feat(rmm-eac5): update RSI_VERSION, RMI_VERSION\n\nThis patch adds necessary support for RMI_VERSION\nand RSI_VERSION commands.\nMacro SMC_RSI_ABI_VERSION renamed to SMC_RSI_VERSION.\n\nNote.\nThis patch sets both RSI and RMI version numbers to\n1.0 as per RMM Specification 1.0-eac5.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If4eb14d93f657388e2fe64ceefee002403cc4ae8\n" }, { "commit": "6bb95105b289a4d9015d74af7cb7254455b2344e", "tree": "faf71d64251c88b5aa5caa5512a76eff62601851", "parents": [ "24597d136cc199d8399be2291fda2efb0a652741" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 02 13:21:37 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "feat(rmm) : add api for rec force exit\n\nadd api to force exit a rec\nadded testcase for force exit rec\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I56c70234e236c7d3615237d11c773bdb970012e3\n" }, { "commit": "24597d136cc199d8399be2291fda2efb0a652741", "tree": "686e70f45e398155a42fc811e6abad9eb2a84254", "parents": [ "a29e811d596794b5e135904be9033e9a1662507e" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 02 10:40:19 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "test(rmm-eac4): add testcase for CPU_ON denied\n\n- Testcase creates multiple rec\n- Host receives CPU_ON request from realm\n- Host calls PSCI_CCMPLETE with denied status\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie89b7a3b9603916275913a273751210350075e96\n" }, { "commit": "ab2fe6b01abef3c4b17ffb2c6ee4759f6801e095", "tree": "8285b1a38265e0fa5dd691874d8bf0cdd58aa93f", "parents": [ "406e19135f9fe88bb7794c60012759ca3fb3bdc8", "6e011646ae828f789fc8643e0e6a0c225130cd0c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 27 15:46:09 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 27 15:46:09 2023 +0200" }, "message": "Merge \"feat(handoff): add basic firmware handoff tests\"" }, { "commit": "6e011646ae828f789fc8643e0e6a0c225130cd0c", "tree": "d82ffdaee70f155372aac8519e8244d37f510a6f", "parents": [ "cdf525212326f8b453f22122dddc9d8bf0725981" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Sep 22 17:17:35 2023 +0100" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Oct 27 11:00:34 2023 +0100" }, "message": "feat(handoff): add basic firmware handoff tests\n\nAdd tests to sanity check information shared between BL31 and NS world\nusing the firmware handoff framework.\n\nChange-Id: I9d00292db7732157d0815e6159438c0db08551ad\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "406e19135f9fe88bb7794c60012759ca3fb3bdc8", "tree": "85424a08efd50fbe536c86d7590705807c091774", "parents": [ "a29e811d596794b5e135904be9033e9a1662507e", "5563de011a3aeda175bfc40e2fc094044c6a1ab9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Oct 26 11:27:20 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 26 11:27:20 2023 +0200" }, "message": "Merge \"tests(spmd): check SMCCC NS physical FF-A instance\"" }, { "commit": "a29e811d596794b5e135904be9033e9a1662507e", "tree": "ff959de9f2e05c711dae73bedf2e5b8a34d56f2b", "parents": [ "cbfec24f12c205a8c827604864e2c51f7d419b33", "f369717f93ee8d7e2c12460e71d335bc702e37b4" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Oct 25 19:08:49 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 25 19:08:49 2023 +0200" }, "message": "Merge changes I3fc755f7,I861892f2,I3fa064c7,I10ae5487,I42955f80, ...\n\n* changes:\n test(rme): check various SIMD state preserved across NS/RL switch\n fix(rme): enhance fpu state verification test\n feat(sve): add helper routines to read, write, compare SVE registers\n feat(fpu): add helper routines to read, write, compare FPU registers\n fix(sve): represent sve Z0-31 registers as array of bytes\n test(rme): check if non SVE realm gets undefined abort\n" }, { "commit": "f369717f93ee8d7e2c12460e71d335bc702e37b4", "tree": "ff959de9f2e05c711dae73bedf2e5b8a34d56f2b", "parents": [ "6e587999a0b2f3055d14e08b7bbcfa5735db9891" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Sep 04 15:04:46 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 15:07:15 2023 +0100" }, "message": "test(rme): check various SIMD state preserved across NS/RL switch\n\nThie test case verifies whether various SIMD related registers like\nQ[0-31], FPCR, FPSR, Z[0-31], P[0-15], FFR are preserved by RMM during\nworld switch between NS world and Realm world.\n\nRandomly verify FPU registers or SVE registers if the system supports\nSVE. Within SVE, randomly configure SVE vector length.\n\nThis testcase runs on below configs:\n* with SVE\n* without SVE\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I3fc755f75bdcdc8c24af0440d8a5f094beafca73\n" }, { "commit": "6e587999a0b2f3055d14e08b7bbcfa5735db9891", "tree": "71b8cd6d26c4f039a925c7313807796b0a1ed2bc", "parents": [ "fa05bd9ea226541e860789443b8f68f8d8846390" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 19 14:00:28 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 15:07:15 2023 +0100" }, "message": "fix(rme): enhance fpu state verification test\n\nSelect a random FPU FILL/CMP command to send to different security\nstates in a more effective way. If a FPU FILL command is issued to\nNon-secure or Realm or Secure world, this change ensures that the next\ncommand issued will be a FPU COMPARE command to a security state that is\ndifferent from the previous state.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I861892f2c340bb259eafa14d2fb540645ee5396a\n" }, { "commit": "fa05bd9ea226541e860789443b8f68f8d8846390", "tree": "e63b0399f570e205112b27f7fd92b3d26cbb1a74", "parents": [ "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 14:36:53 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 15:07:14 2023 +0100" }, "message": "feat(sve): add helper routines to read, write, compare SVE registers\n\nAdd helper routines to read, write, write_rand and compare SVE\nZ, P, FFR registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to configure SVE vector length and\nhas to pass memory to read/write SVE registers.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I3fa064c76a498ee2348d92cba2544a6e50331e15\n" }, { "commit": "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045", "tree": "68f9b32383bb80a3542368ebe9ffc15e4bba1c43", "parents": [ "035899729133080ffff3ed691ba65664c34f75ca" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 13:27:36 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:24:42 2023 +0100" }, "message": "feat(fpu): add helper routines to read, write, compare FPU registers\n\nAdd helper routines to read, write, write_rand and compare FPU state\nand FPU control/status registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to pass memory to read/write FPU\nregisters.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I10ae5487c9f58e46434c1bd5b42fd458ec755045\n" }, { "commit": "035899729133080ffff3ed691ba65664c34f75ca", "tree": "02a0b07c127329297d5c28e0683352357c8c0d8a", "parents": [ "73949a20b61def813b3265c2a6a330656bd001af" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 11:04:51 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:15:59 2023 +0100" }, "message": "fix(sve): represent sve Z0-31 registers as array of bytes\n\nCurrently each Z register is type defined as sve_vector_t but the helper\nroutine to write or read Z registers works based on current vector\nlength.\n\nIf test case defines \u0027sve_vector_t zregs[32]\u0027 and reads all Z registers\nusing sve_read_vector_regs() then zregs[n] might not corresponds to Zn\nregister unless the vector length is set to max value.\n\nThis patch also renames sve_vector_length_get() to sve_rdvl_1()\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I42955f8009bdd7f40d74c5a8d21d7c16ce6d761e\n" }, { "commit": "73949a20b61def813b3265c2a6a330656bd001af", "tree": "ab41f5043a87d13fcccbc8bf0473bc2817fa13a4", "parents": [ "cbfec24f12c205a8c827604864e2c51f7d419b33" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 05 12:01:05 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:15:55 2023 +0100" }, "message": "test(rme): check if non SVE realm gets undefined abort\n\nThis test checks whether a non SVE realm receives undefined abort upon\naccessing SVE register state or instructions.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2785488b1344cc4d59dde75e38d9e0d6f856af61\n" }, { "commit": "5563de011a3aeda175bfc40e2fc094044c6a1ab9", "tree": "b116790a2f924f82b8e8579ab85e32ee5a686c83", "parents": [ "cbfec24f12c205a8c827604864e2c51f7d419b33" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Jul 10 10:49:25 2023 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Oct 25 11:26:24 2023 +0200" }, "message": "tests(spmd): check SMCCC NS physical FF-A instance\n\nCheck FF-A ABIs on top of SMCCCv1.2 at NS physical FF-A instance:\n-For FF-A v1.0/v1.1 ABIs that do not require more than 8 registers as\ninput/output.\n-For FF-A v1.2 ABIs using 18 registers as input/output (e.g.\nFFA_PARTITION_INFO_GET_REGS).\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ib5d29c5c5b23f6385215b76af99e5d1f72ca77ac\n" }, { "commit": "cbfec24f12c205a8c827604864e2c51f7d419b33", "tree": "15f4873ed6a1a25d0aea7149e8dd1c79bf5b8727", "parents": [ "32262e88b9de7dc2fe76106fa6945a5654c1ab3f", "f31bbe7807607ca7957db4f9f7316078afea6614" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 24 16:35:31 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 24 16:35:31 2023 +0200" }, "message": "Merge changes I5d06d118,Ic34acf62,Ice7bc03d\n\n* changes:\n test(rmm): add test for multiple rec single cpu\n feat(rmm) : use shared data buf to pass arg to rec\n feat(rmm): add psci api to realms\n" }, { "commit": "32262e88b9de7dc2fe76106fa6945a5654c1ab3f", "tree": "bd9c9d8e6eeba40a81702f88e8cb3bcbb44b9abf", "parents": [ "cdf525212326f8b453f22122dddc9d8bf0725981", "8ce3053050bc37f5cfccadefd575a597ac86dd95" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 24 12:28:28 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 24 12:28:28 2023 +0200" }, "message": "Merge changes from topic \"rmm-1.0-eac4\"\n\n* changes:\n feat(realm): add host call to flush realm prints\n feat(rmm): add support for multiple rec and cpu\n" }, { "commit": "f31bbe7807607ca7957db4f9f7316078afea6614", "tree": "15f4873ed6a1a25d0aea7149e8dd1c79bf5b8727", "parents": [ "52b5f02cf50a79efdaf7bd6682e40a069dec04b7" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Sep 27 14:04:53 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 24 10:44:40 2023 +0100" }, "message": "test(rmm): add test for multiple rec single cpu\n\nTest creates 8 recs and enters the rec\non same PE.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I5d06d1187717ac03d62c05a580e2fbf3c267e0f1\n" }, { "commit": "8ce3053050bc37f5cfccadefd575a597ac86dd95", "tree": "bd9c9d8e6eeba40a81702f88e8cb3bcbb44b9abf", "parents": [ "550e3e88891507cd514fbd8f27d6ba6b8c5a3162" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 16 15:58:38 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(realm): add host call to flush realm prints\n\nadd new host call to push out realm print buffer\nbuffer is flushed after every print statement\n\nChange-Id: I6efa92a7c75ab7df4615a432802426de39d0032c\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "52b5f02cf50a79efdaf7bd6682e40a069dec04b7", "tree": "62b0019e05420486a64cfd7507fb4f2437fd4735", "parents": [ "699cd4feef98deb1e1d3bc95adc42a16da40052d" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Oct 12 22:02:29 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(rmm) : use shared data buf to pass arg to rec\n\nHost can pass arguments to rec using\nper rec shared buffer.\n\nChange-Id: Ic34acf6253031b3b5f184669084f15460b0fc5fd\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "550e3e88891507cd514fbd8f27d6ba6b8c5a3162", "tree": "81485909f1376913447c3480d640f9717bb61de0", "parents": [ "cdf525212326f8b453f22122dddc9d8bf0725981" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Aug 16 13:20:11 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(rmm): add support for multiple rec and cpu\n\nChanges to support creating and\nexecuting multiple rec on multiple cpus.\nAdded per REC shared buffer between Host and Rec.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ib6dbd814ee9f68df4a53f9cfdc8b7f9c905c35fe\n" }, { "commit": "699cd4feef98deb1e1d3bc95adc42a16da40052d", "tree": "dc08fba188c5d63d40f30d5eb382c8d0e680a2ad", "parents": [ "8ce3053050bc37f5cfccadefd575a597ac86dd95" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Sep 27 16:46:54 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(rmm): add psci api to realms\n\nadd wrappers for PSCI APIs\nCPU_ON\nCPU_OFF\nPSCI_AFFINITY_INFO\nPSCI_FEATURES\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ice7bc03d052a0726163c7a31a32f59688e7f516b\n" }, { "commit": "cdf525212326f8b453f22122dddc9d8bf0725981", "tree": "cb2921b3cfa538802547572d0e8ea360bc0eb309", "parents": [ "9b2f7db4f52d6f144641761b2d2b01644b2b6684", "9e267a0f899d699cb840572eb8fc12936ac49d03" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 20 18:49:36 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 20 18:49:36 2023 +0200" }, "message": "Merge \"test: exercise secure espi interrupt handling\"" }, { "commit": "9b2f7db4f52d6f144641761b2d2b01644b2b6684", "tree": "3c3ba03b6f61ce41caebeba94bae5c81427bb5df", "parents": [ "6f74a663f0b2fa1731640d7e74bfb45347bb260e", "04fc4f2f642b0edad8f1a0fa61d132e9cf35e370" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Oct 16 20:07:15 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 16 20:07:15 2023 +0200" }, "message": "Merge \"test(spm): clear memory flag with two constituents\"" }, { "commit": "6f74a663f0b2fa1731640d7e74bfb45347bb260e", "tree": "bf07329f33a6b39d1fc04ec2964370df9dd7cca0", "parents": [ "89a46c094f9b392f146f0d41e6f1e34fd9d0a925", "dbd5ac26d8c10ec32a546b9d4f6c96b20b62091d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Oct 16 20:05:02 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 16 20:05:02 2023 +0200" }, "message": "Merge changes from topic \"ja/ffa_memory_sharing_rme\"\n\n* changes:\n fix(memory share): reclaim and check memory\n test: normal world can\u0027t share root memory\n feat(cactus): use security state attribute\n feat(ff-a): define memory security state attribute\n" }, { "commit": "89a46c094f9b392f146f0d41e6f1e34fd9d0a925", "tree": "5d57bc467fee1ad54c3960d1e2b43b035dd665a6", "parents": [ "2f13adbc1ac240bdee4c901cbd0e09119f17fce4", "fe69a8c4846c20c06efe945c2c6b1f9e893347fa" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Oct 16 18:36:56 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 16 18:36:56 2023 +0200" }, "message": "Merge \"fix(AArch64): Fix issue in processing dynamic relocations\"" }, { "commit": "fe69a8c4846c20c06efe945c2c6b1f9e893347fa", "tree": "5d57bc467fee1ad54c3960d1e2b43b035dd665a6", "parents": [ "2f13adbc1ac240bdee4c901cbd0e09119f17fce4" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Aug 21 11:49:32 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 16 18:36:39 2023 +0200" }, "message": "fix(AArch64): Fix issue in processing dynamic relocations\n\nFixes issue in processing dynamic relocations, when\nrelocation entries not matching R_AARCH64_RELATIVE type are found.\nLinker might generate entries of relocation type R_AARCH64_NONE\n(code 0), which should be ignored to make the code boot.\nSimilar fix done in TF-A (db9736e3d86d7098f9785a9db834746a8b2ed335)\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ibc769efa322618f59c05a6b1596555fc1b00b57b\n" }, { "commit": "04fc4f2f642b0edad8f1a0fa61d132e9cf35e370", "tree": "e2b57b929eef7a2f3e195bc744a83c1fd1ce24c9", "parents": [ "dbd5ac26d8c10ec32a546b9d4f6c96b20b62091d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 11 17:04:52 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Oct 16 15:03:20 2023 +0100" }, "message": "test(spm): clear memory flag with two constituents\n\nAdd another constituent to the test using the clear memory flags\non retrieve request.\nThis is relevant as there was a bug in the SPM implemention\nthat was not clearing correctly multiple constituents in a fragment.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I17cf3f32b111771ca913e84e3e10e5b6f669933e\n" }, { "commit": "dbd5ac26d8c10ec32a546b9d4f6c96b20b62091d", "tree": "5bf81cbf117fb9f66a5ce386ef69412f5a6068b1", "parents": [ "2e58e73b961f336099e521a8ec160b851b26b437" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 19:47:24 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Oct 16 15:01:03 2023 +0100" }, "message": "fix(memory share): reclaim and check memory\n\nIf the test relates with FFA_MEM_DONATE do not reclaim or check memory.\nThe memory is owned by the receiver, and is not accessible to sender.\n\nIf operation is lend/share, TFTF should reclaim memory contents first,\nand then validate that the SP\u0027s access to memory. This is to avoid\nfault on lend, as lender doesn\u0027t have access to memory until after\nthe reclaim.\n\nChange-Id: I548b5cf2ac5c2774123f438a02565723470b4d85\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "9e267a0f899d699cb840572eb8fc12936ac49d03", "tree": "869431e9ca81b7a20027416704453766d7c10f56", "parents": [ "2f13adbc1ac240bdee4c901cbd0e09119f17fce4" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 11 21:25:26 2022 -0700" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 13 12:04:15 2023 -0500" }, "message": "test: exercise secure espi interrupt handling\n\nHafnium/SPMC added support for enabling interrupts in the extended SPI\nrange. With the help of an SiP SMC call that can pend an interrupt,\nthis patch adds a test to trigger an espi interrupt when cactus is\nrunning and ensure it is handled.\n\nAdditionally, a dummy device region node representing a fake\nperipheral has been added to the Cactus SP manifest. It is used to\nspecify properties of the interrupt in the extended SPI range used\nfor the above test scenario.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ief932c40e3abd33d619f2b144e61cae449147b27\n" }, { "commit": "2e58e73b961f336099e521a8ec160b851b26b437", "tree": "7b075e9baaa4d4f827f88b9723f0729d32c1e881", "parents": [ "5e07e7eb18d5b21e1e356b1d040fc9008b8ad221" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 11:57:48 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:10:50 2023 +0100" }, "message": "test: normal world can\u0027t share root memory\n\nIn [1] the invalid access test was removed from the respective\ntests xml file, as it was leveraging a security vulnerability in\nour SPM implementation.\n\nAs part of the same patchstack, we have harnessed and limited the\nmemory that an SP can use via manifest, or memory sharing operations.\nThis patch reestablishes the invalid access that was discarded,\nthis time however only validating that the memory sharing of root\nmemory fails, which should be indicative that the SP can\u0027t access it.\n\nAlso set missing dependency to the source file: spm_test_helpers.c\nto make file tests-invalid-access.mk.\n\nFuture patches will include tests to the GPC.\n\n[1] https://review.trustedfirmware.org/q/topic:%22ja%252Fmem_region_fix%22+(status:open%20OR%20status:merged)\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I6ee21586a2e94810fb4656054b26b2a51c97a544\n" }, { "commit": "2f13adbc1ac240bdee4c901cbd0e09119f17fce4", "tree": "96e756d3146e35c2e90045989174f2052b84f139", "parents": [ "7043e2a82e3b271552744b46fd180c4bc011ccc3", "568cc46ee1584eaf5f388d17bcc43597651060ae" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 13 15:10:41 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 13 15:10:41 2023 +0200" }, "message": "Merge \"fix(spm_common): fix comparison that is always true\"" }, { "commit": "5e07e7eb18d5b21e1e356b1d040fc9008b8ad221", "tree": "2340fad9f8c4ec95fc92dd649b1896f70241ffba", "parents": [ "d13d760570e9d0f640e8bd83bcfbc21240949156" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 14:36:09 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:08:49 2023 +0100" }, "message": "feat(cactus): use security state attribute\n\nCactus uses security attribute from memory transaction\ndescriptor in the shared memory related tests.\n\nChange-Id: I7c4f3ef2c72e36236d23e5a061e27a2ea60fa2d6\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "d13d760570e9d0f640e8bd83bcfbc21240949156", "tree": "a0b70191908599e7242033b0629d97c14c6ce5b6", "parents": [ "7043e2a82e3b271552744b46fd180c4bc011ccc3" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 14:19:03 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:08:49 2023 +0100" }, "message": "feat(ff-a): define memory security state attribute\n\nFF-A v1.1rel0 defines the security state attribute for the\nmemory transaction descriptor. Add respective definition\nto ffa_helpers.h.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Iefb510f5272587bc9faa96731af0159e2379576b\n" }, { "commit": "7043e2a82e3b271552744b46fd180c4bc011ccc3", "tree": "c819ffa35f4e270d06bf7727c1780688b7f125e9", "parents": [ "99243ddd194fb1ee4022a941518d6ddf672692a1", "c28a8dbfb2cda1e4f7f54b1aae51b77990b79ad8" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Oct 13 01:21:34 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 13 01:21:34 2023 +0200" }, "message": "Merge \"Add test for Errata management firmware interface.\"" }, { "commit": "568cc46ee1584eaf5f388d17bcc43597651060ae", "tree": "729ccdba8f947b05fa5057e392df0ea80d21c365", "parents": [ "99243ddd194fb1ee4022a941518d6ddf672692a1" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Oct 12 16:39:30 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Oct 12 16:39:30 2023 +0100" }, "message": "fix(spm_common): fix comparison that is always true\n\nThis comparison always evaluates to true. I assume it was a typo when\ncopy and pasting a line.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I90d8a33b3a9b4ac0aabc9cafa11b5b705ef1aab0\n" }, { "commit": "99243ddd194fb1ee4022a941518d6ddf672692a1", "tree": "512fb996d19060098a9a52772dc70f217192dd02", "parents": [ "c6f3fe090bd72738101d20046cf310ac84bdfbe4", "6e5c99643b199e064f1e8090d963671965ced1d7" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Oct 11 11:03:27 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 11 11:03:27 2023 +0200" }, "message": "Merge changes Iead2dc62,Icf326cf4\n\n* changes:\n fix(rme): append realm.bin at end of tftf.bin\n test(xlat) : fix testcase xlat v2: Stress test\n" }, { "commit": "c28a8dbfb2cda1e4f7f54b1aae51b77990b79ad8", "tree": "a4a7970ae95f9c5ed7e0ee170fcb4303add53337", "parents": [ "c6f3fe090bd72738101d20046cf310ac84bdfbe4" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Sep 28 23:21:54 2023 -0500" }, "committer": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Tue Oct 10 09:59:17 2023 -0500" }, "message": "Add test for Errata management firmware interface.\n\nAdd test to check the em_cpu_erratum_features for\na multiprocessor system.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: Id09fdb837f44fff63c5ca4249accbca046cc06ef\n" }, { "commit": "6e5c99643b199e064f1e8090d963671965ced1d7", "tree": "c5079b4d7de61ed810e5241021b5005d35990ba7", "parents": [ "92b99ee435ebafa5e503b19dce753079ad35218d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Oct 06 16:38:13 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 10 14:31:18 2023 +0100" }, "message": "fix(rme): append realm.bin at end of tftf.bin\n\nCurrently realm.bin is appended to tftf.bin at offset of 10 MB.\nThis patch removes this dependency by reserving empty sections\nfor realm image and dependencies, in tftf binary after\nall loadable sections (end of binary),\nand append realm.bin at end of tftf.bin later in build process.\n\nThe patch removes the need for TFTF to map memory corresponding\nto Realm payload dynamically at runtime.\n\nChange-Id: Iead2dc62ff2965cf7bb03e61c93e76df218da973\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "92b99ee435ebafa5e503b19dce753079ad35218d", "tree": "e55b21ab9abcabcd02b80883a1191a141d0a4ce9", "parents": [ "afffe3a45076fa46a8cd73b0923e06874c8ab135" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 10 14:23:48 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 10 14:30:53 2023 +0100" }, "message": "test(xlat) : fix testcase xlat v2: Stress test\n\nTestcase fails when test tries to unmap memory region\nwith size\u003d0, mapping region with size\u003d0 was success,\nadded workaround to skip mapping if size\u003d0,\nWill need to be fixed in xlat library later.\n\nChange-Id: Icf326cf4889b833e1bd9e064eeeb1f309ae147c6\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "c6f3fe090bd72738101d20046cf310ac84bdfbe4", "tree": "f42a7bc9eaa25c2a9bc697fbfd159b9509b42f13", "parents": [ "fb790e66d7304441434d700987f89c9a07ca8444", "226f4a742e8c0232a34baefac2a7946ae33d4c83" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Oct 09 15:19:12 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 09 15:19:12 2023 +0200" }, "message": "Merge \"docs: update toolchain requirements documentation\"" }, { "commit": "226f4a742e8c0232a34baefac2a7946ae33d4c83", "tree": "f42a7bc9eaa25c2a9bc697fbfd159b9509b42f13", "parents": [ "fb790e66d7304441434d700987f89c9a07ca8444" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Sep 07 11:23:46 2023 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 04 17:35:01 2023 +0100" }, "message": "docs: update toolchain requirements documentation\n\nTF-A tests have been verified with the latest toolchain verison\n12.3.Rel1. Henceforth the requirements are updated.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I4c4c996862f0ca11805002128097c3d1c91d0809\n" }, { "commit": "fb790e66d7304441434d700987f89c9a07ca8444", "tree": "d751b1c0856b93b8e7730c825c614c64b444bad4", "parents": [ "6d8721db1753e0b9fc4252308186d5eb152252a8", "afffe3a45076fa46a8cd73b0923e06874c8ab135" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Oct 03 22:01:07 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 03 22:01:07 2023 +0200" }, "message": "Merge \"fix(spm): instruction permissions on memory sharing\"" }, { "commit": "afffe3a45076fa46a8cd73b0923e06874c8ab135", "tree": "d751b1c0856b93b8e7730c825c614c64b444bad4", "parents": [ "6d8721db1753e0b9fc4252308186d5eb152252a8" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Sep 22 17:14:52 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Sep 28 15:15:38 2023 +0100" }, "message": "fix(spm): instruction permissions on memory sharing\n\n- FFA_MEM_SHARE the instruction access to be used shall be NX,\nhowever both sender and the borrower should leave it not specified.\n- FFA_MEM_LEND/FFA_MEM_DONATE the lender must specify the instruction\npermissions it wishes to receive on the retrieve request.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I0c6e49c30cbbca513644b592695f853bbdf1994b\n" }, { "commit": "6d8721db1753e0b9fc4252308186d5eb152252a8", "tree": "4464d81a42505c45e15b29820533bbf2ea0f894a", "parents": [ "e3c73d226e7a0edafdc49f4be9f5621f5d286454", "30b8bc2aadb82281da999c7264f399d2b7775c42" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Sep 19 14:49:16 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 19 14:49:16 2023 +0200" }, "message": "Merge changes from topic \"xlnx_versal_net_intro\"\n\n* changes:\n docs(versal-net): add Versal NET documentation\n chore(xilinx): reorganize timer code into common path\n feat(versal-net): introduce platform support\n" }, { "commit": "e3c73d226e7a0edafdc49f4be9f5621f5d286454", "tree": "040deae47b58fde8636d6e6b2e0d350eaaa8545f", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41", "4550b49db8ddf98e4445fdd121d3e2bed466b034" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Sep 14 12:46:54 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 14 12:46:54 2023 +0200" }, "message": "Merge changes from topic \"eac2\"\n\n* changes:\n fix(rme): remove RIPAS_UNDEFINED definition\n feat(rme): use RIPAS/HIPAS EAC 2 definitions\n feat(rme): support for PMU as per RMM Specification 1.0-eac2\n feat(rme): add Realm SVE tests for EAC1\n feat(rme): modify API of RMI_RTT_*_RIPAS\n feat(rme): changes in handling RMI_RTT_UNMAP_UNPROTECTED\n feat(rme): update API of data/rtt functions\n feat(rme): remove RMI_VALID_NS status\n feat(rme): remove RMI_ERROR_IN_USE error code\n feat(rme):set size of RsiHostCall.gprs[] to 31\n feat(rme): pass RD pointer in arg0 register X1\n feat(rmm): modify rmi_realm_params structure\n" }, { "commit": "4550b49db8ddf98e4445fdd121d3e2bed466b034", "tree": "040deae47b58fde8636d6e6b2e0d350eaaa8545f", "parents": [ "35b0fa999146f9b1fe12abb237f9eecec42030c8" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Jul 14 12:07:56 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:50:15 2023 +0100" }, "message": "fix(rme): remove RIPAS_UNDEFINED definition\n\nThis patch removes RIPAS_UNDEFINED definition\nand matches RMM-TF patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21987\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I26d6c5e6f7c1053d1b2a7688118e6175985be029\n" }, { "commit": "35b0fa999146f9b1fe12abb237f9eecec42030c8", "tree": "39051ad40d5b1f3415349f9c8a5998c7525380e9", "parents": [ "4067f8610d0d9e89bac0499f09bcbd89d904ff36" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Jul 04 16:24:14 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:50:00 2023 +0100" }, "message": "feat(rme): use RIPAS/HIPAS EAC 2 definitions\n\nThis patch:\n- Modifies HIPAS/RIPAS definitions\n as per RMM Specification 1.0-eac2. It matches\n the changes introdiced by TF-A RMM code patch\n https://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21822\n- Return value of host_realm_destroy_undelegate_range()\n changed from void to u_register_t to report errors in\n the code flow.\n- In \u0027struct rtt_entry\u0027 types of \u0027state\u0027 and \u0027ripas\u0027 fields\n changed from \u0027unsigned int\u0027 to \u0027u_register_t\u0027 to match\n the size of values returned by RMI_RTT_READ_ENTRY command.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ied80fb6e1cd4b2da392514ace33201ffd9fc1da9\n" }, { "commit": "4067f8610d0d9e89bac0499f09bcbd89d904ff36", "tree": "e8f75c7f51dbd6d4237c327a63641df9920b5eaa", "parents": [ "f81345ce2cd13d59cb6efa5847ec02baf54cd489" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Jun 12 12:22:37 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:49:49 2023 +0100" }, "message": "feat(rme): support for PMU as per RMM Specification 1.0-eac2\n\nThis patch introduces PMU changes as per RMM\nSpecification 1.0-eac2:\n- pmu_ovf, pmu_intr_en and pmu_cntr_en fields in RmiRecExit\nare replaced with a synthetic single-bit field pmu_ovf_status\nwhich reports the level of the virtual PMU input to the GIC.\nThis field also includes the state of PMU Enable bit PMCR_EL0.E.\nThese changes match RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21434\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I4135c62927e8156931af9a43a665a19d0e90b342\n" }, { "commit": "f81345ce2cd13d59cb6efa5847ec02baf54cd489", "tree": "ca115e7029fc8f338a96f41ce044583aafa3bc2f", "parents": [ "cd04e41b418decee80a03d25eb7598e7a6b8da95" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 07 17:30:10 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:49:37 2023 +0100" }, "message": "feat(rme): add Realm SVE tests for EAC1\n\nThis patch adds SVE tests for RMM EAC1.\nThe \u0027feature_flag\u0027 parameter passed to\n\u0027host_create_realm_payload()\u0027 function is modified\nto contain \u0027sve_vl\u0027, \u0027num_bps\u0027, \u0027num_wps\u0027 and\n\u0027pmu_num_ctrs entries\u0027. This allows to pass values\nwhich can exceed these fields in feature_register_0\nfor testing. It makes possible to pass\n\u0027Create SVE Realm with invalid VL\u0027 which was\nskipped originally, when SVE was configured with\nthe maximum supported vector length value.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Icd5e57c1bb0cb8dee27b7ace5643aec597e036c1\n" }, { "commit": "cd04e41b418decee80a03d25eb7598e7a6b8da95", "tree": "57050d8f27e3eba6f4a3e5483f6ae0ee2013f630", "parents": [ "ef46c0460838d515f906f3a05aff313729596a51" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Apr 25 14:14:47 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:47:30 2023 +0100" }, "message": "feat(rme): modify API of RMI_RTT_*_RIPAS\n\nThis patch modifies API of RMI_RTT_INIT_RIPAS\nand RMI_RTT_SET_RIPAS commands\u0027 handlers\nas per RMM Specification 1.0-eac1.\nIt matches RMM patches\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20710\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20715\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Id594ca751a1c9ce18607cc8e17bef0bc6214d3ad\n" }, { "commit": "ef46c0460838d515f906f3a05aff313729596a51", "tree": "f02ba79f053da0a5f8f1bdbbcc0aa8ef27ae9842", "parents": [ "1e44db50fb7d1f04c072865e879e7cd5b44a02b8" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Apr 24 12:38:19 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:46:18 2023 +0100" }, "message": "feat(rme): changes in handling RMI_RTT_UNMAP_UNPROTECTED\n\nMake changes in handling RMI_RTT_UNMAP_UNPROTECTED\ncommand as per RMM Specification 1.0-eac1, which now returns\nthe top IPA of non-live RTT entries.\nThis patch matches RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20685\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I5b640db01784c7f9fbd4835d2f4187246443d967\n" }, { "commit": "1e44db50fb7d1f04c072865e879e7cd5b44a02b8", "tree": "456759fe83f4c0f99e90697dc3af29a52a4576ee", "parents": [ "81025b4c9789e0721db8efcacb7632946d2d108c" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Apr 19 17:26:51 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:45:23 2023 +0100" }, "message": "feat(rme): update API of data/rtt functions\n\nThis patch modifies API of host functions calling\nRMI_DATA_DESTROY, RMI_RTT_DESTROY and RMI_RTT_FOLD\ncommands according to RMM Specification 1.0-eac1.\nIt matches changes in RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20604\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I4410ea1cdbc093359b22a0a9495167efbe443c85\n" }, { "commit": "81025b4c9789e0721db8efcacb7632946d2d108c", "tree": "3f27881f023ff485cd6c90d81741565aad4fad86", "parents": [ "ac174ab64b45ee0d943c1e9c60edae5a0e294c77" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Apr 18 11:55:04 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:43:33 2023 +0100" }, "message": "feat(rme): remove RMI_VALID_NS status\n\nThis patch removes RMI_VALID_NS s2tte status as per\nRMM Specification 1.0-eac1, it matches RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20581\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Idcf4f421ec8d4d89d441986f50694c82877b3755\n" }, { "commit": "ac174ab64b45ee0d943c1e9c60edae5a0e294c77", "tree": "f4f637dfcea9bf6c14cfb9de626a4abef8f85963", "parents": [ "3d3dea2c3712b9b3f6b69b1690a6c73aeefc9a3e" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 16:35:22 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:43:21 2023 +0100" }, "message": "feat(rme): remove RMI_ERROR_IN_USE error code\n\nThis patch removes RMI_ERROR_IN_USE error code,\nas per RMM Specification 1.0-eac1, no functional\nmodifications are made.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ia911f9ba07b69d384bbd910f4b4dd3b68646c98a\n" }, { "commit": "3d3dea2c3712b9b3f6b69b1690a6c73aeefc9a3e", "tree": "e94fa3ce32d2f1f956059797fee04ee9a51cb095", "parents": [ "44927c3293c656b878ef1c93e1c8cc4dc92944af" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 15:36:27 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:42:51 2023 +0100" }, "message": "feat(rme):set size of RsiHostCall.gprs[] to 31\n\nThis patch sets the size of gprs[] array in RsiHostCall\nstructure to 31, as per RMM Specification 1.0-eac1.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I81417009b34fca435dd070c94d8e064b8f8bfd9b\n" }, { "commit": "44927c3293c656b878ef1c93e1c8cc4dc92944af", "tree": "1bc325c1ab0b86418f58b3c5159a66066709e719", "parents": [ "b69eae0e22dde3487cc0edcf0c8d2e092f54cf13" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 15:17:13 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Sep 12 16:55:14 2023 +0100" }, "message": "feat(rme): pass RD pointer in arg0 register X1\n\nThis patch makes changes according to RMM Specification\n1.0-eac1 for passing RD pointer in arg0 for RMI_DATA_CREATE,\nRMI_DATA_CREATE_UNKNOWN, RMI_REC_CREATE and RMI_RTT_CREATE\ncommands.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ia19baaf59209b2de06d63cd392c53e3ee19e3ec9\n" }, { "commit": "b69eae0e22dde3487cc0edcf0c8d2e092f54cf13", "tree": "19a9dc33bef7c68b8de1efe361bbd1f7b30434ef", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 10:27:58 2023 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Sep 08 12:24:42 2023 +0200" }, "message": "feat(rmm): modify rmi_realm_params structure\n\nThis patch modifies rmi_realm_params structure\naccording to definition of RmiRealmParams in\nRMM Specification 1.0-eac1.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I63c3097290004de90cd2222b24419aef517d9b49\n" }, { "commit": "30b8bc2aadb82281da999c7264f399d2b7775c42", "tree": "d8204dc54938f125c9510cd79c8f5ff7a62e2972", "parents": [ "1d8f2222855d4bf5c6dac48c43d66560324a04b0" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Aug 25 13:08:01 2023 +0530" }, "committer": { "name": "Michal Šimek", "email": "monstr@monstr.eu", "time": "Fri Sep 08 08:13:10 2023 +0100" }, "message": "docs(versal-net): add Versal NET documentation\n\nAdd information about Versal NET platform for TF-A Tests and provide\nthe build commands.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: If136b0d5d1f8cab12089243750096b18097c6444\n" }, { "commit": "1d8f2222855d4bf5c6dac48c43d66560324a04b0", "tree": "eab8162b1127b3dd6caee080a2808e86dcc0d4a9", "parents": [ "56f41cda007f73b997b687498b7f09fc72d262c6" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Aug 25 12:02:33 2023 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Tue Sep 05 10:29:01 2023 +0530" }, "message": "chore(xilinx): reorganize timer code into common path\n\nReorganized timer code into common folder, updated paths in\nplatform.mk and Versal/Versal NET ttc timer irq in platform_def.h for\nXilinx project.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I504727f55099decf07a208fc95254597e6e24902\n" }, { "commit": "56f41cda007f73b997b687498b7f09fc72d262c6", "tree": "7fe3036ca8fc2943663ed1d5f7389804d28f119c", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Aug 25 11:59:30 2023 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Mon Sep 04 12:01:34 2023 +0530" }, "message": "feat(versal-net): introduce platform support\n\nIntroduce platform support for AMD-Xilinx Versal NET, an adaptive\ncompute acceleration platform (ACAP). The Versal NET is designed to\noffer a wide range of compute, acceleration, and connectivity\noptions, including high-speed networking interfaces.\n\n- pl011 is used for console.\n- TTC is used for Timers.\n- NVM is not supported.\n\nFor Versal devices with 1 cluster and 2 cores, the SCNTR and SCNTRS\nregisters are not accessible from NS EL1, so we are using TTC timers\ninstead.\n\nFor Versal NET devices with 4 clusters and 4 cores per cluster, the\nSCNTR and SCNTRS registers are not accessible from NS EL1, so we\nare using TTC timers instead.\n\nsummary:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 128\nTests Passed : 34\nTests Failed : 7\nTests Crashed : 0\nTotal tests : 169\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nNOTICE: Exiting tests.\n\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I80e76d9f898f5ebca91a403ff802857ea70d7868\n" }, { "commit": "8f6d559b99acc7bb347d3f214c0812e562477a41", "tree": "e47b85a68d09cea2d4b9d29998c2893141ece874", "parents": [ "c68ba0dec2989735fa24a8ed4efcf9cd76af2b05", "507ed939b32d26244412af3f6253a7adcc22420c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Aug 30 16:19:35 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 30 16:19:35 2023 +0200" }, "message": "Merge changes from topic \"jpc/el3-initialize-hfg-el2-regs\"\n\n* changes:\n refactor(fgt): modify FEAT_FGT test to check for init values\n feat(cpufeat): add feat detection helpers\n" } ], "next": "507ed939b32d26244412af3f6253a7adcc22420c" }