)]}'
{
  "log": [
    {
      "commit": "1768e59c3a6ac8d727ac012719b4b09947c8400d",
      "tree": "cc6ad04618bb60fb861bf3e7e4da2538c1a5cf42",
      "parents": [
        "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue May 23 13:28:38 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue Oct 31 13:56:54 2023 +0000"
      },
      "message": "feat(rme): add tests to check NS SME ID registers and configurations\n\nThese tests checks the functionality of RMM for NS SME support.\n- Create Realm and test ID registers specific to SME\n- Check if Realm gets undefined abort when it accesses SME\n- Check whether RMM preserves NS SMCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ia8ffd0188297a74c095dbadfb389add50c548e10\n"
    },
    {
      "commit": "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581",
      "tree": "3e0552b2dae1f333abe34bddd7a4ea63c40f985f",
      "parents": [
        "47b702c49a622e895d70104d78a20bb979dae229"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue Jun 06 16:31:19 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue Oct 31 13:56:17 2023 +0000"
      },
      "message": "feat(sme): add sme helper routines and add streaming sve support\n\nThis patch adds a few helper routines to set the Streaming SVE vector\nlength (SVL) in the SMCR_EL2 register, to enable/disable FEAT_SME_FA64\nand to get CPU\u0027s Streaming SVE mode status.\n\nThis patch also makes SVE compare routines compatible for both normal\nSVE and streaming SVE mode.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7294bb17a85de395a321e99241704066662c90e8\n"
    },
    {
      "commit": "40de8ec10f4d9925c24d2b9dd22822e0c8fd4224",
      "tree": "30347a76b3f2429f8ab3d0f124526d860ee77503",
      "parents": [
        "6bb95105b289a4d9015d74af7cb7254455b2344e"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Oct 12 21:45:12 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Oct 31 02:57:53 2023 +0000"
      },
      "message": "feat(rmm-eac5): update RSI_VERSION, RMI_VERSION\n\nThis patch adds necessary support for RMI_VERSION\nand RSI_VERSION commands.\nMacro SMC_RSI_ABI_VERSION renamed to SMC_RSI_VERSION.\n\nNote.\nThis patch sets both RSI and RMI version numbers to\n1.0 as per RMM Specification 1.0-eac5.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If4eb14d93f657388e2fe64ceefee002403cc4ae8\n"
    },
    {
      "commit": "6bb95105b289a4d9015d74af7cb7254455b2344e",
      "tree": "faf71d64251c88b5aa5caa5512a76eff62601851",
      "parents": [
        "24597d136cc199d8399be2291fda2efb0a652741"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 02 13:21:37 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Oct 31 02:57:53 2023 +0000"
      },
      "message": "feat(rmm) : add api for rec force exit\n\nadd api to force exit a rec\nadded testcase for force exit rec\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I56c70234e236c7d3615237d11c773bdb970012e3\n"
    },
    {
      "commit": "24597d136cc199d8399be2291fda2efb0a652741",
      "tree": "686e70f45e398155a42fc811e6abad9eb2a84254",
      "parents": [
        "a29e811d596794b5e135904be9033e9a1662507e"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 02 10:40:19 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Oct 31 02:57:53 2023 +0000"
      },
      "message": "test(rmm-eac4): add testcase for CPU_ON denied\n\n- Testcase creates multiple rec\n- Host receives CPU_ON request from realm\n- Host calls PSCI_CCMPLETE with denied status\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie89b7a3b9603916275913a273751210350075e96\n"
    },
    {
      "commit": "f369717f93ee8d7e2c12460e71d335bc702e37b4",
      "tree": "ff959de9f2e05c711dae73bedf2e5b8a34d56f2b",
      "parents": [
        "6e587999a0b2f3055d14e08b7bbcfa5735db9891"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Sep 04 15:04:46 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Oct 25 15:07:15 2023 +0100"
      },
      "message": "test(rme): check various SIMD state preserved across NS/RL switch\n\nThie test case verifies whether various SIMD related registers like\nQ[0-31], FPCR, FPSR, Z[0-31], P[0-15], FFR are preserved by RMM during\nworld switch between NS world and Realm world.\n\nRandomly verify FPU registers or SVE registers if the system supports\nSVE. Within SVE, randomly configure SVE vector length.\n\nThis testcase runs on below configs:\n* with SVE\n* without SVE\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I3fc755f75bdcdc8c24af0440d8a5f094beafca73\n"
    },
    {
      "commit": "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045",
      "tree": "68f9b32383bb80a3542368ebe9ffc15e4bba1c43",
      "parents": [
        "035899729133080ffff3ed691ba65664c34f75ca"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Aug 30 13:27:36 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Oct 25 14:24:42 2023 +0100"
      },
      "message": "feat(fpu): add helper routines to read, write, compare FPU registers\n\nAdd helper routines to read, write, write_rand and compare FPU state\nand FPU control/status registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to pass memory to read/write FPU\nregisters.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I10ae5487c9f58e46434c1bd5b42fd458ec755045\n"
    },
    {
      "commit": "035899729133080ffff3ed691ba65664c34f75ca",
      "tree": "02a0b07c127329297d5c28e0683352357c8c0d8a",
      "parents": [
        "73949a20b61def813b3265c2a6a330656bd001af"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Aug 30 11:04:51 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Oct 25 14:15:59 2023 +0100"
      },
      "message": "fix(sve): represent sve Z0-31 registers as array of bytes\n\nCurrently each Z register is type defined as sve_vector_t but the helper\nroutine to write or read Z registers works based on current vector\nlength.\n\nIf test case defines \u0027sve_vector_t zregs[32]\u0027 and reads all Z registers\nusing sve_read_vector_regs() then zregs[n] might not corresponds to Zn\nregister unless the vector length is set to max value.\n\nThis patch also renames sve_vector_length_get() to sve_rdvl_1()\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I42955f8009bdd7f40d74c5a8d21d7c16ce6d761e\n"
    },
    {
      "commit": "73949a20b61def813b3265c2a6a330656bd001af",
      "tree": "ab41f5043a87d13fcccbc8bf0473bc2817fa13a4",
      "parents": [
        "cbfec24f12c205a8c827604864e2c51f7d419b33"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Jun 05 12:01:05 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Oct 25 14:15:55 2023 +0100"
      },
      "message": "test(rme): check if non SVE realm gets undefined abort\n\nThis test checks whether a non SVE realm receives undefined abort upon\naccessing SVE register state or instructions.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2785488b1344cc4d59dde75e38d9e0d6f856af61\n"
    },
    {
      "commit": "52b5f02cf50a79efdaf7bd6682e40a069dec04b7",
      "tree": "62b0019e05420486a64cfd7507fb4f2437fd4735",
      "parents": [
        "699cd4feef98deb1e1d3bc95adc42a16da40052d"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Oct 12 22:02:29 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 23 19:34:54 2023 +0200"
      },
      "message": "feat(rmm) : use shared data buf to pass arg to rec\n\nHost can pass arguments to rec using\nper rec shared buffer.\n\nChange-Id: Ic34acf6253031b3b5f184669084f15460b0fc5fd\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "699cd4feef98deb1e1d3bc95adc42a16da40052d",
      "tree": "dc08fba188c5d63d40f30d5eb382c8d0e680a2ad",
      "parents": [
        "8ce3053050bc37f5cfccadefd575a597ac86dd95"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Sep 27 16:46:54 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 23 19:34:54 2023 +0200"
      },
      "message": "feat(rmm): add psci api to realms\n\nadd wrappers for PSCI APIs\nCPU_ON\nCPU_OFF\nPSCI_AFFINITY_INFO\nPSCI_FEATURES\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ice7bc03d052a0726163c7a31a32f59688e7f516b\n"
    },
    {
      "commit": "8ce3053050bc37f5cfccadefd575a597ac86dd95",
      "tree": "bd9c9d8e6eeba40a81702f88e8cb3bcbb44b9abf",
      "parents": [
        "550e3e88891507cd514fbd8f27d6ba6b8c5a3162"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 16 15:58:38 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 23 19:34:54 2023 +0200"
      },
      "message": "feat(realm): add host call to flush realm prints\n\nadd new host call to push out realm print buffer\nbuffer is flushed after every print statement\n\nChange-Id: I6efa92a7c75ab7df4615a432802426de39d0032c\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "550e3e88891507cd514fbd8f27d6ba6b8c5a3162",
      "tree": "81485909f1376913447c3480d640f9717bb61de0",
      "parents": [
        "cdf525212326f8b453f22122dddc9d8bf0725981"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Aug 16 13:20:11 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 23 19:34:54 2023 +0200"
      },
      "message": "feat(rmm): add support for multiple rec and cpu\n\nChanges to support creating and\nexecuting  multiple rec on multiple cpus.\nAdded per REC shared buffer between Host and Rec.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ib6dbd814ee9f68df4a53f9cfdc8b7f9c905c35fe\n"
    },
    {
      "commit": "3d3dea2c3712b9b3f6b69b1690a6c73aeefc9a3e",
      "tree": "e94fa3ce32d2f1f956059797fee04ee9a51cb095",
      "parents": [
        "44927c3293c656b878ef1c93e1c8cc4dc92944af"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Thu Apr 06 15:36:27 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Wed Sep 13 09:42:51 2023 +0100"
      },
      "message": "feat(rme):set size of RsiHostCall.gprs[] to 31\n\nThis patch sets the size of gprs[] array in RsiHostCall\nstructure to 31, as per RMM Specification 1.0-eac1.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I81417009b34fca435dd070c94d8e064b8f8bfd9b\n"
    },
    {
      "commit": "9d0cfe88aedc34f1b61a51ff18013743c56e2fbc",
      "tree": "b5b65d1a477d3d46aacfb69bd3dff348a2136ce4",
      "parents": [
        "85d58f31f121445225c2b9e6ee94c8589cc36669"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Apr 17 10:57:26 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Tue Jul 25 17:00:33 2023 +0100"
      },
      "message": "test(tftf): test PAuth in Realm\n\n- Enable PAuth in Realm RL1 by default.\n- Check if PAuth keys are accessible in Realm RL1.\n- Check if Realm PAuth keys are preserved across RMM entry/exit.\n- Check if NS PAuth keys are preserved across RMM entry/exit.\n- Generate PAuth fault by cloberring LR.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I85d8e03ec604c96117555e7aa866453cb2745cfe\n"
    },
    {
      "commit": "fb98ffd60a30c8d2b67b49bf7482fff8be7c6488",
      "tree": "3a192f12127f5c2f7c5a323dac343c5c4caa5ff8",
      "parents": [
        "9af432e408b3e66f3e4cd00cbc98486c7bd9be03"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Jun 05 11:33:33 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Jun 05 13:53:56 2023 +0100"
      },
      "message": "fix(realm): align realm stack\n\nrealm_entrypoint fails while accessing unaligned stack base. This\nissue happens when a newly added global variable shifts the end of\nstack to be unaligned.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I75901a2ead41adc0a19f92896be9e75b1fc882c6\n"
    },
    {
      "commit": "9af432e408b3e66f3e4cd00cbc98486c7bd9be03",
      "tree": "5dd128bc21f399ec872ecb9d8b969d29784ef78e",
      "parents": [
        "8ebb89cae65a199e80894775b80a202f50e94cec"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Fri Jun 02 17:18:23 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Jun 05 11:52:21 2023 +0100"
      },
      "message": "fix(tftf): command id passed to realm to compare FPU registers\n\nThis fixes the command id passed to Realm to compare FPU/SIMD regs.\nAnd also adds a missing break statement in Realm payload main entry\nfunction for command REALM_REQ_FPU_CMP_CMD.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Iaf7073475291785990a55675746968b291fdf507\n"
    },
    {
      "commit": "5270d01e968b1b0a8b853a9263e767a467e541b9",
      "tree": "ac67959df7b5d536b4c662ed1f0a0e2f19970980",
      "parents": [
        "c1136a849fc21470313e4e852a22ae4b9db50440"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Apr 19 14:53:42 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed May 24 13:40:42 2023 +0100"
      },
      "message": "tftf(rme): check if RMM doesn\u0027t leak Realm contents in SVE registers\n\nThis test verifies that the Realm contents in SVE registers are not\nseen by NS world once the Realm returns back to the host. This test\nperforms the below steps:\n\n1. Set NS world SVE VQ to max and write a known pattern.\n2. Set NS world ZCR_EL2 with VQ as 0 (128 bits).\n3. Create Realm with max SVE VQ\n4. Call Realm to fill in Z registers\n5. Once Realm returns, NS sets ZCR_EL2 with max VQ and reads the\n   Z registers.\n6. The upper bits of Z registers must be either 0 or the old values\n   filled by NS world at step 1.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I8205190d1ce9c37b99d35cf5b15df21ca9b838c3\n"
    },
    {
      "commit": "c1136a849fc21470313e4e852a22ae4b9db50440",
      "tree": "b6b5e8854589497f4e2d2c159f0bd2e590dcd8c5",
      "parents": [
        "d179ddcc64cac3b319b301cfe6c1bc32c1ea0eaf"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Apr 12 15:24:44 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed May 24 13:40:42 2023 +0100"
      },
      "message": "tftf(rme): intermittently switch to Realm while doing NS SVE ops\n\nInterleave NS SVE operations with Realm SVE operations and check whether\nSVE vectors are not affected.\n\nThis test also configures SVE op array and SVE vector length with random\nvalue in NS and Realm for test each iteration.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7a9ba4bd0d298f187baa3048ec622eb97ec3d99f\n"
    },
    {
      "commit": "0bbdc2dff449036aa65e4c53cd351d01484e0d23",
      "tree": "60f35abe7f72ade6409b3ffcd46262502a9b6885",
      "parents": [
        "ed7cdc8b28137ab15d9f263825674d156b3c2b30"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Apr 05 15:30:18 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Thu May 18 16:08:39 2023 +0100"
      },
      "message": "feat(rme): add SVE Realm tests\n\nVerifies Realm with SVE support. Below tests are added\n- Check whether RMI features reports proper SVE VL\n- Create SVE Realm and check rdvl result\n- Create SVE Realm with invalid VL and check if it fails\n- Create SVE Realm and test ID registers\n- Create non SVE Realm and test ID registers\n- Create SVE Realm and probe all supported VLs\n- Check RMM preserves NS ZCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I98a20f34ce72c7c1a353ed13678870168fa27c48\n"
    },
    {
      "commit": "369955abac0a083f57bfb787eeda82a511eb8fc0",
      "tree": "54a35fd1b033a708569c91f2dfb1e1516d690cec",
      "parents": [
        "38133fa69bfefab6e3d1d7461b42c806d36ae33b"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Apr 19 18:05:56 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri May 05 13:56:12 2023 +0100"
      },
      "message": "test(tftf): test FPU state registers context is preserved in RL/SE/NS\n\nTest that FPU/SIMD state are preserved during a randomly context switch\nbetween secure/non-secure/realm(R-EL1)worlds.\nFPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers,\nthe test runs for 1000 iterations with random combination of:\nSECURE_FILL_FPU, SECURE_READ_FPU, REALM_FILL_FPU, REALM_READ_FPU,\nNONSECURE_FILL_FPU, NONSECURE_READ_FPU commands,to test all possible\nsituations of synchronous context switch between worlds, while the\ncontent of those registers is being used.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I6da5fd334777000111924bb1239b77123a3dcea6\n"
    },
    {
      "commit": "2f30f1030f186760b20cd06b59832e332b2bdd0a",
      "tree": "e06899ba1be405650b4a15603429900dac67ccc2",
      "parents": [
        "2eb601b98a245df8a31e670a7dc322c2e8f153cf"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Mon Mar 13 19:37:46 2023 +0000"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Fri Mar 31 11:41:56 2023 +0200"
      },
      "message": "feat(rme): add PMU Realm tests\n\nThis patch adds Realm PMU payload tests with\nPMU interrupt handling.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2\n"
    },
    {
      "commit": "002e569021f2e219456d02dfe239218eba5c7cfa",
      "tree": "4c2ea2d7cce38d168ce5e03849498161d537f1c2",
      "parents": [
        "0fcfd47a5936180b754819ee928e8d5af173c5d2"
      ],
      "author": {
        "name": "nabkah01",
        "email": "nabil.kahlouche@arm.com",
        "time": "Mon Oct 10 12:36:46 2022 +0100"
      },
      "committer": {
        "name": "nabkah01",
        "email": "nabil.kahlouche@arm.com",
        "time": "Tue Nov 08 16:34:01 2022 +0000"
      },
      "message": "feat: tftf realm extension\n\nThis patch adds Realm payload management capabilities to TFTF\nto act as a NS Host, it includes creation and destruction of a Realm,\nmapping of protected data and creation of all needed RTT levels,\nsharing of NS memory buffer from Host to Realm by mapping of\nunprotected IPA, create REC and auxiliary granules, exit Realm\nusing RSI_HOST_CALL ABI.\n\nOlder realm_payload name is used now for only R-EL1 test cases,\nRMI and SPM test cases have been moved to new file tests-rmi-spm.\n\nNew TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk,\nas an offset from where R-EL1 payload memory resources start.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7\n"
    }
  ]
}