)]}' { "log": [ { "commit": "3650d9cdfaa8eda20eba4b0c366c7c213a356557", "tree": "39ef73f5a1aace7ba04a2bde89390121a03d2d6c", "parents": [ "fdbd5857fe0a2d29d9eb7ffb7bb9023e387cdfcb", "a06b808ca77122612185e4f4db56208dd706ba8a" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 23 12:26:44 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 23 12:26:44 2025 +0000" }, "message": "Merge changes from topic \"for-lts-v2.12.3\" into lts-v2.12\n\n* changes:\n feat(mbedtls): update mbedtls to version 3.6.3\n feat(mbedtls): update mbedtls to version 3.6.3\n feat(mbedtls): update minimum version to latest MbedTLS v3.6.2\n feat(lib): add mbedtls support\n feat(realm): add MbedTLS as submodule\n" }, { "commit": "a06b808ca77122612185e4f4db56208dd706ba8a", "tree": "39ef73f5a1aace7ba04a2bde89390121a03d2d6c", "parents": [ "504df476ea6bea4610b874fcf3791509e201c23a" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Mon Apr 07 13:18:19 2025 -0500" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 16 17:28:32 2025 +0200" }, "message": "feat(mbedtls): update mbedtls to version 3.6.3\n\nUpdate additional mbedtls submodule to version 3.6.3.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I69814f9a5e7e0c260169111a7ec1dd42dbc3679c\n(cherry picked from commit 69a9c4027085d4331f54aa1cc753626749812168)\n" }, { "commit": "504df476ea6bea4610b874fcf3791509e201c23a", "tree": "0a67975cbc2638c0b49acfd36ecfe6e06ebfd95f", "parents": [ "f89ca7312142e8ef64b66de3f90e456ad82a3a00" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 03 12:49:06 2025 -0500" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 16 17:28:30 2025 +0200" }, "message": "feat(mbedtls): update mbedtls to version 3.6.3\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I4bfb546c351c30a6fc4d22f29bc03efad316df7d\n(cherry picked from commit d5bb5f6c82f7ebcf28dccbbfad058e27e207c14f)\n" }, { "commit": "f89ca7312142e8ef64b66de3f90e456ad82a3a00", "tree": "c564d6e4da84106cbda3cc975c66774f35505026", "parents": [ "388cd8d71893432d68e65fa1ae59d62e6d90f660" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Dec 17 09:14:50 2024 +0000" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 16 17:28:28 2025 +0200" }, "message": "feat(mbedtls): update minimum version to latest MbedTLS v3.6.2\n\nUse the latest MbedTLS version 3.6.2 as the minimum to stay in\nsync with TF-A.\n\nChange-Id: I4c70ec87805a99ba0cfaf2c23cfea51133d0daf7\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n(cherry picked from commit d8092a550b85c6369aabf96430c9b06cc8444298)\n" }, { "commit": "388cd8d71893432d68e65fa1ae59d62e6d90f660", "tree": "6d06522bfc86e7d146430fea148e67ca04ce5923", "parents": [ "1525915acc9057163cfeb71ca2b143cbf493904e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 12:19:32 2024 +0000" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 16 17:28:26 2025 +0200" }, "message": "feat(lib): add mbedtls support\n\nAdd support for compiling Mbed TLS from external source.\n\nThe Mbed TLS library is compiled from source pointed by MBEDTLS_DIR\nenvironment variable. Any TFTF test that includes mbedtls.mk will have\nsupport for mbedtls library. Note that by default the MBEDTLS_DIR will\npoint to the default submodule directory (ext/mbedtls).\n\nThis support is added for testing RMM capabilities related to\nDevice Assignment in RMM.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I0e386334078812e5ff5bdcffd4143732e0478b64\n(cherry picked from commit 23788fa84220f873a21f8bca53d973e240ae8740)\n" }, { "commit": "1525915acc9057163cfeb71ca2b143cbf493904e", "tree": "0df65cff7b341469b5007827310ae14b4a69bd44", "parents": [ "fdbd5857fe0a2d29d9eb7ffb7bb9023e387cdfcb" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 04:39:38 2024 +0000" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 16 17:28:11 2025 +0200" }, "message": "feat(realm): add MbedTLS as submodule\n\nThis patch adds MbedTLS repository as a git submodule.\nThe version of MbedTLS added is v3.6.2.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I744ef44e61c85ade3d56920cfc1b8fd1a27bb045\n(cherry picked from commit c5f75b914824a6c3cb992596b44f1c2a116eb7d3)\n" }, { "commit": "fdbd5857fe0a2d29d9eb7ffb7bb9023e387cdfcb", "tree": "084ae228feef23eca7e2fec7a6253e93c4c2a41d", "parents": [ "6a113621a9efdc143e9270b1789046cd7d9cdfb1", "ab800fffd328b690ce89647b4fa1c97fea677b67" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 18 23:36:43 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 18 23:36:43 2025 +0100" }, "message": "Merge \"test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\" into lts-v2.12" }, { "commit": "ab800fffd328b690ce89647b4fa1c97fea677b67", "tree": "084ae228feef23eca7e2fec7a6253e93c4c2a41d", "parents": [ "6a113621a9efdc143e9270b1789046cd7d9cdfb1" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Feb 07 17:59:35 2025 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Feb 07 17:59:35 2025 +0100" }, "message": "test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\n\nTesting was conducted using FVP Version 11.26.11\non Cortex-X3, Cortex-X4, Neoverse-V2, Neoverse-V3\nand Cortex-X925. Additionally, negative testing\nwas performed on Cortex-X2.\n\nThis patch tests SMCCC_ARCH_WORKAROUND_4 [1] for CVE_2024_7881 [2]\n[1]: https://developer.arm.com/documentation/den0028/latest\n[2]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881\n\nChange-Id: I4c33b7a9372236ce3ef38f9d1786d5794bb7ddbc\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n(cherry picked from commit 43d421bb292984fdc56269fb3e87e619ca0892d3)\n" }, { "commit": "6a113621a9efdc143e9270b1789046cd7d9cdfb1", "tree": "99e0b5dc52529869eae94348826fc1a51c0b7b04", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa", "cf898bbaa402c3202641829558300c744dd0cd99" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Nov 20 23:26:34 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 20 23:26:34 2024 +0100" }, "message": "Merge \"docs(release): changelog for v2.12 release\"" }, { "commit": "cf898bbaa402c3202641829558300c744dd0cd99", "tree": "99e0b5dc52529869eae94348826fc1a51c0b7b04", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Nov 15 09:43:11 2024 +0000" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Nov 20 11:18:21 2024 -0600" }, "message": "docs(release): changelog for v2.12 release\n\nChange-Id: I5f4eb0ccff8dcd7e5cf3cd8c475057495e53c28f\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "b607317afc8c6ad5f37ac8873dfa8777c50b96aa", "tree": "ade1fb648af0b10a6080c9a8035962b7ef0176f3", "parents": [ "6abf05e7077e19281443e773012bc81e8e659786", "784c6d220ea2b62b20e58eb814ba379349ce1665" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Nov 19 15:50:14 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 19 15:50:14 2024 +0100" }, "message": "Merge changes from topic \"xlnx_plat_skip_query_pmf\"\n\n* changes:\n fix(zynqmp): update test skip list\n fix(versal-net): update test skip list\n fix(versal): update test skip list\n" }, { "commit": "6abf05e7077e19281443e773012bc81e8e659786", "tree": "13ad5ef729e1eda7fc70c89969dd774319806f25", "parents": [ "b2b581650c4af293b734a45430ba49bccd96d60d", "16059ac52d8f221c921e0766bc2b714ee52e06ed" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 12:55:00 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 19 12:55:00 2024 +0100" }, "message": "Merge \"fix: add sysreg define for ID_AA64MMFR3_EL1\"" }, { "commit": "16059ac52d8f221c921e0766bc2b714ee52e06ed", "tree": "13ad5ef729e1eda7fc70c89969dd774319806f25", "parents": [ "b2b581650c4af293b734a45430ba49bccd96d60d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 11:15:22 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 13:19:55 2024 +0200" }, "message": "fix: add sysreg define for ID_AA64MMFR3_EL1\n\nThe patch 7c78f7b4a removed the definition for ID_AA64MMFR3_EL1 sysreg.\nThis define is needed for older GCC (like GCC 11) to compile TFTF\nsuccessfully. This patch restores the define.\n\nChange-Id: I18f8e00830c8e72807b6f1613e9d9864f12669ba\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "b2b581650c4af293b734a45430ba49bccd96d60d", "tree": "ce322be37116651bf3ab1d681632c176f8105233", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade", "46d0228e2a1a17c57be8f5011f183ea28e6ba518" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 11:23:40 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 19 11:23:40 2024 +0100" }, "message": "Merge changes from topics \"FEAT_DoubleFault2\", \"mb/serr-fix\"\n\n* changes:\n fix(serror): use custom argument for incrementing elr_elx\n feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n" }, { "commit": "46d0228e2a1a17c57be8f5011f183ea28e6ba518", "tree": "ce322be37116651bf3ab1d681632c176f8105233", "parents": [ "7c78f7b4a74e58512ff6998f7a5438520e58c343" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Nov 18 16:58:37 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Nov 19 11:22:08 2024 +0100" }, "message": "fix(serror): use custom argument for incrementing elr_elx\n\nAdd a custom argument to increment the elr_elx after handling SError.\nIn some cases, to prevent re-triggering the instruction, ELR needs\nto be incremented by 4. In other cases, it may not be necessary.\n\nThis argument is passed to the handler, which then decides whether\nto increment elr_elx by setting the passed argument accordingly after\nhandling the SError.\n\nChange-Id: I404f3c5e24f894502a8d00c73649be0b2dd540fa\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "7c78f7b4a74e58512ff6998f7a5438520e58c343", "tree": "ea7bd3a6363d1bf5686e5cfbd2a92cabec7a3df6", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Oct 25 11:44:32 2024 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Nov 19 10:10:16 2024 +0000" }, "message": "feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n\nWhen FEAT_DoubleFault2 is supported, TF-RMM must take into\naccount bit SCTLR2_EL1.EASE in order to decide whether to inject\na SEA into the sync exception vector or into the serror one.\n\nThe test on this patch verifies that TF-RMM injects the SEA\nto the right vector depending on SCTLR2.EASE bit.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c976fecb04d123e3efb96c5973b1466e241097f\n" }, { "commit": "784c6d220ea2b62b20e58eb814ba379349ce1665", "tree": "56b6ce66cb9fd60b5d96f0680fc479e40f61e9c2", "parents": [ "746b32be41f26c3cb29031bb01ab0c3efd3d890b" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Nov 15 09:32:52 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Mon Nov 18 08:23:36 2024 +0000" }, "message": "fix(zynqmp): update test skip list\n\nTest cases \"Query Vendor-Specific Service\" and \"Probe PMF version\"\nare failing since PMF is not supported on AMD platform.\nTest cases will be skipped till non-availability of PMF support.\n\nChange-Id: I82c85838b2b10ccf2d044925b7b713a0edf5556a\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "4c19b48e1d0aed1cfb94785c86544d2a58190ade", "tree": "94a32197863ac3dc2d6a050eb4321887fdf41ceb", "parents": [ "27f833a0817002e1ea9b88e11ba173357588afcc", "f675feb04d6583e80770a1cda48989a3f27e61fa" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Nov 14 17:25:42 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 14 17:25:42 2024 +0100" }, "message": "Merge \"fix(versal2): move timer clk offset definition to platform header\"" }, { "commit": "f675feb04d6583e80770a1cda48989a3f27e61fa", "tree": "94a32197863ac3dc2d6a050eb4321887fdf41ceb", "parents": [ "27f833a0817002e1ea9b88e11ba173357588afcc" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Wed Nov 13 11:37:30 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Thu Nov 14 09:09:57 2024 +0000" }, "message": "fix(versal2): move timer clk offset definition to platform header\n\nFor Versal2 platform TTC_CLK_SEL_OFFSET is defined in common timers source\nwhich is creating build conflict for other platform.\n\nMoving the definition for TTC_CLK_SEL_OFFSET to versal2 platform header.\n\nChange-Id: I1e2db4c591520be12e568d84da290b17d72bf897\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "27f833a0817002e1ea9b88e11ba173357588afcc", "tree": "37a9c57f2fed61dc7115b4a0104a62567d390834", "parents": [ "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f", "891856dd39671e0f996a5ac5c21e7444c24c49eb" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Nov 12 16:59:17 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 12 16:59:17 2024 +0100" }, "message": "Merge \"fix(timer): enable virtual timer in respective test\"" }, { "commit": "891856dd39671e0f996a5ac5c21e7444c24c49eb", "tree": "37a9c57f2fed61dc7115b4a0104a62567d390834", "parents": [ "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 12 14:02:46 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 12 15:14:31 2024 +0000" }, "message": "fix(timer): enable virtual timer in respective test\n\nThe virtual timer interrupt was enabled from main function.\nEnablement HVC is implementation defined to Hafnium SPMC.\n\nCactus SP is loaded on top of EL3 SPMC tests in spm-l3-boot-tests\ngroup, which failed due to enablement function.\n\nThis patch moves the code enabling code from cactus main\ninto the respective command handler to operate the architectural\ntimer.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Iee7b884003ca1e9b7fcee4e89b563970ffe753a0\n" }, { "commit": "746b32be41f26c3cb29031bb01ab0c3efd3d890b", "tree": "e94b5d241de2e796ae6a540c814ea9eb00072194", "parents": [ "ac24bb830b3b6da926c71aec40150688fd3c338d" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 05 06:18:51 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 12 03:23:10 2024 +0000" }, "message": "fix(versal-net): update test skip list\n\nTest cases \"Query Vendor-Specific Service\" and \"Probe PMF version\"\nare failing since PMF is not supported on AMD platform.\nTest cases will be skipped till non-availability of PMF support.\n\nChange-Id: I40fd7defea853d0a1aee5da79924d4ee5c15cfaa\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "ac24bb830b3b6da926c71aec40150688fd3c338d", "tree": "280ce1e731cbb573344a9a7dec1fa453d3abd38f", "parents": [ "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 05 06:18:39 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 12 03:23:03 2024 +0000" }, "message": "fix(versal): update test skip list\n\nTest cases \"Query Vendor-Specific Service\" and \"Probe PMF version\"\nare failing since PMF is not supported on AMD platform.\nTest cases will be skipped till non-availability of PMF support.\n\nChange-Id: I560ee5b69244cee13003a71c8ecc5848a1b903e6\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f", "tree": "f8979bc2f589f87671ed5e50216364e64e1dc06d", "parents": [ "a7aa825f328ce0d844f134af8f0cd7468f811d07", "e9c18128b5234f1e76aa0147666d04de61bca93b" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Nov 11 18:48:06 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 11 18:48:06 2024 +0100" }, "message": "Merge \"test: arch timer in nwd is honored across world switch\"" }, { "commit": "a7aa825f328ce0d844f134af8f0cd7468f811d07", "tree": "4775918602e40087fcf0f9a9795009292b961972", "parents": [ "0d42dceeb1382652091f709d2d286773b46a4936", "e42561dbcd9d66d4de22d1b2bf48e124872b815c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Nov 11 16:03:08 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 11 16:03:08 2024 +0100" }, "message": "Merge \"fix: update definitions for sysregs on older toolchains\"" }, { "commit": "0d42dceeb1382652091f709d2d286773b46a4936", "tree": "2c2dc48110b1fbabc90a96a78483bd885868c5bb", "parents": [ "73d5bbd188aa33ad7ef4c28acbddaf2d8b9433a7", "11221142eac86235c7efdec6eb8ba195c14af8e8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Nov 11 14:36:53 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 11 14:36:53 2024 +0100" }, "message": "Merge changes Ibafc696c,I2d976951\n\n* changes:\n fix(build): add a dependency to the build directory\n fix(build): use a grouped target for the tests_list files\n" }, { "commit": "e42561dbcd9d66d4de22d1b2bf48e124872b815c", "tree": "eab01079c905b0f119a826ca02ecb8e65a642647", "parents": [ "73d5bbd188aa33ad7ef4c28acbddaf2d8b9433a7" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Nov 11 11:22:03 2024 +0100" }, "committer": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Nov 11 13:00:46 2024 +0100" }, "message": "fix: update definitions for sysregs on older toolchains\n\nThe patch 0db4a3cd added new sysreg access which older toolchains\ndo not support. This fix opts to use the renaming variant of the\nnecessary preprocessor macros for the registers used as part of\nthat patch, so that TFTF can compile with older toolchains.\n\nChange-Id: I1d4cdfc3f67a085af35a3b51477eda79e9e93db7\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "73d5bbd188aa33ad7ef4c28acbddaf2d8b9433a7", "tree": "b5d66c48a39a422a902364d694a41521c35de431", "parents": [ "8e65838b7baaf9a0c57582aa7deee11d78012931", "4b67210c4ae32e723fc5805f3b7e8c48fb8ec962" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Nov 08 18:41:30 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 08 18:41:30 2024 +0100" }, "message": "Merge changes from topic \"jc/context_mgmt_tests\"\n\n* changes:\n feat(cm): add test to validate EL2 regs during context switch\n feat(cm): add el2-ctx registers helper macros\n feat(cm): add tests to validate EL1 regs during context switch\n feat(cm): add el1-ctx register helper macros\n" }, { "commit": "4b67210c4ae32e723fc5805f3b7e8c48fb8ec962", "tree": "b5d66c48a39a422a902364d694a41521c35de431", "parents": [ "0db4a3cdde090a94721a8a598cbbbf857f7cf47f" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Sep 23 13:06:15 2024 +0200" }, "committer": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Fri Nov 08 17:48:28 2024 +0100" }, "message": "feat(cm): add test to validate EL2 regs during context switch\n\nVerify that EL2 system registers are preserved when switching\nfrom Normal world to Secure world and vice versa. Do this by\nmodifying the live EL2 register state and dumping it to memory,\nthen performing an FF-A Cactus call and checking whether the\nstate matches the previously saved context.\n\nChange-Id: I0537b4d671c72c0a2fd29ac7e218bf69e1c66001\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "0db4a3cdde090a94721a8a598cbbbf857f7cf47f", "tree": "30581ed1d668fe4be2075f5ce034dedc1e3ee5e3", "parents": [ "86e5e5d500a839920edcf71783f31b7e4fc20c42" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Sep 23 12:52:15 2024 +0200" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 16:52:44 2024 +0000" }, "message": "feat(cm): add el2-ctx registers helper macros\n\nThis patch adds the necessary definitions for the registers\nand helpers that are used in the EL2 context switch test.\n\nChange-Id: Ie846f9341d600ae8fb7a46a9655a8f8ee62d84b0\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "86e5e5d500a839920edcf71783f31b7e4fc20c42", "tree": "c9b96514811730ade3be4cd5449254025502fb07", "parents": [ "af49307617a6861c13008371a1e5397b278bb4c7" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Aug 05 19:52:29 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 16:52:38 2024 +0000" }, "message": "feat(cm): add tests to validate EL1 regs during context switch\n\n* This patch adds a test to verify the integrity of the el1_context\n registers across world-switch.\n\n* It aims at testing the save and restore functionality provided\n by the EL3 context management library.\n\n* It validates the EL1 ctx register entries after interaction with\n TSP (S-EL1) software.\n\nChange-Id: Id435d9d7699231d66e9e7acdbb3459ec439d2aef\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "af49307617a6861c13008371a1e5397b278bb4c7", "tree": "8f8243c121303783723ef96c2994bb7a388c5947", "parents": [ "8e65838b7baaf9a0c57582aa7deee11d78012931" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Aug 12 17:26:10 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 11:29:43 2024 +0000" }, "message": "feat(cm): add el1-ctx register helper macros\n\nAdding EL1 context registers related helper macros\nnecessary to test EL1 context entries.\n\nChange-Id: Ifb0149ad78f951958990290b496e7c1b92c072ea\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "e9c18128b5234f1e76aa0147666d04de61bca93b", "tree": "0f9061891055da886d987e8245b046d8eaf4288b", "parents": [ "97ee573bf9b34d8d8352b6a8af2f2c47c0f41bf9" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Sep 10 16:28:48 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Nov 06 17:31:31 2024 -0600" }, "message": "test: arch timer in nwd is honored across world switch\n\nThis patch introduces a test to ensure that the functionality of arch\n(EL1 physical) timer configured by NWd endpoint, such as an hypervisor,\nis not corrupted by SPMC when an SP also configures the arch timer for\nits own use.\n\nAlso, necessary helpers and utilities to create the test scenario have\nbeen added.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I1cfd1e1117412b2b23a57af30064c41dc2e66e0b\n" }, { "commit": "8e65838b7baaf9a0c57582aa7deee11d78012931", "tree": "6fba961e72767d7a0c58b914acc24723190802a3", "parents": [ "a62262f047c9c48c65021f4e23be7b709e8c2811", "72b7ce11edd6042d5a3fe75bba83fb5e7f58ee08" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Nov 06 21:56:30 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 06 21:56:30 2024 +0100" }, "message": "Merge \"feat(ls64): add LS64_ACCDATA test\"" }, { "commit": "72b7ce11edd6042d5a3fe75bba83fb5e7f58ee08", "tree": "6fba961e72767d7a0c58b914acc24723190802a3", "parents": [ "a62262f047c9c48c65021f4e23be7b709e8c2811" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Nov 04 13:44:39 2024 +0000" }, "committer": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Wed Nov 06 21:46:35 2024 +0100" }, "message": "feat(ls64): add LS64_ACCDATA test\n\nFEAT_LS64_ACCDATA introduces the system register ACCDATA_EL1, its value\nreplacing the first four bytes of the data provided to an ST64BV0\ninstruction. As this system register would need context switching\nbetween non-secure and secure worlds, there is an SCR_EL3 bit to allow\ntrapping accesses from lower ELs into EL3.\n\nIntroduce a check to verify that accesses to this system register do not\ntrap into EL3, if the CPUID registers advertise this feature.\nBits[63:32] of ACCDATA_EL1 are described as RES0, so mask those bits\nwhen comparing the read-back values with the written one.\n\nChange-Id: Ia32bcf7187356c701470a1757708b3d554e88629\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "a62262f047c9c48c65021f4e23be7b709e8c2811", "tree": "c9e1bef94457fea688cd23beb3cb694a3f3cb531", "parents": [ "97ee573bf9b34d8d8352b6a8af2f2c47c0f41bf9", "f2f1e27c93581b6a9770b8b70780bcd80b961b24" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Nov 06 21:36:42 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 06 21:36:42 2024 +0100" }, "message": "Merge \"feat(tcr2): add asymmetric feature testing for FEAT_TCR2\"" }, { "commit": "97ee573bf9b34d8d8352b6a8af2f2c47c0f41bf9", "tree": "a6b003f7f9c39f43d3441cb2fbf20870daa80f7d", "parents": [ "a948c86a529c14b98214915d291ed997096836e8", "357177b52669038f8748789de0f2c4ba39e8d09a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Nov 06 11:32:24 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 06 11:32:24 2024 +0100" }, "message": "Merge \"fix(realm): fix host_realm_init_ipa_state()\u0027s retry path\"" }, { "commit": "357177b52669038f8748789de0f2c4ba39e8d09a", "tree": "9f76b4e859037498025b749b4960a0b6ddd303b7", "parents": [ "205400d4e105efde03c993cee10defdaf3190504" ], "author": { "name": "pedro martelletto", "email": "martelletto@google.com", "time": "Mon Nov 04 10:41:31 2024 +0000" }, "committer": { "name": "pedro martelletto", "email": "martelletto@google.com", "time": "Wed Nov 06 06:55:38 2024 +0000" }, "message": "fix(realm): fix host_realm_init_ipa_state()\u0027s retry path\n\nmake sure to initialise the IPA state after creating RTTs and before\nreturning success.\n\nChange-Id: I47da3b0cd343c86567c1c38ebd08a50e1129c455\nSigned-off-by: pedro martelletto \u003cmartelletto@google.com\u003e\n" }, { "commit": "a948c86a529c14b98214915d291ed997096836e8", "tree": "6f643f4af1de221d2738a3b0d3092c909aa52105", "parents": [ "205400d4e105efde03c993cee10defdaf3190504", "bd2fd4e8d3923d46e3e8ee68f591eaaff2ed07e3" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Nov 05 16:08:21 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 05 16:08:21 2024 +0100" }, "message": "Merge changes from topic \"ja/rxtx_protect\"\n\n* changes:\n test(memory share): SPMC handles GPF in FFA_MEM_FRAG_RX\n refactor: hypervisor retrieve request helpers\n test(SPM): GPF during FFA_MEM_FRAG_TX\n" }, { "commit": "bd2fd4e8d3923d46e3e8ee68f591eaaff2ed07e3", "tree": "6f643f4af1de221d2738a3b0d3092c909aa52105", "parents": [ "80354938c1384a9238b9056ad9f3468defc5d49b" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Oct 15 11:31:54 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 05 10:17:39 2024 +0000" }, "message": "test(memory share): SPMC handles GPF in FFA_MEM_FRAG_RX\n\nAttest SPMC can handle a GPF when handling a FFA_MEM_FRAG_RX.\nThe FFA_MEM_FRAG_RX accesses to a NWd RX buffer, during the\na multi-fragment retrieve request.\nThe SPMC should handle the GPF, and smoothly return\nFFA_ERROR_ABORTED to the NWd.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Id2116755beddb9350f84155ea4a358de679ac780\n" }, { "commit": "80354938c1384a9238b9056ad9f3468defc5d49b", "tree": "9bd76349090a2c961e34647714278a3cd8249a5e", "parents": [ "c362de3e39acb112b466212713476e367ba509d2" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Oct 15 11:24:27 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 05 10:17:39 2024 +0000" }, "message": "refactor: hypervisor retrieve request helpers\n\nFactored out of hypervisor_retrieve_request the looping\npart, for retrieving the fragments of a fragmented\nretrieve request. This is to aid testing hypervisor retrieve\nrequest, when it faults in the middle of the operation.\n\nAlso added two helpers to access the size of a fragment\nand the total size for both ABIs:\n- FFA_MEM_RETRIEVE_RESP.\n- FFA_MEM_FRAG_TX.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I49d12d69eff8c132b0a29954772dd6634f590f88\n" }, { "commit": "c362de3e39acb112b466212713476e367ba509d2", "tree": "a5dc47ab586d6eb0a5ec3535b262a003eb9b6dae", "parents": [ "205400d4e105efde03c993cee10defdaf3190504" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jun 20 12:50:14 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 05 10:17:23 2024 +0000" }, "message": "test(SPM): GPF during FFA_MEM_FRAG_TX\n\nTest that the SPMC recovers from a GPF when handling\nFFA_MEM_FRAG_TX interface.\n\nChange-Id: I5b98419b32cdfd26431b461aede96e88d238b78b\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "205400d4e105efde03c993cee10defdaf3190504", "tree": "88d8cddd6a8f5aee6924bb857e624319d0373b85", "parents": [ "a0c8d3f504eab3ea929ef669bc746ae5a8daa2ef", "dadd2e26e3edb16903c0e5679a4388f2202537a8" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Oct 31 18:31:44 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 31 18:31:44 2024 +0100" }, "message": "Merge \"Revert \"fvp: skip cpu cluster power-on check\"\"" }, { "commit": "a0c8d3f504eab3ea929ef669bc746ae5a8daa2ef", "tree": "1dabc799480b69a2ba571f9b3505da95c3d2001f", "parents": [ "fd43af6083438eca1540ff58468f0173da1350ff", "f855e9fa002d8bfe25d72e726f16098190076e53" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Oct 30 15:28:30 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 30 15:28:30 2024 +0100" }, "message": "Merge changes from topic \"ja/fix_setup_and_discovery\"\n\n* changes:\n fix(ff-a): report FFA_YIELD support for SPs only\n fix(ff-a): reporting support of indirect messaging\n" }, { "commit": "f855e9fa002d8bfe25d72e726f16098190076e53", "tree": "1dabc799480b69a2ba571f9b3505da95c3d2001f", "parents": [ "d551d093073f0c5ca808eaed6076f2f62bd336fa" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:11:47 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:33:19 2024 +0000" }, "message": "fix(ff-a): report FFA_YIELD support for SPs only\n\nThe FFA_YIELD interface is only valid at the virtual\nFF-A instace, and not at the physical FF-A instance.\nI.e. SPs can use the ABI with SMC conduit into the SPMC.\nThe NWd is not expected to call FFA_YIELD into SPMC.\n\nThis patch drops FFA_YIELD from the common test target\nfor FFA_FEATURES between tftf and cactus/ivy partitions,\nadds the specific tests to both of them with expected\ndifferences.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I7d9a5729b82f3f2f77631a8ab6210fa026078d7d\n" }, { "commit": "d551d093073f0c5ca808eaed6076f2f62bd336fa", "tree": "dc4ea52bfc57413f3640bb5e410a8cc1f121e933", "parents": [ "fd43af6083438eca1540ff58468f0173da1350ff" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:09:47 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:09:47 2024 +0000" }, "message": "fix(ff-a): reporting support of indirect messaging\n\nHafnium was not reporting the support of indirect messaging\nor direct messaging 2, added in FF-A v1.1 and FF-A v1.2,\nrespectively, in the returned information of the ABI\nFFA_PARTITION_INFO_GET. The patch [1] fixes this issue.\n\nThis patch makes equivalent change to the arguments expected\nfor the FFA_PARTITION_INFO_GET return on cactus partitions.\n\n[1] https://review.trustedfirmware.org/c/hafnium/hafnium/+/31712\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I29ef51a7566a09b6fbeada55725d571f0440fbcd\n" }, { "commit": "fd43af6083438eca1540ff58468f0173da1350ff", "tree": "d49a4388a0f99d2b0ea4b2e55c2aa11f9e623e20", "parents": [ "37a5034e1c96dffd897e7231d406fccb3131aa8d", "951376bb0e8af291cc412be9460e4195692fbd87" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Oct 29 12:10:22 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 29 12:10:22 2024 +0100" }, "message": "Merge changes from topic \"xlnx_plat_versal2\"\n\n* changes:\n docs(versal2): add AMD Versal Gen 2 documentation\n feat(versal2): add support for AMD Versal Gen 2 platform\n" }, { "commit": "951376bb0e8af291cc412be9460e4195692fbd87", "tree": "9e51688ea7dcb3db081c69715949dd1c1708119d", "parents": [ "7dbb6c110477adaca32d3afce88135ec76dac6e7" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Oct 04 03:43:07 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Oct 25 09:31:47 2024 +0530" }, "message": "docs(versal2): add AMD Versal Gen 2 documentation\n\nAdd information about AMD Versal Gen 2 platform for TF-A Tests and\nthe build commands.\n\nChange-Id: If1ab592064a6ba39c87e62c32e6e74cd6026caec\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "f2f1e27c93581b6a9770b8b70780bcd80b961b24", "tree": "e3f021e5f5f1af491df4544fc00fc1e433d9e6f8", "parents": [ "37a5034e1c96dffd897e7231d406fccb3131aa8d" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Sep 03 11:49:51 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Oct 24 11:19:43 2024 +0100" }, "message": "feat(tcr2): add asymmetric feature testing for FEAT_TCR2\n\nChange-Id: I07b27ff58ccf471ccc43643141e2dfe70083fd13\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "11221142eac86235c7efdec6eb8ba195c14af8e8", "tree": "39fae39e4f94b95396ebb2d5f6ab30f94c5ee9a9", "parents": [ "ada6a86bd3eb9c9629c2f06e3480473e28ccdc3b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 21 10:11:29 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Oct 24 09:23:48 2024 +0100" }, "message": "fix(build): add a dependency to the build directory\n\nThe build directory is never explicitly depended on. Other recipes are\npretty much guaranteed to finish before the sp_layout target requires\nit. However, on extremely slow hard drives (1MB/s) that doesn\u0027t happen.\nAdd an explicit dependency so make waits correctly.\n\nChange-Id: Ibafc696c27c1a1ed14d181ef330871f6539c45f7\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "37a5034e1c96dffd897e7231d406fccb3131aa8d", "tree": "ba51882deb7e44d3b0832904d0ef0ca61b8c871b", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a", "9601dc5343d4aee267a5adcebeb2495f395acc4d" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Oct 23 22:49:08 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 23 22:49:08 2024 +0200" }, "message": "Merge changes from topic \"refact_asymmetric_tests\"\n\n* changes:\n feat: skip asymmetric tests when features not present\n refactor: clarify which kind of exceptions it catches\n refactor: only register undef_injection_handler during register accesses\n" }, { "commit": "9601dc5343d4aee267a5adcebeb2495f395acc4d", "tree": "ba51882deb7e44d3b0832904d0ef0ca61b8c871b", "parents": [ "70de3ff58e06f66819e98a25a9167c6751f87330" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Wed Aug 28 17:27:18 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "feat: skip asymmetric tests when features not present\n\nThis patch skips asymmetric tests, when features are not present\nand will split them into separate tests.\n\nThe problem with the previous test structure was that you can\u0027t\ndistinguish between a trap to EL2 and an undef injection. This meant\nthat on some platforms, the tests would pass even without the\nasymmetric support patches. In these cases, it would be better if the\ntest was skipped, since there\u0027s no situation where it fails.\n\nFor example, if FEAT_SPE wasn\u0027t present on any cores, and the\nasymmetric support patches weren\u0027t applied, then the test would pass.\nThis is because the register accesses would trap to EL2.\n\nThis patch skips the test on every core that doesn\u0027t have the feature\nimplemented. It also splits the test into separate test functions.\nThis allows us to display a separate test result for each asymmetric\ntest. It also allows us to skip the whole test if the feature isn\u0027t\npresent on any cores, since in these cases the test would always pass.\n\nThe structure of the test is similar to\ntftf/tests/runtime_services/standard_service/psci/api_tests/cpu_suspend/test_suspend.c.\nThe run_asymmetric_test function takes a function as an argument, and\nruns it on all CPUs.\n\nThe whole test should only be skipped if the test was skipped on all\nCPUs. The test on each CPU can\u0027t return TEST_RESULT_SKIPPED, because\nthe whole test is skipped if any of the CPUs return\nTEST_RESULT_SKIPPED. Instead, to skip a test, the test returns\nTEST_RESULT_SUCCESS, then sets a flag in the test_skipped array. This\narray is checked at the end by the run_asymmetric_test function.\n\nChange-Id: I802431714de3eb8b059e8fc56f7e19fc94e3e8fb\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "70de3ff58e06f66819e98a25a9167c6751f87330", "tree": "2823ae213e5f1a81ffbc15db0e3a8c1f508ad941", "parents": [ "4397e4444950fcb138122d5fa047fc2250fcc375" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Tue Aug 20 11:27:25 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "refactor: clarify which kind of exceptions it catches\n\nThe function that was called \"undef_injection_handler\" doesn\u0027t just\ncatch undef injections. It also catches traps to EL2 due to registers\nnot being present. Both cases have the same EC value, so it is\nimpossible to distinguish between them.\n\nThis patch edits variable names and adds a comment to clarify this.\n\nChange-Id: Ie7405d7611afc1d2ff2207cfa4a08de3cbc9dff7\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "4397e4444950fcb138122d5fa047fc2250fcc375", "tree": "b8e9c43197838f4128523feda90644836e5085e5", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Tue Aug 20 10:17:38 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "refactor: only register undef_injection_handler during register accesses\n\nBefore, the undef_injection_handler was registered at the start of the\ntest, and unregistered at the end. This patch makes it so the\nundef_injection_handler is only registered where a register is being\naccessed. This gives us more control in which exceptions we catch.\n\nChange-Id: I4262288543cac6b1f9ab0e6fd5092d7e3a31fb75\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "7dbb6c110477adaca32d3afce88135ec76dac6e7", "tree": "26bd19cda1226669eb5c8abe0e5b4995fcb606be", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Oct 04 03:22:30 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Oct 22 04:39:42 2024 +0000" }, "message": "feat(versal2): add support for AMD Versal Gen 2 platform\n\nIntroduce platform support for AMD Versal Gen 2.\n\nSummary:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 194\nTests Passed : 29\nTests Failed : 0\nTests Crashed : 0\nTotal tests : 223\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nNOTICE: Exiting tests.\n\nChange-Id: I608dd556be402f97f9960c688b7d0caa6f17c5c3\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nSigned-off-by: Michal Simek \u003cmichal.simek@amd.com\u003e\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "ada6a86bd3eb9c9629c2f06e3480473e28ccdc3b", "tree": "72f3e2f5c70621d912e860b711ab7aeee5af69d6", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 21 10:06:50 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 21 10:06:50 2024 +0100" }, "message": "fix(build): use a grouped target for the tests_list files\n\nBy default, when specifying multiple independent targets in a rule, make\nwill make an equivalent target for each. However, that is not correct\nwhen the recipe makes both targets with the same invocation. In that\ncase they should be specified as a grouped target so that make knows\nthat both files will be produced at the same time. This is the case for\nthe generate_test_list.py script.\n\nThis is an attempt to fix a race condition when building with many\ncores. Note that the race itself was not reproduced.\n\nChange-Id: I2d976951e39b83dd689a1dda63750679e35f8136\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "dadd2e26e3edb16903c0e5679a4388f2202537a8", "tree": "6f931efd4b82f48ffedde56e79997aa466a96ea9", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Oct 16 22:25:58 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Oct 17 16:29:19 2024 +0200" }, "message": "Revert \"fvp: skip cpu cluster power-on check\"\n\nThis reverts commit 11f6ee85b015635021083db0f494a2c2957566ef.\nThis now addressed through a TF-A patch -\nhttps://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/31902\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: Icea0cefb93723343586e5b3a57a2c9b90a9bf5c6\n" }, { "commit": "32c1669e0143b9aad3bad5af2e1069cb08047d2a", "tree": "413ed93b2228e3447f579e99946176e871b629d2", "parents": [ "492aac16a530d8f3739f4f03e3bbd6d396b43ac9", "0db147aecaec8d10aff6103d038dc149710b25f7" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 10 12:42:36 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 10 12:42:36 2024 +0200" }, "message": "Merge changes I5961f953,I9ab3d94f\n\n* changes:\n feat(realm_payload): use random start REC\n feat(realm_payload): increase maximum number of RECs\n" }, { "commit": "492aac16a530d8f3739f4f03e3bbd6d396b43ac9", "tree": "5d36349afe656f9ddc2bb566873ea5c7b1e59566", "parents": [ "2fe9ef36da3f6d0b2a02423f7892739129c6a3b2", "b2fcf90c9aa5ada4bc373ad9e0dfbec7142f205b" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Oct 07 11:58:46 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 07 11:58:46 2024 +0200" }, "message": "Merge \"docs: update toolchain requirements\"" }, { "commit": "b2fcf90c9aa5ada4bc373ad9e0dfbec7142f205b", "tree": "89672ba7c40a35f659c496272837207783818074", "parents": [ "3a137fc469a3241cfda137975dd8c9805331023b" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Sep 30 18:15:55 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Oct 07 10:51:24 2024 +0100" }, "message": "docs: update toolchain requirements\n\nTF-A tests have been verified with the latest toolchain version\n13.3.Rel1. Henceforth the requirements are updated.\n\nChange-Id: I03cb4fd99ecbba412e1b9018de6e6c330374866d\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "0db147aecaec8d10aff6103d038dc149710b25f7", "tree": "b21bf750fe12bc45bc707d1665459a088db4e8ef", "parents": [ "93d4df58e20da38742613eb1fe2fe401289aeaf2" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 16:46:35 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 17:06:06 2024 +0100" }, "message": "feat(realm_payload): use random start REC\n\nThis patch modifies tests below\nhost_test_realm_create_enter\nhost_test_multiple_realm_create_enter\nhost_realm_multi_rec_single_cpu\nto start Realm execution with a random REC number.\n\nChange-Id: I5961f953efc4dab25d301a7026d0c3949701df4a\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "93d4df58e20da38742613eb1fe2fe401289aeaf2", "tree": "2de78b803f816449d34ce2ec0f869be3dcbd7ffb", "parents": [ "2fe9ef36da3f6d0b2a02423f7892739129c6a3b2" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 09:44:52 2024 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 17:57:08 2024 +0200" }, "message": "feat(realm_payload): increase maximum number of RECs\n\nThis patch changes maximum number of RECs per realm\nMAX_REC_COUNT from 8 to 17. This makes possible to\ntest calculation of REC\u0027s linear index from RmiRecMpidr\ntype which has [7:4] SBZ.\n\nChange-Id: I9ab3d94f25b263b2672012ccbd6e632265a2a745\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "2fe9ef36da3f6d0b2a02423f7892739129c6a3b2", "tree": "1e35ba50c44808b5b946e98fd32aa02c4723b7b3", "parents": [ "3a137fc469a3241cfda137975dd8c9805331023b", "5467cb50ac44eb4d3248c0cf70eaf1fd6a034c8b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 10:42:59 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 03 10:42:59 2024 +0200" }, "message": "Merge changes Id032d455,Ib5420db9,I28f69967,Ic1f25b0e\n\n* changes:\n fix(realm): cater for removal of SH from rtte\n feat(realm): set number of num_bps and num_wps\n feat(realm): update rsi_ipa_state_get() function\n feat(include/runtime_services): update RMI and RSI definitions\n" }, { "commit": "5467cb50ac44eb4d3248c0cf70eaf1fd6a034c8b", "tree": "1e35ba50c44808b5b946e98fd32aa02c4723b7b3", "parents": [ "19cfac8b0cbbc1dfffc58f28a4cacb925eb4c8c9" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Oct 02 18:21:43 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 07:14:34 2024 +0200" }, "message": "fix(realm): cater for removal of SH from rtte\n\nThe RMM v1.0 REL specification removes the SH field from host_controlled\nparameters. Fix up TFTF for this change.\n\nChange-Id: Id032d4555da4b200bb9a355085b8a7f0709884fb\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "19cfac8b0cbbc1dfffc58f28a4cacb925eb4c8c9", "tree": "0ac8d741cacb43841f8d2a4263bb9b03ed1624c3", "parents": [ "9a60ecbf209d2faf117420b9013c52216106d157" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Aug 30 16:36:42 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 01 16:55:17 2024 +0100" }, "message": "feat(realm): set number of num_bps and num_wps\n\nAs per RMM Specification number of breakpoints and\nwatchpoints passed to RMI_REALM_CREATE cannot be 0.\nThese values are passed to host_prepare_realm_payload()\nin feature_flag parameter fields which are set to 0\nby default by callers to this function.\nThis patch modifies the logic for setting num_bps\nand num_wps Realm parameters to avoid 0 values.\n\nChange-Id: Ib5420db959866620005c404c494c4ec1904b010c\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "9a60ecbf209d2faf117420b9013c52216106d157", "tree": "21df19a240173b2d14a9633c146f66665fa1e95d", "parents": [ "dff904b244bc97672dd2408fa2d38f15b3ca7ced" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Aug 06 16:39:00 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 01 16:55:17 2024 +0100" }, "message": "feat(realm): update rsi_ipa_state_get() function\n\nThis patch updates rsi_ipa_state_get() function and its\nrelated test calls as per RMM Specification 1.0-rel0-rc1.\nIt also updates RSI commands API related comments and\nmakes minor changes in test functions to improve code\nreadability.\n\nChange-Id: I28f69967ab6ff5b38c2b9efd423b0e8b4ad61dae\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "dff904b244bc97672dd2408fa2d38f15b3ca7ced", "tree": "55029d438a9f7cfd221d49bab7120480650c8b9b", "parents": [ "3a137fc469a3241cfda137975dd8c9805331023b" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Aug 05 17:11:18 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 01 16:55:17 2024 +0100" }, "message": "feat(include/runtime_services): update RMI and RSI definitions\n\nThis patch:\n- updates fields definitions of RmiFeatureRegister0 type,\n- adds \u0027RSI_IO\u0027 definition to \u0027rsi_ripas_type\u0027 enumeration,\n- adds \u0027algorithm\u0027 and \u0027rpv\u0027 members to \u0027rsi_realm_config\u0027\nstructure\naccording to the RMM Specification 1.0-rel0-rc1.\n\nChange-Id: Ic1f25b0e3ddbc93a4fceb88f9db4d808b54cc628\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "3a137fc469a3241cfda137975dd8c9805331023b", "tree": "9dc78c63eb41d008e8c161917482ac3794c7205d", "parents": [ "0ac547da8dd6c2be4313f945a7731548b7c238c2", "eb37879238d7a63b395e6795d2d4dc6cfea265e2" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Sep 18 10:50:20 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 18 10:50:20 2024 +0200" }, "message": "Merge \"test(spm): using SRI delay flag from NWd\"" }, { "commit": "0ac547da8dd6c2be4313f945a7731548b7c238c2", "tree": "f9729d0a5a043a2f7eb54b1f887074223280491e", "parents": [ "f2ed78567ac1df53fc28c3f46dde45dda86a2819", "408a89df20c6345fbeff60364f674bb61bfd2ff8" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Sep 16 14:08:22 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 16 14:08:22 2024 +0200" }, "message": "Merge \"fix(realm): separate pool creation from realm creation helpers\"" }, { "commit": "408a89df20c6345fbeff60364f674bb61bfd2ff8", "tree": "eacbc5e870296a7fa23ef831c2f970a4b016169c", "parents": [ "31a6f6499c5e558a9ef13ff53922f031d18a48b9" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Aug 06 12:33:29 2024 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Sep 16 12:17:11 2024 +0100" }, "message": "fix(realm): separate pool creation from realm creation helpers\n\nInitialize only one pool per testcase.\nSeparate pool creation from realm creation helpers.\nThis fixes the bug where testcase creates 2 realms\nand 2 pools, and first pool is lost and not cleaned up.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I817e97ea5ef15510c18261689c5f5d4e0e65b054\n" }, { "commit": "f2ed78567ac1df53fc28c3f46dde45dda86a2819", "tree": "9ba4b538191a399bdd9e091db3925cdd22d04f6d", "parents": [ "060d31853a5e3a5e6bce744e0934aa22ebfbb8e1", "9f2de630d5d2472e8ec7348507e343738934940d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 13 18:21:28 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 13 18:21:28 2024 +0200" }, "message": "Merge changes I8db1048d,If47077da,Ic2ab11af\n\n* changes:\n feat(doe): add PCIe DOE tests\n feat(pcie): add PCIe support to FVP platform\n feat(pcie): add PCIe DOE library\n" }, { "commit": "9f2de630d5d2472e8ec7348507e343738934940d", "tree": "4905c2ec19086fbdecde033abd1f2f766d98f692", "parents": [ "36ed009a073c64a422c769b46eede6538fa42667" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 11:48:22 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 13 18:20:18 2024 +0200" }, "message": "feat(doe): add PCIe DOE tests\n\nThis patch adds PCIe DOE tests for\n- DOE discovery protocol\n- SPDM get version\nTo build this test suite use \u0027TEST\u003dpcie-doe\u0027\noption.\n\nThe spdm.h is imported from https://github.com/DMTF/libspdm\nproject.\n\nChange-Id: I8db1048d01b4f8061d8a4ddccc198159ed61e6b7\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "060d31853a5e3a5e6bce744e0934aa22ebfbb8e1", "tree": "2964cb4965f24cc753cd0cc193b0d8c20fbbbf15", "parents": [ "31a6f6499c5e558a9ef13ff53922f031d18a48b9", "f09c77af164cb1332a4db3d141ffc5d60625967b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Sep 12 14:18:46 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 12 14:18:46 2024 +0200" }, "message": "Merge changes Ieac47398,I0161f713\n\n* changes:\n fix(realm): fix calculation of Realm\u0027s REC index\n fix(realm): fix realm initialisation code\n" }, { "commit": "f09c77af164cb1332a4db3d141ffc5d60625967b", "tree": "4d5f1085a718618101a75d36e503d0da4aba0b1d", "parents": [ "f30108d8427112a11fbcd3561bdb0bed425f8896" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 15:50:44 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Sep 12 11:59:53 2024 +0100" }, "message": "fix(realm): fix calculation of Realm\u0027s REC index\n\nThis patch fixes the issues related to the calculation of\nRealm\u0027s REC index based on the read value of MPIDR_EL1 register\nand REC\u0027s mpidr parameter from the REC\u0027s index.\nRMM reports MPIDR_EL1.Aff0 field matching RmiRecMpidr type\nwith [7:4] bits RES0, making MPIDR_EL1\u003d0x80000100 represent\nREC 16, but not 256 as it is implemented in the existing code.\nThe patch adds the following macros:\n- RMI_REC_MPIDR(idx) which calculates RmiRecMpidr value based\non REC index.\n- REC_IDX(mpidr) gets REC index from MPIDR_EL1.\n\nChange-Id: Ieac473984f3a50d2815dcfe8d291d31bd70ebae7\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "f30108d8427112a11fbcd3561bdb0bed425f8896", "tree": "bd52b3644cc71a7a21dc41c4007748aad6926697", "parents": [ "f13410b3e4d9a2526333d2621ad5e8aede6c2b86" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Sep 06 17:24:24 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Sep 11 16:14:33 2024 +0100" }, "message": "fix(realm): fix realm initialisation code\n\nThe curent code in \u0027realm_entrypoint\u0027 relies\non primary VCPU to perform initialisation and\nsymbols relocation. This makes impossible to\nrun any REC\u003cn\u003e before REC\u003c0\u003e runs, because\nREC\u003cn\u003e will be detected as a secondary VCPU\nnot required to perform the initialisation\nwhich will cause the crash.\nThis patch fixes this issue by introducing\n\u0027cold_boot_flag\u0027 variable which is updated\nby the first VCPU which runs \u0027realm_entrypoint\u0027\nand performs initialisation.\n\nChange-Id: I0161f7132f64423cff646db74f95753aa9a5d073\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "36ed009a073c64a422c769b46eede6538fa42667", "tree": "e7c152d972ff234597afff7712780b0bdab3fb2c", "parents": [ "9f0dc01f4d4f6f1800e86c4c6f1e8377e119a713" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:37:54 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:37:54 2024 +0100" }, "message": "feat(pcie): add PCIe support to FVP platform\n\nThis patch adds PCIe support to FVP platform.\n\nChange-Id: If47077dac50dd090c0e949213688a6427d29872b\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "9f0dc01f4d4f6f1800e86c4c6f1e8377e119a713", "tree": "119dc2ce7fa5fe4807fc535ea0dfc1275af2fedb", "parents": [ "31a6f6499c5e558a9ef13ff53922f031d18a48b9" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:22:06 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:22:06 2024 +0100" }, "message": "feat(pcie): add PCIe DOE library\n\nThis patch adds PCIe DOE library source files.\n\nChange-Id: Ic2ab11afa0438d74c53cb157a63caada7457d77e\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "31a6f6499c5e558a9ef13ff53922f031d18a48b9", "tree": "996cd85963464f1b12ce11afb960cec7962a54b2", "parents": [ "7e26d6a95e4c28fd28cb472e451f15dd44f79a57", "3d804155c21db7f97f00bfec7eb14ef83f45f7bc" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Sep 06 15:43:50 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 06 15:43:50 2024 +0200" }, "message": "Merge \"fix(corstone1000): skip some TF-A tests\"" }, { "commit": "7e26d6a95e4c28fd28cb472e451f15dd44f79a57", "tree": "b4925984f5e247b520ea69b55127694d29d24514", "parents": [ "f13410b3e4d9a2526333d2621ad5e8aede6c2b86", "6f20400a44e90ccfff25f7aedaa1954cc56cb9f1" ], "author": { "name": "Sandrine Afsa Bailleux", "email": "sandrine.afsa@arm.com", "time": "Fri Sep 06 14:22:43 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 06 14:22:43 2024 +0200" }, "message": "Merge \"Fix: drivers/gic: Relax GICD_ITARGETSR assertion for unicore\"" }, { "commit": "3d804155c21db7f97f00bfec7eb14ef83f45f7bc", "tree": "769aa020c30105ed45c758f177c819f3c31edaa9", "parents": [ "f13410b3e4d9a2526333d2621ad5e8aede6c2b86" ], "author": { "name": "Harsimran Singh Tungal", "email": "harsimransingh.tungal@arm.com", "time": "Wed Sep 04 14:38:03 2024 +0100" }, "committer": { "name": "hartun01-arm", "email": "harsimransingh.tungal@arm.com", "time": "Wed Sep 04 16:52:30 2024 +0200" }, "message": "fix(corstone1000): skip some TF-A tests\n\nSome of the TF-A tests get stuck when run on TF-A master for Corstone-1000.\nSo, skip those tests for now for Corstone-1000. This change is required to integrate Corstone-1000 FVP platform in TF-A Open CI\n\nChange-Id: I3fd06200141e18b9c6c767718aaf52aede136560\nSigned-off-by: Harsimran Singh Tungal \u003charsimransingh.tungal@arm.com\u003e\n" }, { "commit": "f13410b3e4d9a2526333d2621ad5e8aede6c2b86", "tree": "ba921595c125dd787e93dee8d3d57c54f04cd8f7", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5", "435c27e58850dc946b37d4af5271b5fc3ecc2399" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Aug 28 15:40:25 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 28 15:40:25 2024 +0200" }, "message": "Merge \"test(sdei): add test for attempting to bind too many events\"" }, { "commit": "6f20400a44e90ccfff25f7aedaa1954cc56cb9f1", "tree": "5e204d1a1a8c283494bdb77333d608018f630581", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5" ], "author": { "name": "Pranjal Shrivastava", "email": "praan@google.com", "time": "Wed Aug 28 12:29:48 2024 +0000" }, "committer": { "name": "Pranjal Shrivastava", "email": "praan@google.com", "time": "Wed Aug 28 12:50:49 2024 +0000" }, "message": "Fix: drivers/gic: Relax GICD_ITARGETSR assertion for unicore\n\nAs per the GICv2 arch specification, section 4.3.12 in a uniprocessor\nimplementation all interrupts target one processor and the\nGICD_ITARGETSRs are RAZ/WI. The assert on the gicd_itargets_val in the\ngic_v2 driver causes the tftf to halt on uniprocessor systems. Thus,\nskip the assert on uniprocessor systems.\n\nChange-Id: I471836b413a7835487de3a5dd9cf0e3b6d28b523\nSigned-off-by: Pranjal Shrivastava \u003cpraan@google.com\u003e\n" }, { "commit": "435c27e58850dc946b37d4af5271b5fc3ecc2399", "tree": "ba921595c125dd787e93dee8d3d57c54f04cd8f7", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Wed Aug 07 15:32:02 2024 +0100" }, "committer": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Wed Aug 21 11:39:41 2024 +0100" }, "message": "test(sdei): add test for attempting to bind too many events\n\nThe test makes sure that if you attempt to bind more events than are\navailable, it will return an error code instead of crashing.\n\nChange-Id: Ib74589a04ed7cbd0d1a9de355a9bf3c99f945ae5\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\n" }, { "commit": "f44fdf4fc4867afa946b0c2bb644b744a50981f5", "tree": "42471b88543cc40597fb0fffdd306dbb362fac34", "parents": [ "47415f560939c3ddc5272816fdbe4b9a7f61d1ce", "3ca234295ae5802cd684ba56cdec018bde26d2d2" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Aug 20 22:30:25 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 20 22:30:25 2024 +0200" }, "message": "Merge changes from topic \"mp/simd_ctxt_mgmt\"\n\n* changes:\n feat: introduce a new test suite supported by EL3 SPMC\n feat: support Cactus SP to boot on EL3 SPMC\n fix(cactus): skip computing linear core id\n" }, { "commit": "3ca234295ae5802cd684ba56cdec018bde26d2d2", "tree": "42471b88543cc40597fb0fffdd306dbb362fac34", "parents": [ "6f7344b97ab42d045b7a2f502bf9c80100ae8a44" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jul 05 16:26:12 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 19 11:25:51 2024 -0500" }, "message": "feat: introduce a new test suite supported by EL3 SPMC\n\nA new test suite is being created which is supported by Cactus SP. It\naims to exercise the SIMD context management support in EL3 SPMC.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I2a65da8c098b40858a2af0f9012cc225a24e6fcb\n" }, { "commit": "6f7344b97ab42d045b7a2f502bf9c80100ae8a44", "tree": "55dfa7d260bee6752f67d5098de73de612883add", "parents": [ "3b4e989a8c0dfbb3c44dfe3819feca89b6cee5a2" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jul 05 16:21:26 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 19 11:25:51 2024 -0500" }, "message": "feat: support Cactus SP to boot on EL3 SPMC\n\nEL3 SPMC has a limited set of FF-A functionality and does not support\nall the features built into the current Cactus SP implementation.\n\nHence, this patch introduces a build option to strip out few features\nfrom Cactus SP in order to boot it on EL3 SPMC.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I6319563adca67460015b79219ebc5c9468e3d54a\n" }, { "commit": "3b4e989a8c0dfbb3c44dfe3819feca89b6cee5a2", "tree": "951e6f25058090c88c1de8854a23dbf3e9266bec", "parents": [ "47415f560939c3ddc5272816fdbe4b9a7f61d1ce" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jul 05 16:18:34 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 19 11:25:51 2024 -0500" }, "message": "fix(cactus): skip computing linear core id\n\nOn a S-EL2 based SPMC, computing of linear core id is trivial as it\ncan be simply extracted from a read of MPIDR, which is virtualized\nthrough VMPIDR_EL2 register to return vcpu index, followed by a mask operation.\n\nHowever, on a non-SEL2 based SPMC, read of MPIDR by S-EL1 SP returns\nphysical MPIDR. Computing linear core id at this stage in early boot\nis complicated given the operations needed to interpret the various\nlevels of affinity which is platform dependent. Hence, rather than\ntrying to compute linear id from MPIDR, reuse the physical core id\npopulated by SPMC in x4 register.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I21f2fbbd71e8a67c851cb28f92ab5b8d39e0f644\n" }, { "commit": "47415f560939c3ddc5272816fdbe4b9a7f61d1ce", "tree": "f2103abf26962ecd3cbf2e55f450a1771772d333", "parents": [ "8e88c675ce720c443dbb593adc0bf10bfa8840ed", "ccd82702aeb079cc5c20ef4227726c576a731fa9" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Aug 19 16:32:09 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 19 16:32:09 2024 +0200" }, "message": "Merge changes from topic \"tftf_refactor\"\n\n* changes:\n refactor(neoverse_rd): introduce flash and ros macros\n refactor(neoverse_rd): introduce timer and watchdog macros\n refactor(neoverse_rd): define naming convention for CSS macros\n refactor(neoverse_rd): remove deprecated header files\n refactor(neoverse_rd): refactor header files for second gen platforms\n refactor(neoverse_rd): refactor header files for first gen platforms\n" }, { "commit": "ccd82702aeb079cc5c20ef4227726c576a731fa9", "tree": "150279b593dbce693f96454daeae1090720f75b5", "parents": [ "4ccb1ef774f03e2d1cc74fdb93aa53088c1073c6" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Jul 31 16:27:23 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:35 2024 +0200" }, "message": "refactor(neoverse_rd): introduce flash and ros macros\n\nAs part of the refactoring for TFTF on the first and second\ngeneration of platforms, introduce flash related memory layout\nmacros to be added in nrd_ros_def1.h and nrd_ros_def2.h files.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I01929bbd465d777e827c3eb547bb973339bd4308\n" }, { "commit": "4ccb1ef774f03e2d1cc74fdb93aa53088c1073c6", "tree": "32e6cd47416c4032b5a49e200d597c61eb732384", "parents": [ "2d20ac071513593961e7ddd9033eae70b36aaf83" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Jul 31 13:28:08 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:31 2024 +0200" }, "message": "refactor(neoverse_rd): introduce timer and watchdog macros\n\nAs part of the refactoring for TFTF on the first and second\ngeneration of platforms, introduce timer and watchdog related\nmemory layout macros to the nrd_css_def1.h and nrd_css_def2.h\nfiles.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: Iabe4c310ed4297d71cf53869a68d45c5c589fce2\n" }, { "commit": "2d20ac071513593961e7ddd9033eae70b36aaf83", "tree": "90c6981aa04a1f1856d646ab7be335bb595fc69f", "parents": [ "3a426d6d89621fdc7e913e11dc2614742b86a584" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Jul 29 15:35:07 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:24 2024 +0200" }, "message": "refactor(neoverse_rd): define naming convention for CSS macros\n\nAs part of the refactoring for TFTF on the first and second generation\nof platforms, introduce a naming convention for macros within\nnrd_css_def*.h and nrd_css_fw_def*.h. All CSS related macros must adhere\nto the format NRD_CSS_\u003cname\u003e.\n\nChange-Id: I756c46688dd66dfc6b1d89159ebcd39d68c8f91c\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "3a426d6d89621fdc7e913e11dc2614742b86a584", "tree": "69e36c1da8305418047bd698ae17cbcdf75a07cd", "parents": [ "b79a256cfe2419ccc8c48a78a89e7b7735330fe0" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Jul 29 13:11:53 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:14 2024 +0200" }, "message": "refactor(neoverse_rd): remove deprecated header files\n\nTF-A underwent a major rehaul in directory structure. This change\ndeals with removal of the previous common include files that are\nnow deprecated.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I0c77ee262b26f7bd5d8660b481f19aab8d721246\n" }, { "commit": "b79a256cfe2419ccc8c48a78a89e7b7735330fe0", "tree": "27fb1c3e3ac16344f8cf96eb269a50967e475a74", "parents": [ "61b321e9f8f3a3cd8398b65e5f733abc5577d1a4" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Jul 29 13:07:55 2024 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 15:13:10 2024 +0100" }, "message": "refactor(neoverse_rd): refactor header files for second gen platforms\n\nTF-A underwent a major rehaul in directory structure. This change\ndeals with refactoring the header files for second generation platforms\ngrouped as nrd2 in TFTF to a structure that aligns with that of TF-A.\n\nChange-Id: I263a91e768644b491a0dc2b706e7c88d6b65e8a9\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "8e88c675ce720c443dbb593adc0bf10bfa8840ed", "tree": "0ee43633643d2dc742b5bb60e5993a980417afe2", "parents": [ "33d3d3365e2bfe6d912379266c90ff9d33b1418a", "e4f2eaa6f626646cfa3e439086966ac114540cbc" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Aug 19 11:56:08 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 19 11:56:08 2024 +0200" }, "message": "Merge changes from topic \"ar/asymmetricSupport\"\n\n* changes:\n feat: introduce asymmetric feature testing for feat_spe\n feat: skip TRBE extension test if ERRATA applies\n feat: test if errata 2938996 and 2726228 workaround is applied\n feat: skeleton for asymmetric feature testing capability\n" }, { "commit": "33d3d3365e2bfe6d912379266c90ff9d33b1418a", "tree": "8ae11cb64740d350a5a5b459ae8b9e072226e6dc", "parents": [ "cea63b2bbd871a6664b54af325f6a739e8746ff7", "66ee63286f790f61c56dfb8765b5668ccd8991aa" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 16 20:11:45 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 16 20:11:45 2024 +0200" }, "message": "Merge \"fix: cactus_mm is too verbose on some tests\"" }, { "commit": "e4f2eaa6f626646cfa3e439086966ac114540cbc", "tree": "ebb5c60c417e4393c160b78f1c31b780a3c48d2f", "parents": [ "eeac9d97edaf45041b7325f9aade1ad7bfeb6828" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Mon Aug 12 17:59:54 2024 +0100" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 12:07:48 2024 -0500" }, "message": "feat: introduce asymmetric feature testing for feat_spe\n\nChange-Id: Ide9bda1b5f1cabc63241f42b93a672d8e04b8119\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "eeac9d97edaf45041b7325f9aade1ad7bfeb6828", "tree": "3cd50819f0a22bcc8ad0d8d8271f9a29dc3ccf2b", "parents": [ "8191621885dfc65789a19ef0eb590b8639ed87d1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Aug 16 12:34:58 2024 +0100" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 09:08:00 2024 -0500" }, "message": "feat: skip TRBE extension test if ERRATA applies\n\nFor Cortex-A520(2938996) and Cortex-X4(2726228) erratums TRBE feature is\ndisabled by EL3.\n\nCheck and skip TRBE test if the core is affected.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Iaa394ae79dec38d0b369012e149abbc65b0cf0f8\n" }, { "commit": "8191621885dfc65789a19ef0eb590b8639ed87d1", "tree": "8fbbf09517a4e7de5976e8912a594be10cfb1f04", "parents": [ "0145ec3459750f35a6546b3f015906356b7dc6cd" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Aug 15 15:08:23 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 09:07:55 2024 -0500" }, "message": "feat: test if errata 2938996 and 2726228 workaround is applied\n\nThis patch confirms if access to trbe el1 register generates an undef\ninjection in affected cores. If a core is affected by errata 2938996/\n2726228 and it generates an undef injection on access to trbe el1 register then\nthe test passes. If it is an unaffected core then the test passes , but\nwhen undef injection doesn\u0027t happen in affected core, the test fails.\n\nChange-Id: I515a9aa4613c6d99ee73e579206089ebf89ffae8\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "0145ec3459750f35a6546b3f015906356b7dc6cd", "tree": "4cb24cf11b7177ae3af728007d27a328f5c636df", "parents": [ "cea63b2bbd871a6664b54af325f6a739e8746ff7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Aug 12 17:59:54 2024 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Aug 16 11:39:26 2024 +0100" }, "message": "feat: skeleton for asymmetric feature testing capability\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I6da831043c9485de00ba29a22ebaea6e9cdb5f57\n" }, { "commit": "cea63b2bbd871a6664b54af325f6a739e8746ff7", "tree": "32fa54ead3a7fb903e1cdb9a2772074a91a96a86", "parents": [ "e4690a01f06e3b67a5afef3644adc1e4db2f5bdb", "7a3c1dc2dc559814882ebf47265e57c31bf05afc" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Aug 15 21:02:33 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 15 21:02:33 2024 +0200" }, "message": "Merge \"refactor(memory share): use UART macro in device mem share\"" } ], "next": "e4690a01f06e3b67a5afef3644adc1e4db2f5bdb" }