)]}' { "log": [ { "commit": "f68ebdb9b45cc7a58f816f153f5e626c898dc0cf", "tree": "8eb48a5843eb4acfa86c3066173aaa2b0f898d4b", "parents": [ "0012dbc2a841abeff25be8be1113f19073ee4d2c" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Wed Sep 18 16:13:00 2019 +0100" }, "committer": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Fri Oct 04 09:35:00 2019 +0100" }, "message": "Try to leak counter values from secure world.\n\nThis patch introduces a series of tests that try to leak PMU counter values\nfrom EL3 and S_EL1.\n\nPMU events used:\n\t- CPU cycles via PMU counter PMCCNTR_EL0\n\t- Retired writes to PC via PMU counter PMEVCNTR0_EL0\n\nThis AARCH64-specific patch is for security fix:\nhttps://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1789\n\nThe AARCH32 versions of these tests will be in a future patch.\n\nSigned-off-by: Petre-Ionut Tudor \u003cpetre-ionut.tudor@arm.com\u003e\nChange-Id: Ib27948edadde30272e59a9ab208543703fa078bd\n" }, { "commit": "0012dbc2a841abeff25be8be1113f19073ee4d2c", "tree": "7ea4030213ff226769f46328b29717651d8b81ea", "parents": [ "f19b16dba6d867b71cd68bbc1b2f086b14be978c", "2129608e9ab970909c924a934a93a501099ab3bc" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Sep 30 06:47:17 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 30 06:47:17 2019 +0000" }, "message": "Merge \"Separate shutdown and stats after shutdown tests\"" }, { "commit": "f19b16dba6d867b71cd68bbc1b2f086b14be978c", "tree": "6f8b8038f5ed040e7274b462df191cc77e89ce90", "parents": [ "cdba6c95f558304f77b062d58c6c398b3655ef93", "1c97f9418db19942656072435955874c83027124" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Sep 27 15:46:41 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 15:46:41 2019 +0000" }, "message": "Merge \"Allowing zeroes in trusted OS SMC return values\"" }, { "commit": "1c97f9418db19942656072435955874c83027124", "tree": "4289d6f078487d87f03dfd62f834f5df51cb508c", "parents": [ "2676b99a81b4f886b7b79189cbe432705843977b" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Mon Sep 23 16:44:03 2019 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Thu Sep 26 22:51:20 2019 +0200" }, "message": "Allowing zeroes in trusted OS SMC return values\n\nTrusted OSes should preserve or fill by zeroes the values of x1-x3\nregisters across an SMC call in order to prevent data leakage. The\nbehaviour of OP-TEE regarding to this has changed recently from\npreserving values to filling them by zeroes. This patch utilitizes the\nnewly added allow_zeros[] parameter of the smc_check_match function to\nmake the tests compatible with OP-TEE commit 6e558fa94ab0 or later.\n\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\nChange-Id: I52ddfb69261833a3fba76c5f89d27d1ea13043b0\n" }, { "commit": "cdba6c95f558304f77b062d58c6c398b3655ef93", "tree": "8e34cf61f431a255cf7f3004d9e3cce4c6e74530", "parents": [ "2676b99a81b4f886b7b79189cbe432705843977b", "1b92611fddb4b3360ca1d6db3b91a2c3b7bf99bb" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Sep 25 06:25:59 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 25 06:25:59 2019 +0000" }, "message": "Merge \"Fix a false fail for SMC WORKAROUND2 test on Cortex-A76\"" }, { "commit": "1b92611fddb4b3360ca1d6db3b91a2c3b7bf99bb", "tree": "8e34cf61f431a255cf7f3004d9e3cce4c6e74530", "parents": [ "2676b99a81b4f886b7b79189cbe432705843977b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Sep 16 14:46:31 2019 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Sep 24 12:10:43 2019 -0500" }, "message": "Fix a false fail for SMC WORKAROUND2 test on Cortex-A76\n\nSome platforms with A76 core do not require the dynamic\nmitigation using SMCCC_ARCH_WORKAROUND_2 call. Test which\nverifies such workaround can be skipped in such scenario.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Iacf27da7181828a2fd1166bd6eeb069ba27da0c5\n" }, { "commit": "2129608e9ab970909c924a934a93a501099ab3bc", "tree": "68fee8b5582b4ba8c366fe13e51f7f9a67ce862b", "parents": [ "2676b99a81b4f886b7b79189cbe432705843977b" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Wed Sep 18 14:53:33 2019 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Mon Sep 23 14:50:12 2019 -0500" }, "message": "Separate shutdown and stats after shutdown tests\n\nCreating new test suite for System shutdown and stats after shutdown\ntests separate from the other manual tests since the others have been\nautomated for some platforms. This test suite is intended to be used\nfor manual testing for the upcoming release.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I3725b28528696fa51d4c1f3af60f8a6e61e1a702\n" }, { "commit": "2676b99a81b4f886b7b79189cbe432705843977b", "tree": "9c16d690c69f9d9cdab479da158472dd7f688e21", "parents": [ "4c213e5eb22269da1a92b53c01a91e8f36439a0e", "89391603d63fd409c18e00e45c864dc9749f2f25" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Aug 16 15:27:53 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 16 15:27:53 2019 +0000" }, "message": "Merge \"Create new xml to split Juno reboot tests\"" }, { "commit": "89391603d63fd409c18e00e45c864dc9749f2f25", "tree": "f8c42818b8d0345db9f19d438597078e37e7e8bd", "parents": [ "6927d85a0429bd247cb76b7cb4201e330fc745a1" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Wed Jul 31 15:33:07 2019 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Aug 08 10:15:51 2019 -0500" }, "message": "Create new xml to split Juno reboot tests\n\nCreating a new xml to separate Juno TFTF reboot tests by those that are expected to pass and\nthose that aren\u0027t (2 RESET2 tests).\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I101de828aeedd33e0601597b70e00056b884ceba\n" }, { "commit": "4c213e5eb22269da1a92b53c01a91e8f36439a0e", "tree": "40a8030578f1abbb33633c3783e26cdb6c94e4a3", "parents": [ "f70889bee012047998ec9fd0942eca9f99120c67", "ee3e7cd720887077ad27f48f4c8e681926c16587" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Aug 02 06:50:04 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 02 06:50:04 2019 +0000" }, "message": "Merge \"ld: Separate code and RO data sections\"" }, { "commit": "f70889bee012047998ec9fd0942eca9f99120c67", "tree": "b47d5b879a4a3ef00ed1c2fb5553d839c15f1d31", "parents": [ "6927d85a0429bd247cb76b7cb4201e330fc745a1", "38c645cbe3089e6878a75a5d3e41a7dcfdc26286" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Aug 02 06:49:32 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 02 06:49:32 2019 +0000" }, "message": "Merge \"TF-A Tests: Pick up changes from TF-A code base\"" }, { "commit": "ee3e7cd720887077ad27f48f4c8e681926c16587", "tree": "b2be6933f915effc206f73faf1ce5a73118751c7", "parents": [ "6927d85a0429bd247cb76b7cb4201e330fc745a1" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Wed Jul 03 16:44:49 2019 +0100" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Thu Aug 01 11:34:18 2019 +0100" }, "message": "ld: Separate code and RO data sections\n\nThis prevents the execution of the read-only data.\n\nThis is done in a similar way in TF-A when the build flag\nSEPARATE_CODE_AND_RODATA is enabled.\n\nThe build flag is probably not needed in TF-A Tests.\n\nChange-Id: I2bdc0237c00377beb2febeb47207770c85036192\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "38c645cbe3089e6878a75a5d3e41a7dcfdc26286", "tree": "b47d5b879a4a3ef00ed1c2fb5553d839c15f1d31", "parents": [ "6927d85a0429bd247cb76b7cb4201e330fc745a1" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Aug 01 11:27:20 2019 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Aug 01 11:27:20 2019 +0100" }, "message": "TF-A Tests: Pick up changes from TF-A code base\n\nThis patch pick up the following changes from TF-A:\n- Fix for SCTLR bit definitions in \u0027include/lib/aarch64/arch.h`\n- Introduction of 128-bit integer types int128_t and uint128_t\nin \u0027include/lib/libc/aarch64/stdint.h_`\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I7e7b1b6d8f79eeb6b16df2ce2bea07c5748d1216\n" }, { "commit": "6927d85a0429bd247cb76b7cb4201e330fc745a1", "tree": "1b15e54ea94905d8b3095a4137e514ddeba5911e", "parents": [ "c78987eee6cc5b9f0c02da288c3a4331429a6014", "513be4966f8a9db2fe3166efdc03843f5010cdfe" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jul 31 14:28:11 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 31 14:28:11 2019 +0000" }, "message": "Merge \"Creating separate xml for Reboot tests\"" }, { "commit": "c78987eee6cc5b9f0c02da288c3a4331429a6014", "tree": "89f6a460b4d075671de8b4bbc9879d1722dd2f69", "parents": [ "31db80cc6d39f506fb2913c93380c2acde391094", "8dec845212bede5e127ef7293e0b20c9e02195ed" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jul 31 12:09:50 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 31 12:09:50 2019 +0000" }, "message": "Merge \"TF-TF: Fix bug in calculation of number of CPUs\"" }, { "commit": "513be4966f8a9db2fe3166efdc03843f5010cdfe", "tree": "d775a570f1b96baed834b921b7d411c1a6a499d9", "parents": [ "7bdfa0b07a52e487a443394aad89bcd37fbc02a8" ], "author": { "name": "lauwal01", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jul 09 10:58:01 2019 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Fri Jul 26 12:36:12 2019 -0500" }, "message": "Creating separate xml for Reboot tests\n\nSeparating the manual tests xml to only include reboot tests so these\ncan be automated.\n\nChange-Id: Ib1dfe7f215811e9ecb5b8f439965465187b3fe9b\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\n" }, { "commit": "8dec845212bede5e127ef7293e0b20c9e02195ed", "tree": "32c429ca955deda4928c94b5bef2618ee87bb1f8", "parents": [ "7bdfa0b07a52e487a443394aad89bcd37fbc02a8" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Jul 16 09:34:24 2019 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jul 17 16:41:54 2019 +0100" }, "message": "TF-TF: Fix bug in calculation of number of CPUs\n\nThis patch fixes the bug in tftf_get_total_aff_count()\nwhich incorrectly calculates the number of CPUs for\naff_lvl \u003d 0. The function reads tftf_pd_nodes[] array\nonly based on condition\n`tftf_pd_nodes[node_idx].level \u003d\u003d aff_lvl` but\ndoesn\u0027t check for `indexes \u003c PLATFORM_NUM_AFFS`.\nThis causes reads of the array beyond its boundaries\nwhich results in incorrect calculation of number of CPUs,\nand some of the tests entering infinite loops.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: If7b2d8eba7560126aeff29c6b8c9355198aad453\n" }, { "commit": "31db80cc6d39f506fb2913c93380c2acde391094", "tree": "ae0109aefaf241e77345d0b6f9d6432f481da693", "parents": [ "7bdfa0b07a52e487a443394aad89bcd37fbc02a8", "d1193ef6d09b94e5c5083b868371d1ace9149854" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jul 17 15:05:42 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 17 15:05:42 2019 +0000" }, "message": "Merge \"Skip multicore spurious interrupt test\"" }, { "commit": "d1193ef6d09b94e5c5083b868371d1ace9149854", "tree": "ae0109aefaf241e77345d0b6f9d6432f481da693", "parents": [ "7bdfa0b07a52e487a443394aad89bcd37fbc02a8" ], "author": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Tue Jul 16 15:30:22 2019 +0100" }, "committer": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Tue Jul 16 15:54:21 2019 +0100" }, "message": "Skip multicore spurious interrupt test\n\nThis specific test is known to have unstable behaviour. As a temporary\nsolution we skip this test for AArch64 Juno configs.\n\nChange-Id: I7c93de0c80ad8dba47b83f0b343d868dc18b732f\nSigned-off-by: John Tsichritzis \u003cjohn.tsichritzis@arm.com\u003e\n" }, { "commit": "7bdfa0b07a52e487a443394aad89bcd37fbc02a8", "tree": "07e42b8ab8a08c40959c15f5e4a53ce93177c676", "parents": [ "39b397af7566135498e6995102698c0efb0dc90c", "e36bf03bb7ec22a463e8077aace4fda1ea90d87d" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jun 28 06:24:56 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 28 06:24:56 2019 +0000" }, "message": "Merge \"Add missing testsuites in extensive set of tests\"" }, { "commit": "e36bf03bb7ec22a463e8077aace4fda1ea90d87d", "tree": "07e42b8ab8a08c40959c15f5e4a53ce93177c676", "parents": [ "39b397af7566135498e6995102698c0efb0dc90c" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jun 26 15:36:23 2019 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jun 27 11:01:52 2019 +0200" }, "message": "Add missing testsuites in extensive set of tests\n\nThe extensive set of tests is meant to be a superset of the standard\nset. However, 2 testsuites were present in the standard set and were\nmissing from the extensive one.\n\nChange-Id: Idc5d6abd9a2bcdfcfa41421e823a88095ab4e16e\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "39b397af7566135498e6995102698c0efb0dc90c", "tree": "ee8e82f936f3008e99b80f97c487d369437f51f8", "parents": [ "11c53c86d4828b12ffa61ce180b0c4e694348ae3", "8051274dfc4dae689ba53bc3e56d320780cbd5a4" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jun 20 11:57:17 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 20 11:57:17 2019 +0000" }, "message": "Merge \"libc: fix memchr implementation\"" }, { "commit": "8051274dfc4dae689ba53bc3e56d320780cbd5a4", "tree": "ee8e82f936f3008e99b80f97c487d369437f51f8", "parents": [ "11c53c86d4828b12ffa61ce180b0c4e694348ae3" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Thu Jun 20 10:03:17 2019 +0100" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Thu Jun 20 10:03:17 2019 +0100" }, "message": "libc: fix memchr implementation\n\nThe previous implementation could behave incorrectly because of the sign\nextension of the char when compared to the int.\n\nChange-Id: Id1e40ca9cfb1c271cb391e26698862726b833c8b\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "11c53c86d4828b12ffa61ce180b0c4e694348ae3", "tree": "52d5d996388dc808ee73088dc1aa58cdd7f12ad6", "parents": [ "16a4773b5330d348997ae2dd3204992e590702b4", "d64e1539d505e537282f6c31e42f16474a6b5bda" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jun 18 15:57:31 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 18 15:57:31 2019 +0000" }, "message": "Merge \"Add test to measure latencies when turning ON a cluster\"" }, { "commit": "d64e1539d505e537282f6c31e42f16474a6b5bda", "tree": "7a7a86f914f48342f8b1e482195df01a2de5b95d", "parents": [ "a3ccf4b875dc5500662262a9a15a29525da04312" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jul 09 13:10:21 2018 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Jun 18 10:53:05 2019 +0100" }, "message": "Add test to measure latencies when turning ON a cluster\n\nChange-Id: If698dc76c1873fb79ffe63ac6ee0c808186310ac\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "16a4773b5330d348997ae2dd3204992e590702b4", "tree": "e9b28bc0a3b3019eb44dad2c80307bc86ef2cd14", "parents": [ "a3ccf4b875dc5500662262a9a15a29525da04312", "3fd90497faa87ef81b60aa685689bda015f2acb1" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jun 12 06:46:19 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 12 06:46:19 2019 +0000" }, "message": "Merge \"Support for FVP cluster with 8 CPUs.\"" }, { "commit": "3fd90497faa87ef81b60aa685689bda015f2acb1", "tree": "24046b7a9287064cf03ee4d9e40be888367987f7", "parents": [ "c9ab1fd3b32cc3adce83b76a5a801ae492c175ff" ], "author": { "name": "Madhukar", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 04 15:57:18 2019 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 11 10:10:22 2019 -0500" }, "message": "Support for FVP cluster with 8 CPUs.\n\nFew Cortex FVPs have upto 8 CPUs in single clsuter. This patch solves\nthe issue reported in https://developer.trustedfirmware.org/T333\n\nChange-Id: I14c36b0d643a85527b7122cee0f728fddb871ec7\nSigned-off-by: Madhukar Pappireddy\u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "a3ccf4b875dc5500662262a9a15a29525da04312", "tree": "7c21d4c11ab786608629cffd8ac43ba9f25069d5", "parents": [ "7a5ade85e460988fe8540066eaecde6a3f36c894", "49180a8496b41f77bbf89b4d3db3830e135ea405" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jun 11 10:50:06 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 11 10:50:06 2019 +0000" }, "message": "Merge \"Cosmetic changes to suspend_private.h\"" }, { "commit": "49180a8496b41f77bbf89b4d3db3830e135ea405", "tree": "0605865a1da94d6ce883a749d0b9195c9ff4d3d7", "parents": [ "c9ab1fd3b32cc3adce83b76a5a801ae492c175ff" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 07 16:35:48 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jun 06 13:31:56 2019 +0200" }, "message": "Cosmetic changes to suspend_private.h\n\nReword some comments, express offsets relative to one another, move the\ncompile-time assertions closer to the structure they depend on.\n\nChange-Id: Id3d61ca704321844d12c9bb25e2e6eb303a7a579\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "7a5ade85e460988fe8540066eaecde6a3f36c894", "tree": "501e62a9b578008aac0670d4241906d364d028ec", "parents": [ "c9ab1fd3b32cc3adce83b76a5a801ae492c175ff", "167fe8352a1a60df1c551ecfc86b68154da1774a" ], "author": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Wed Jun 05 16:34:30 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 05 16:34:30 2019 +0000" }, "message": "Merge \"doc: Update communication tools\"" }, { "commit": "167fe8352a1a60df1c551ecfc86b68154da1774a", "tree": "501e62a9b578008aac0670d4241906d364d028ec", "parents": [ "c9ab1fd3b32cc3adce83b76a5a801ae492c175ff" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jun 03 10:56:28 2019 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jun 04 14:03:48 2019 +0100" }, "message": "doc: Update communication tools\n\nPrefer to use the trustedfirmware.org collaboration tools (i.e. issues\ntracker and development mailing list) over the #trusted-firmware-a IRC\nchannel.\n\nChange-Id: I78aef022b00cd553e1ab6542b967dd3f0640dd52\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "c9ab1fd3b32cc3adce83b76a5a801ae492c175ff", "tree": "7bc7490da8fab528fc151eb712adc02efa5a414d", "parents": [ "16a32f7e388fc3246b1e1d06c815a0fa09cd7818", "cae91ca61cc36462c3e1b639c2725535a0c05df4" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue May 28 07:49:13 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue May 28 07:49:13 2019 +0000" }, "message": "Merge changes from topic \"jts/amu\"\n\n* changes:\n Fix AMU non-zero counters test\n Remove unexecuted code for AMU group 1 counters\n" }, { "commit": "cae91ca61cc36462c3e1b639c2725535a0c05df4", "tree": "7bc7490da8fab528fc151eb712adc02efa5a414d", "parents": [ "68759a8015fc997aeeb2fb0caf6b55bbbec73d02" ], "author": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Sun May 12 16:06:09 2019 +0100" }, "committer": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Fri May 24 14:10:51 2019 +0100" }, "message": "Fix AMU non-zero counters test\n\nThe condition checked in one of the AMU tests (AMU counters always\nnon-zero) does not always hold. The counter that counts the memory stall\ncycles, under certain circumstances, can be zero. Hence, the test is\nadjusted accordingly and, consequently, renamed.\n\nChange-Id: I8c7300481c2b45825101ee87f61c68c2ab51758a\nSigned-off-by: John Tsichritzis \u003cjohn.tsichritzis@arm.com\u003e\n" }, { "commit": "68759a8015fc997aeeb2fb0caf6b55bbbec73d02", "tree": "25fb8d86e88f96e86ed9cdfa50f717662b641ff0", "parents": [ "16a32f7e388fc3246b1e1d06c815a0fa09cd7818" ], "author": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Sun May 12 15:10:27 2019 +0100" }, "committer": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Mon May 20 12:43:55 2019 +0100" }, "message": "Remove unexecuted code for AMU group 1 counters\n\nThis patch removes from the AMU tests the part that iterates over group\n1 counters. The reasons for this are the following:\n\n1) Currently the AMU tests are executed only in FVP but FVP doesn\u0027t\nhave/expose group 1 counters.\n\n2) Even if some platform implements group 1 counters in the future, we\ndon\u0027t know what they will be counting. As such we cannot know what the\nvalid values for those counters will be. Hence, we can\u0027t establish a\nspecific test at this moment to validate the group 1 counter values.\n\n3) Even now that the loop exists in the code, the macro defining the\ngroup 1 counters is defined as zero. Which means that the loop is\nalready not executed, despite being there (dead code).\n\nHowever, the architecture defines how group 1 counters should be\nimplemented. For this reason, the assembly helper functions that access\nthe group1 counters are left intact. This will allow us to easily extend\nthe AMU tests again in the future to include group 1 counters.\n\nChange-Id: I5a6f119c7e817de9dc5e510c3fadd008820bd564\nSigned-off-by: John Tsichritzis \u003cjohn.tsichritzis@arm.com\u003e\n" }, { "commit": "16a32f7e388fc3246b1e1d06c815a0fa09cd7818", "tree": "bb892f0c8949550fcba0111186e559998a47ff0f", "parents": [ "2755ecb5dcab5fac6295245a15afaecfff8eba78", "7c5df58ddbb2c55a0ef16d1e8d9ae3f3d2f4c73e" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri May 17 07:28:22 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 17 07:28:22 2019 +0000" }, "message": "Merge changes from topic \"sb/el3-payload\"\n\n* changes:\n run_armds_script.sh: Ask user which DSTREAM to connect to\n Adapt run_ds5_script.sh for recent Arm DS versions\n" }, { "commit": "7c5df58ddbb2c55a0ef16d1e8d9ae3f3d2f4c73e", "tree": "bb892f0c8949550fcba0111186e559998a47ff0f", "parents": [ "47ab4f4fd1c650eff22844593577814a095952dd" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Aug 30 17:37:43 2018 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri May 10 14:31:07 2019 +0200" }, "message": "run_armds_script.sh: Ask user which DSTREAM to connect to\n\nPreviously the script to run the EL3 payload on Juno would connect to\nthe first DSTREAM it detected, without even asking the user\u0027s consent.\n\nChange-Id: I1586957094cc3247c1dadf0adac263af0256e03d\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "47ab4f4fd1c650eff22844593577814a095952dd", "tree": "522f39bd3f176b4d74c4eda9aaf302e61b7e9444", "parents": [ "2755ecb5dcab5fac6295245a15afaecfff8eba78" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri May 10 13:23:41 2019 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri May 10 14:31:07 2019 +0200" }, "message": "Adapt run_ds5_script.sh for recent Arm DS versions\n\nArm DS-5 has been superseded by Arm Development Studio. Do the necessary\nchanges to the EL3 payload scripts to migrate to the latter:\n\n - Rename run_ds5_script.sh into run_armds_script.sh.\n - The command-line debugger is now called armdbg.\n - The CDB entry string for Arm Juno development board has changed.\n\nChange-Id: Idc640e7fcff790d5a1bf6e938e14a0dbc88029b9\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "2755ecb5dcab5fac6295245a15afaecfff8eba78", "tree": "9805a9ad3d674ccd3d5d2f7dc83696955a1c947d", "parents": [ "1f018ba629bd534a14bbf133d4e9fa61e2f09686", "96e250320b9c1cec90946e93d87f27fdafac5092" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue May 07 13:07:13 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue May 07 13:07:13 2019 +0000" }, "message": "Merge \"Fix AArch32 build error\"" }, { "commit": "96e250320b9c1cec90946e93d87f27fdafac5092", "tree": "9805a9ad3d674ccd3d5d2f7dc83696955a1c947d", "parents": [ "1f018ba629bd534a14bbf133d4e9fa61e2f09686" ], "author": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Tue May 07 10:42:22 2019 +0100" }, "committer": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Tue May 07 10:51:44 2019 +0100" }, "message": "Fix AArch32 build error\n\nPointer authentication code should be conditionally compiled only if\nTFTF is built for AArch64 since AArch32 doesn\u0027t support pointer\nauthentication. This was previously causing a compilation error.\n\nChange-Id: I97a0ea66f562cf2ebb41478b1b31a26bcaf815b2\nSigned-off-by: John Tsichritzis \u003cjohn.tsichritzis@arm.com\u003e\n" }, { "commit": "1f018ba629bd534a14bbf133d4e9fa61e2f09686", "tree": "eae0800de352250121d33417c78520ae16012291", "parents": [ "3da9cb1fcad88d5c7ca60141c067ad5559cdb399", "8d84b4c68c5f015b1315034dd1d64767ce5401e8" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue May 07 07:29:21 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue May 07 07:29:21 2019 +0000" }, "message": "Merge \"Add topology helper to get parent node\"" }, { "commit": "8d84b4c68c5f015b1315034dd1d64767ce5401e8", "tree": "eae0800de352250121d33417c78520ae16012291", "parents": [ "3da9cb1fcad88d5c7ca60141c067ad5559cdb399" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jul 09 13:07:57 2018 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Apr 29 15:36:28 2019 +0100" }, "message": "Add topology helper to get parent node\n\nIt was not possible to get a parent node given an MPIDR\nof the CPU using the current topology APIs. This patch adds\nthe `tftf_get_parent_node_from_mpidr()` API to achieve the same.\n\nChange-Id: I818f1e628689928293c1fdb85606885e851a5785\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "3da9cb1fcad88d5c7ca60141c067ad5559cdb399", "tree": "03dea16e67cb32994050580fd74a0fb5cb9c9994", "parents": [ "5394feaf2190cb0a80ff0b633d2702a9add337a2" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Tue Apr 23 10:53:45 2019 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Tue Apr 23 10:53:45 2019 +0100" }, "message": "drivers: console: pl011: Move comments to header\n\nRather than having the description of each function in the\nimplementation, move it to the header so that it isn\u0027t needed to copy\nit in each file that implements a console driver.\n\nChange-Id: I1b437ae3d3ccff10979466727353bc1fa1d5b188\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "5394feaf2190cb0a80ff0b633d2702a9add337a2", "tree": "140067e4ede341c460971103a6bb3adbec3de091", "parents": [ "26b3864c09add32f2b5a8e3798c9731fc856e9a5" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Apr 17 13:12:10 2019 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Apr 17 13:14:48 2019 +0100" }, "message": "quark: Introduce simple TFTF test\n\nIntroduce test to verify that Quark is present in the system.\n\nChange-Id: Ia31e65e737b8909f7caecae830fcb217e88a9b01\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "26b3864c09add32f2b5a8e3798c9731fc856e9a5", "tree": "224a51e581518b4acb6d1e8b960fee5134474cae", "parents": [ "1d03668d7ebe6286b70808097d80b72d624be0a2" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Mar 28 13:16:04 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Apr 17 13:14:48 2019 +0100" }, "message": "quark: Introduce Quark Secure Partition\n\nTest partition designed to have a virtual address space as small as\npossible in order to test the extension ARMv8.4-TTST. This Secure\nPartition doesn\u0027t have print capabilities. The only service it provides\nis one that returns a magic number to verify that it has been loaded.\n\nChange-Id: I431f6c65f2926d486836d12ddfefe05e83b0c47f\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "1d03668d7ebe6286b70808097d80b72d624be0a2", "tree": "a883d996054c046a55984d93665acdd52c989f7f", "parents": [ "6a82072252cb14349a7d89c3eaed9204f7f01bd7" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Mar 27 15:23:59 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Apr 17 13:14:47 2019 +0100" }, "message": "drivers: dummy_console: Add dummy console driver\n\nPlaceholder driver with empty functions.\n\nChange-Id: I50accca77995c642c7b920bdc1b7d936e7883313\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "6a82072252cb14349a7d89c3eaed9204f7f01bd7", "tree": "ee88100c271d2a19d5f7435d0bbef7745aed66f1", "parents": [ "dd842755d5567569c706ca1cd7b9416ed1caef12", "6a6f48338312f1b8e5637fa85d7942e6bb9d8bab" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Apr 15 07:25:08 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Apr 15 07:25:08 2019 +0000" }, "message": "Merge \"Makefile: Enable strict align arch minor version\"" }, { "commit": "6a6f48338312f1b8e5637fa85d7942e6bb9d8bab", "tree": "758dea2b85bfd8e97a5d86f65b73a81a7f93d15e", "parents": [ "8790f025e12065ccccfe4d19fdcc672c80aa784b" ], "author": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Mon Apr 08 15:46:36 2019 +0100" }, "committer": { "name": "Joel Hutton", "email": "Joel.Hutton@arm.com", "time": "Fri Apr 12 15:43:03 2019 +0100" }, "message": "Makefile: Enable strict align arch minor version\n\nAdd -mstrict-align flag, and -march minor version. These are needed to\nprevent compilers generating unaligned accesses and enable\narchitectural features respectively.\n\nEnable the SCTLR.A and SCTLR.SA alignment checks in all images.\n\nTF test has several cases of code which enable the alignment checks.\n\nChange-Id: I9a0413786caf94d0abf376aa1b4fb54fc7f2f355\nSigned-off-by: Joel Hutton \u003cJoel.Hutton@Arm.com\u003e\n" }, { "commit": "dd842755d5567569c706ca1cd7b9416ed1caef12", "tree": "93b7b65f111add64c1f75ed6299e509ad15d67e6", "parents": [ "8790f025e12065ccccfe4d19fdcc672c80aa784b" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Apr 10 09:30:10 2019 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Apr 10 12:13:34 2019 +0000" }, "message": "Update links to TF-A documentation\n\nUpdate the links to the TF-A documentation to point to\ntrustedfirmware.org rather than Github.\n\nChange-Id: Ib49b90b6733cdf6acd17d95e6d4968ac162bd150\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "8790f025e12065ccccfe4d19fdcc672c80aa784b", "tree": "e5548628d170748a3f2d98973b4db315a76c88ef", "parents": [ "29ef1dd13dfb989008fc98f7f7c17f163e0479bf" ], "author": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Fri Mar 15 14:47:02 2019 +0000" }, "committer": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Mon Apr 08 14:34:42 2019 +0100" }, "message": "Add unit tests for Pointer Authentication\n\nAdd unit tests to:\n Test access to the key registers.\n Use the pointer authentication instructions.\n Call psci version and check the EL3 pointer authentication keys\n aren\u0027t leaked.\n Make a tsp call and check the secure world keys aren\u0027t leaked.\n\nChange-Id: Ic7940757e6f9fc905ccef8c035e0c22b47b35cd7\nSigned-off-by: Joel Hutton \u003cJoel.Hutton@Arm.com\u003e\n" }, { "commit": "29ef1dd13dfb989008fc98f7f7c17f163e0479bf", "tree": "8037437c8156f8fb43e26b1da5996223ed15014c", "parents": [ "cc0239947d60902a114247277523943fcf537e1d" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Apr 04 11:18:49 2019 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Apr 04 11:19:25 2019 +0100" }, "message": "xlat v2: Synchronize with TF-A\n\nChange-Id: Ibd277c918088cf2afdd262689fa1e1c4ad369619\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "cc0239947d60902a114247277523943fcf537e1d", "tree": "853a0aaf2182f0c563e4df8ef6266cc5462924e0", "parents": [ "372b675ac20e2addc1c13f36ce61e5f90749f40d" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Apr 04 11:18:32 2019 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Apr 04 11:19:19 2019 +0100" }, "message": "Partial sync of architectural headers with TF-A\n\nChange-Id: I0509065512907217dc17c0ec5ce474e2bb8d4e89\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "372b675ac20e2addc1c13f36ce61e5f90749f40d", "tree": "e788daebf2b14c2ea79f1b4763aac97b010d2203", "parents": [ "fae77720145bf50b0965b90d0055015a21923aef", "f152f8f480f36b448d1f8b02e4902ae30523cca5" ], "author": { "name": "Antonio Niño Díaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Apr 04 10:06:38 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 04 10:06:38 2019 +0000" }, "message": "Merge changes from topic \"an/xlat-v2-tests\"\n\n* changes:\n xlat v2: Alignment tests\n xlat v2: Stress tests\n Increase virtual address space size in AArch64\n xlat v2: Add unit tests\n" }, { "commit": "fae77720145bf50b0965b90d0055015a21923aef", "tree": "a11e91b812f0c1bd4a62fd3aa644b82947877907", "parents": [ "88e96a1d790ca47c500a254dea32426e41e4e369" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Thu Mar 07 10:17:15 2019 +0000" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Apr 01 11:08:40 2019 +0100" }, "message": "Introduce test for SVE support\n\nWhen SVE extension is enabled, test that it correctly performs simple\noperations.\n\nGenerating SVE instructions requires O3 compilation optimization. Since\nthe build structure does not allow compilation flag modification for\nspecific files, the function testing SVE support has been pre-compiled\nand added as an assembly file.\n\nChange-Id: Id9ba7d9e1de9bcbae3065cad2dd3e1dbe87ef03a\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "f152f8f480f36b448d1f8b02e4902ae30523cca5", "tree": "76ff0aa3a6e67366fa3d4e5cc5381955788e9941", "parents": [ "402b269ccd3926feab74ba4dfb39d6f0dc703c4d" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Oct 05 15:18:45 2018 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Mar 29 13:00:08 2019 +0000" }, "message": "xlat v2: Alignment tests\n\nChange-Id: I6a689998a74f7841c668ccbb4be7b03d36b355b2\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "402b269ccd3926feab74ba4dfb39d6f0dc703c4d", "tree": "9dbcc4070eb546b9b5234b0f59f9deb6f4b6db5a", "parents": [ "f00940b6a36458d0a321e1defbe2599453f29913" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Oct 05 15:11:38 2018 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Mar 29 13:00:08 2019 +0000" }, "message": "xlat v2: Stress tests\n\nChange-Id: I2b5de1b884db78eea6d83ab8b31de32b5c23b316\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "f00940b6a36458d0a321e1defbe2599453f29913", "tree": "fa284d5dd94ca9ef81fc4124c55a3f545b718ac7", "parents": [ "54959b0c9989faccec05d420aee14ff865d60fab" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Mon Aug 13 09:54:26 2018 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Mar 29 13:00:07 2019 +0000" }, "message": "Increase virtual address space size in AArch64\n\nThis is needed to have room for xlat v2 tests.\n\nChange-Id: Ic4e39f8f964c2c41effc99f1b419cf7cdc405bbb\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "54959b0c9989faccec05d420aee14ff865d60fab", "tree": "a73e3908a4a82b89ff2d31f5cb346411305dc751", "parents": [ "88e96a1d790ca47c500a254dea32426e41e4e369" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Mar 29 12:59:35 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Mar 29 12:59:35 2019 +0000" }, "message": "xlat v2: Add unit tests\n\nAdd basic unit tests for the xlat tables library v2.\n\nChange-Id: I814470d2aceec8a7d1da5190c7c5b355178b1a54\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "88e96a1d790ca47c500a254dea32426e41e4e369", "tree": "f134a85da7dfc1f3bdcefb05db514c4231651103", "parents": [ "931e057f2c56fb852dc8141912933eda3e1b12e9" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 28 09:34:55 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 28 17:04:35 2019 +0100" }, "message": "Update change log for v2.1 release\n\nChange-Id: I2e593badc2c0923d292f3d55d384c8d6e1f6a0df\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "931e057f2c56fb852dc8141912933eda3e1b12e9", "tree": "521ebd5a0f0d0f20c04a2bffe673ff5ea0c60bac", "parents": [ "61667c63a548d20b0fdd230d2f2f2de37c765aca" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 21 09:32:28 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 28 17:04:35 2019 +0100" }, "message": "Update readme.rst file for v2.1 release\n\n - Bump version from 2.0 to 2.1.\n - Upgrade recommended FVP version.\n\nChange-Id: I8c7bae8b8285ec6228a2e1ed1bfbe1d8ffc51587\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "61667c63a548d20b0fdd230d2f2f2de37c765aca", "tree": "d2c4e477dfb4edf57803ebcd11a0369ce804e469", "parents": [ "b1e04de8f886e81c09be639668ed449fc9c8d7bf" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Mar 20 13:58:28 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 28 17:04:35 2019 +0100" }, "message": "Upgrade version string displayed on startup\n\nChange-Id: I0b319f9724d540b46c5d8ded3cb37f686871ec95\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "b1e04de8f886e81c09be639668ed449fc9c8d7bf", "tree": "8c16bfcc72bd087412e30ebaf3348253d43196da", "parents": [ "9f5a2e3ba0503404152098e9d5884d5502f7b48f" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 21 09:35:01 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 28 17:03:44 2019 +0100" }, "message": "Add missing link to issues tracker in readme file\n\nChange-Id: I69cb86be54bf84a3e42a498382f373b193737d8a\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "9f5a2e3ba0503404152098e9d5884d5502f7b48f", "tree": "08a6de2edaa70b7cb14ff63df5b6ea9f030b83a3", "parents": [ "de3a7e1d07d9aa943e7abe938c964f784bf3243e", "a29e2bdf708458430016d2efd43ef15af0cf18d8" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 28 09:55:11 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 28 09:55:11 2019 +0000" }, "message": "Merge \"Update user guide on manual tests\"" }, { "commit": "de3a7e1d07d9aa943e7abe938c964f784bf3243e", "tree": "a1a5113f397693e9d1d30abe27d7f5ac9b05d335", "parents": [ "c498eebb153cc520fa146eb199c1027c7880b4e5" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Mar 20 14:28:05 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 28 09:33:54 2019 +0000" }, "message": "Remove Jeenu Viswambharan from the maintainers list\n\nChange-Id: If1447c63ff985ce8fdaeef0c4939dbacff99a5ee\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "c498eebb153cc520fa146eb199c1027c7880b4e5", "tree": "74974a47c66e46a012db8916d61aab064394e548", "parents": [ "3b725db7bb951cb43e9119fbd96cf60eb2e23a92" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Mon Mar 25 13:13:57 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Mon Mar 25 13:13:57 2019 +0000" }, "message": "docs: Update SPM User Guide instructions\n\nChange-Id: I33f4ef5707641a4a7dc597c3c9bf6c2c82111d65\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "a29e2bdf708458430016d2efd43ef15af0cf18d8", "tree": "959df87c0e160efd00277549f1d5751471ce6bb4", "parents": [ "3b725db7bb951cb43e9119fbd96cf60eb2e23a92" ], "author": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Fri Mar 22 16:40:33 2019 +0000" }, "committer": { "name": "Joel Hutton", "email": "joel.hutton@arm.com", "time": "Fri Mar 22 17:19:29 2019 +0000" }, "message": "Update user guide on manual tests\n\nUpdate the user guide to reflect the correct flags needed\nfor the manual tests.\n\nChange-Id: I5459e06f26f25e0f269c75adce1ec3a23f64e809\nSigned-off-by: Joel Hutton \u003cJoel.Hutton@Arm.com\u003e\n" }, { "commit": "3b725db7bb951cb43e9119fbd96cf60eb2e23a92", "tree": "98bd1da412d0a9d2845987c763565941b7de2384", "parents": [ "b4ddca80b1b20bf2f1870e9623b18e5c11139847", "eb1a41684e7cfd40beeff12a518a5e7c23d9c8c7" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 21 15:54:38 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 21 15:54:38 2019 +0000" }, "message": "Merge changes from topic \"an/fix-spm-mm\"\n\n* changes:\n SPM-MM: Re-enable disabled tests\n SPM-MM: Fix call preemption test\n" }, { "commit": "eb1a41684e7cfd40beeff12a518a5e7c23d9c8c7", "tree": "0fba84f97074295030779c22f546b70356cdccff", "parents": [ "81d507ef3c46760d1a67460eaeaac20cb50ee48c" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Mar 20 16:03:49 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Mar 21 13:54:52 2019 +0000" }, "message": "SPM-MM: Re-enable disabled tests\n\nThe tests are actually passing now.\n\nChange-Id: I0f9ef11dabded51daf791c42ce0e22ff222425db\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "81d507ef3c46760d1a67460eaeaac20cb50ee48c", "tree": "18af1e706cd8af726df6a9ca964ba106dd0d132d", "parents": [ "f2218e7b6a4f8c2c3d6db00703caad95f5e5b157" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Mar 21 13:49:23 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Mar 21 13:54:52 2019 +0000" }, "message": "SPM-MM: Fix call preemption test\n\nThe timer was being set up for 1 ms rather than 1 second.\n\nChange-Id: I16d6ea69d42abf28dc9591e97d6bfb302d5f8127\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "b4ddca80b1b20bf2f1870e9623b18e5c11139847", "tree": "7538138fb153c315c8103eb2191c93dd563a1754", "parents": [ "f2218e7b6a4f8c2c3d6db00703caad95f5e5b157", "9c9f92c4c4cd07ea75ea72a42f15b32ed4c01bf0" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Mar 20 17:28:50 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 20 17:28:50 2019 +0000" }, "message": "Merge changes from topic \"an/pauth\"\n\n* changes:\n Add ARMv8.3 pointer authentication support\n Remove pointer authentication test\n" }, { "commit": "f2218e7b6a4f8c2c3d6db00703caad95f5e5b157", "tree": "83f72bbabcabae7e25e82c3192d27718dea21f67", "parents": [ "960906b2d8fc2596f257b55606c69505d2bf1130" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Tue Mar 19 10:59:11 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Tue Mar 19 11:22:43 2019 +0000" }, "message": "Reintroduce Cactus-MM and SPM-MM tests\n\nThe code has been taken from commit 99f4fd283b6f (\"cactus: Use UART2\ninstead of UART0\") and modified slightly to be integrated in the current\nmaster.\n\nThere are three tests that are failing in the CI. They have been\ndisabled for the time being:\n\n- mem_attr_changes_tests() in cactus_main() in the file\n spm/cactus_mm/cactus_mm_main.c.\n\n- Two tests in the file tftf/tests/tests-spm-mm.xml.\n\nChange-Id: I6332cbff1cefeb82b9447fae1b613879e65186a1\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "960906b2d8fc2596f257b55606c69505d2bf1130", "tree": "4954a1fe21024c8f407e0a74964f64119fe76788", "parents": [ "bf8f1b887d2f03757ca6d06ce21e455e4fd5e71c" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Feb 08 11:32:05 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Mar 18 14:23:35 2019 +0000" }, "message": "Check arguments when building manual tests\n\nManual tests require setting USE_NVM\u003d1 and NEW_TEST_SESSION\u003d0\notherwise they will not function properly (as test results will\nnot be preserved across reboots). We should check that these\nvariables have the required values during the build.\n\nChange-Id: I72fc8a4badf107fe2ebd6bfb88631828e14a77b3\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "bf8f1b887d2f03757ca6d06ce21e455e4fd5e71c", "tree": "599434ad1c200ac1967fbc1c87310398ba75c2a2", "parents": [ "f1837f87275147f6bf8c277445367b9d5a9c805d" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Mar 18 13:42:54 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Mar 18 14:23:35 2019 +0000" }, "message": "Remove tests-fwu.mk from tests-standard.mk\n\nThe FWU test components are being built as part of the\ntests-standard.mk configuration but tests-standard does not\nactually run any FWU tests (see tests-standard.xml). These FWU\ntest components do not need to be built.\n\nChange-Id: I11a9012fcf79f4066947b0b2801c64d053f38d42\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "f1837f87275147f6bf8c277445367b9d5a9c805d", "tree": "30f56073a5b481254e2c6029deb2940e262e8748", "parents": [ "d606e7485b57f2e2dac769e3dfcb651840e4024b" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Feb 08 11:51:46 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Mar 18 14:23:35 2019 +0000" }, "message": "Remove manual tests from tests-standard.mk\n\nThese tests require build variables to be set to non-default values\n(USE_NVM\u003d1 and NEW_TEST_SESSION\u003d0). This conflicts with other tests that\nare part of tests-standard (the default set of tests) and so the\nproposed solution is to remove them from this set.\n\nChange-Id: Id54148aab9410002dace33ad595ac1b0cf4678ca\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "9c9f92c4c4cd07ea75ea72a42f15b32ed4c01bf0", "tree": "50e83b79b1c811db525e3c2e64b99951a59fed4e", "parents": [ "4ac64eb32c8fcb3a00aecda6c943768505e3282a" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Mar 13 13:57:39 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Mar 13 13:57:39 2019 +0000" }, "message": "Add ARMv8.3 pointer authentication support\n\nARMv8.3-PAuth adds functionality that supports address authentication of\nthe contents of a register before that register is used as the target of\nan indirect branch, or as a load.\n\nThis feature is supported only in AArch64 state.\n\nThis feature is mandatory in ARMv8.3 implementations.\n\nThis patch adds the functionality needed for platforms to provide\nauthentication keys for the TF-A Test Framework, and a new option\n(ENABLE_PAUTH) to enable pointer authentication in the framework itself.\nThis option is disabled by default.\n\nPointer authentication support has been added to FVP.\n\nChange-Id: Id2d5c978deb68ae60107879f1c3d0b231cba9f42\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "4ac64eb32c8fcb3a00aecda6c943768505e3282a", "tree": "0776c82d8df17eeb715a090cde8e3654ab94909a", "parents": [ "d606e7485b57f2e2dac769e3dfcb651840e4024b" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Feb 06 13:05:18 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Mar 13 13:54:57 2019 +0000" }, "message": "Remove pointer authentication test\n\nThis test only makes sure that the pointer authentication registers can\nbe read, which isn\u0027t a useful test now that the TFTF is going to support\nusing pointer authentication.\n\nChange-Id: I01735677353ab08ba26f6faad1b900d98654c0d2\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "d606e7485b57f2e2dac769e3dfcb651840e4024b", "tree": "0f4d5283328145817e1e99139a1eed23aad01417", "parents": [ "673285d0c59455887215c8686ab43d9688cca7e8", "3ddff339574682c1f6727e2fc0d130ad66d717d2" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Mar 05 09:49:15 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 05 09:49:15 2019 +0000" }, "message": "Merge \"el3_payload: Add initial platform support for RD-N1-Edge\"" }, { "commit": "673285d0c59455887215c8686ab43d9688cca7e8", "tree": "b3610f5e6d4fded56d2cc6532affe63cd2faa60a", "parents": [ "426cbb2cc56b3a2b129ac7386b96bb325c577f1a" ], "author": { "name": "Chandni Cherukuri", "email": "chandni.cherukuri@arm.com", "time": "Tue Jan 08 11:47:17 2019 +0530" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Mar 05 08:32:14 2019 +0000" }, "message": "readme: Add support for RD-N1-Edge platform in readme.rst\n\nFVP_RD_N1Edge is the Fixed Virtual Platform on which the\nTrusted Firmware-A Tests are executed for RD-N1-Edge\n\nChange-Id: If6ffaa5430b9d41caf6d0697896bc92114e9a87c\nSigned-off-by: Chandni Cherukuri \u003cchandni.cherukuri@arm.com\u003e\n" }, { "commit": "426cbb2cc56b3a2b129ac7386b96bb325c577f1a", "tree": "7ef584d0d5bade2d74aad33061521e26ec30534b", "parents": [ "d6e806d35599bf003c575d7d113367b8de910448", "33f1774a7d1c74bbe29d9c18fb06d2efdea758db" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Mar 05 08:28:10 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 05 08:28:10 2019 +0000" }, "message": "Merge \"plat/arm/rdinfra: Add initial platform support for RD-N1-Edge\"" }, { "commit": "d6e806d35599bf003c575d7d113367b8de910448", "tree": "cd4ccb353ae8b91e6504057c20eaf641cd13ab63", "parents": [ "602b7f58dd7668411c8a4032652b4552bd7fe934" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 14:34:26 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Mar 04 12:20:48 2019 +0000" }, "message": "libc: Update makefiles\n\nAdded includes and sources of libc to the makefiles.\n\nChange-Id: I8e84db9634e0df7d51caa5c5858311672dd3a8d1\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "602b7f58dd7668411c8a4032652b4552bd7fe934", "tree": "675e0939d19e306e01703359d7b8661d4f312d32", "parents": [ "8a573de8dda42258b747e56f19190311ea090d29" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 14:13:43 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Mar 04 12:20:38 2019 +0000" }, "message": "libc: Update includes\n\nReflect the changes in the structure of libc.\n\nNB: the include of stdarg.h in nvm_results_helpers.c is not in alphabetical\norder because it needs to be included before stdio.h. Fixing this would require\nfurther changes.\n\nChange-Id: I07f62a3450802833408ff3e1f950fd3b643e5e33\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "8a573de8dda42258b747e56f19190311ea090d29", "tree": "f1243b67c7cdecaa271e0d137c20788b01b1c237", "parents": [ "892ce40b6fe172a76d3bf88bf5de0a441dc48734" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 13:54:30 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Mar 04 12:19:43 2019 +0000" }, "message": "libc: Adapt to TFTF\n\nAdd support for functions used in TFTF but not in TF-A.\n\nReplaced calls to plat_panic_handler with calls to panic, since there is no\nimplementation of the former in TFTF.\n\nChange-Id: Ic10de2c6e749db97b932cd7ffbb6067b5befe914\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "892ce40b6fe172a76d3bf88bf5de0a441dc48734", "tree": "b3f39b7552d1eee41e2344124e843285b5d1b187", "parents": [ "4128f9f887ed0ef0c511d2299c75ca71335b3cf1" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 13:42:38 2019 +0000" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Mar 04 11:17:40 2019 +0000" }, "message": "libc: Delete stdlib files\n\nKeep uuid, rand and strncpy for compatibility reasons\n\nChange-Id: Iefd82a5c9df48f6159732027e40a58f7d6afc09f\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "4128f9f887ed0ef0c511d2299c75ca71335b3cf1", "tree": "9c1624075ae2a7af810df40d527d46195d55ee26", "parents": [ "2eafdf2c74cf00b9bc3dbeccac794a433acc0c16" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 13:34:41 2019 +0000" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Mar 04 11:17:40 2019 +0000" }, "message": "libc: Import from TF-A\n\nBased on arm-trusted-firware commit 873e394b3bf93214a441f9f98237b58fbbea55aa\n\nChange-Id: I510e092f2b9ff333e9461bdde8d80ed1fab1460c\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "3ddff339574682c1f6727e2fc0d130ad66d717d2", "tree": "0e86bb94df8d6b904991df19523509690a6bbe1d", "parents": [ "33f1774a7d1c74bbe29d9c18fb06d2efdea758db" ], "author": { "name": "Chandni Cherukuri", "email": "chandni.cherukuri@arm.com", "time": "Mon Jan 07 14:19:40 2019 +0530" }, "committer": { "name": "Chandni Cherukuri", "email": "chandni.cherukuri@arm.com", "time": "Wed Feb 27 14:50:16 2019 +0530" }, "message": "el3_payload: Add initial platform support for RD-N1-Edge\n\nRD-N1-Edge platform consists of two clusters of four CPUs\neach. CPU0 of the first cluster is the primary CPU. SoC UART0 is\nused for the console log.\n\nChange-Id: I724c772f95d590154536e7bc1544976e55b983cf\nSigned-off-by: Chandni Cherukuri \u003cchandni.cherukuri@arm.com\u003e\n" }, { "commit": "33f1774a7d1c74bbe29d9c18fb06d2efdea758db", "tree": "03c904a233b48adbf42652664a49beff848f5422", "parents": [ "2eafdf2c74cf00b9bc3dbeccac794a433acc0c16" ], "author": { "name": "Chandni Cherukuri", "email": "chandni.cherukuri@arm.com", "time": "Mon Jan 07 14:17:52 2019 +0530" }, "committer": { "name": "Chandni Cherukuri", "email": "chandni.cherukuri@arm.com", "time": "Wed Feb 27 14:50:02 2019 +0530" }, "message": "plat/arm/rdinfra: Add initial platform support for RD-N1-Edge\n\nRD-N1-Edge platform consists of two clusters of four CPU\u0027s\neach. The FVP for this platform does not support system suspend and\nresume functionality as there is no wakeup source supported. So all\nthe system suspend and resume related tests are skipped.\n\nChange-Id: I33649c7c67023127e736c760bf0ec4193c95ed1a\nSigned-off-by: Chandni Cherukuri \u003cchandni.cherukuri@arm.com\u003e\n" }, { "commit": "2eafdf2c74cf00b9bc3dbeccac794a433acc0c16", "tree": "75f100cd27664c04cb24c544aab1115c042e65b6", "parents": [ "ae2fe05479ffd533517bbf4f3da429a50bce7e59" ], "author": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Mon Feb 25 15:31:35 2019 +0000" }, "committer": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Mon Feb 25 15:48:16 2019 +0000" }, "message": "Fix header paths\n\nChange-Id: Iee1998b9b039dfd21a3ef38c5afeae3fc65569c2\nSigned-off-by: John Tsichritzis \u003cjohn.tsichritzis@arm.com\u003e\n" }, { "commit": "ae2fe05479ffd533517bbf4f3da429a50bce7e59", "tree": "91df49544f9545f489c97140e1eaf9b92a6a4084", "parents": [ "ffdfd16fd8cdedeec558749a416759cc58208b37", "af6a4db5fe93ac5e5adea401b3a9e52f25dcbbe3" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Feb 12 08:26:30 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 12 08:26:30 2019 +0000" }, "message": "Merge \"Update user guide on manual tests\"" }, { "commit": "ffdfd16fd8cdedeec558749a416759cc58208b37", "tree": "723e7d461bd8d164d2ad708c054fb63f44c1eeb7", "parents": [ "418ca0c3505885eeca960fdf91f51cdd507c8764" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Mon Feb 11 15:34:32 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Mon Feb 11 15:34:32 2019 +0000" }, "message": "Synchronize files with TF-A repository\n\nChange-Id: Ieb56d0639efd29c2695751b2b36cc98ce2c90dab\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "af6a4db5fe93ac5e5adea401b3a9e52f25dcbbe3", "tree": "b113904b6a45cc2cf6a90f007198a05b09185afb", "parents": [ "418ca0c3505885eeca960fdf91f51cdd507c8764" ], "author": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Fri Feb 08 14:33:52 2019 +0000" }, "committer": { "name": "Joel Hutton", "email": "joel.hutton@arm.com", "time": "Fri Feb 08 15:22:54 2019 +0000" }, "message": "Update user guide on manual tests\n\nManual tests now rely on passing a flag to dump the flash to a file,\nthen passing that flash file back in when relaunching the model to\ncontinue the tests.\n\nChange-Id: I77d226b9a1d50f16fd3b13e1254f5152293b23bf\nSigned-off-by: Joel Hutton \u003cJoel.Hutton@Arm.com\u003e\n" }, { "commit": "418ca0c3505885eeca960fdf91f51cdd507c8764", "tree": "8bb97e5e4002688ed97d1528c09f6af9adad0562", "parents": [ "6d7047dcb24325e0a782b47c0ad507b6a5b32746" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Jan 30 16:07:36 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Jan 30 16:07:36 2019 +0000" }, "message": "Remove SMCCC 2.0 support\n\nSMCCC v2.0 is no longer required for SPM, and won\u0027t be needed in the\nfuture.\n\nThe SPM implementation based on SPCI and SPRT was using it, but it has\nbeen adapted to SMCCC v1.0.\n\nChange-Id: I624b32f9547274b50add4ea81b485cc9f5121e53\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "6d7047dcb24325e0a782b47c0ad507b6a5b32746", "tree": "7e8496ca50786a6f38e42a9d00c944c73738f1b7", "parents": [ "09a00ef98c6108fec75dafcc7dbdddacb2ee2e91", "a43b003acd6c8e8991a57e993f7bfcdfaa04f980" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 28 07:40:15 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 28 07:40:15 2019 +0000" }, "message": "Merge changes from topic \"sb/exception-dump\"\n\n* changes:\n Dump some registers when hitting an unexpected exception\n Improve readability of TFTF exceptions code\n" }, { "commit": "09a00ef98c6108fec75dafcc7dbdddacb2ee2e91", "tree": "77b585708a4fd850f0dac3a3f0fcaf34576fa8c9", "parents": [ "9e550b6f75f064b53d74a4ad3c8672332d87451c" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Jan 11 13:12:58 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 25 08:23:20 2019 +0000" }, "message": "Sanitise includes of include/drivers across codebase\n\nEnforce full include path for includes.\n\nThe reason for this change is that having a global namespace for\nincludes isn\u0027t a good idea. It defeats one of the advantages of having\nfolders and it introduces problems that are sometimes subtle (because\nyou may not know the header you are actually including if there are two\nof them with the same name).\n\nChange-Id: I45e912b16c9fff81f50840dad7e7f90ed6637b2a\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "a43b003acd6c8e8991a57e993f7bfcdfaa04f980", "tree": "52e7bbdc784f3fcd6cf629d76b21b692acca1652", "parents": [ "e760449e0759d351b849c5934cfa2ee06bde89a7" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 14:04:32 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jan 24 08:59:54 2019 +0100" }, "message": "Dump some registers when hitting an unexpected exception\n\nAt the moment, no information is printed on the UART whenever we hit\nan unexpected exception, not even an error message. This is not great\nfrom the user\u0027s perspective, who has got no idea of what is going on.\n\nNow we print an error message, as well as the state of some of the\nregisters. This includes general-purpose registers, as well as some\nsystem registers.\n\nThis is implemented for TFTF running:\n\n- in AArch64 state, at EL2;\n- in AArch64 state, at NS-EL1;\n- in AArch32 state.\n\nWe might want to dump more registers in the future but this patch\nat least provides a basis we can build upon.\n\nAlso, the SP_EL0 has been removed from the list of registers saved in\nthe CPU context because TFTF always uses SP_ELx and does not touch\nSP_EL0 at all.\n\nChange-Id: I56e4afa917b53b5ccccff1d5d09ac8ccfaa6ae49\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "e760449e0759d351b849c5934cfa2ee06bde89a7", "tree": "52d0550dfa247e432bff782182544bae38f5afbd", "parents": [ "9e550b6f75f064b53d74a4ad3c8672332d87451c" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 09:37:28 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jan 24 08:59:54 2019 +0100" }, "message": "Improve readability of TFTF exceptions code\n\nThe only exceptions that TFTF expects are IRQs from the current\nexception level. All other exceptions are unhandled and put the TFTF\ninto an irrecoverable state. Introduce an unhandled_exception macro\nthat makes it clearer.\n\nChange-Id: Ia64600d540007a648c14d8663c91c60c8591eae6\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "9e550b6f75f064b53d74a4ad3c8672332d87451c", "tree": "80206b2fe2b493ea3786dfbb783bbafbf03e17d0", "parents": [ "971545c399ec0e79718132bcf7883111842b76e8", "e223699220a568c30f4926282b31a87d0b424270" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jan 23 08:46:43 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 23 08:46:43 2019 +0000" }, "message": "Merge changes from topic \"jh/hikey960\"\n\n* changes:\n hikey960: Fake only 1 core\n hikey960: Enable SGI\n hikey960: Enable MMU\n Hikey960 port: initial commit\n" }, { "commit": "971545c399ec0e79718132bcf7883111842b76e8", "tree": "17ac6b0b6ca0b221a0bedfbac8066c2a9570f6e6", "parents": [ "a2d516fc5215973b4df38fe072fb68a8899e4ae4" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 18 13:30:29 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 18 14:32:47 2019 +0100" }, "message": "Use lock-less printf() in assert macro\n\nThis allows to use assertions in interrupt context (which we do in\nsome places currently). Before this patch, a CPU could dead lock\nitself by:\n\n1. acquiring the printf lock in the normal execution context;\n2. taking an interrupt while still holding the lock;\n3. inside the interrupt handler, executing an assertion check that\n fails and thus tries to print an error message on the UART.\n\nIn a situation where several CPUs might be executing assert() at the\nsame time, we will now get interleaved messages but that should be\npretty rare.\n\nChange-Id: I6d1603300f6a3ea5756a46338cb950b7ca3e7956\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "a2d516fc5215973b4df38fe072fb68a8899e4ae4", "tree": "18da625a1492e7d41a1dc89fab61e50d884354b9", "parents": [ "c1617386e332973c334b097ad7e188437ef8e1a7" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 16:34:19 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 16:40:07 2019 +0100" }, "message": "Always print file and line number in panic/unreachable macros\n\nRelease builds used to have a special variant of these macros without\nthe source code location information. This kind of mechanism is useful\nwhen writing software that needs both a development and production\nversion so that the source code information is not leaked when the\ndevice is in the field.\n\nHowever, in the context of TF-A Tests, it makes little sense, as it\u0027s\nunlikely somebody would ever ship a device with TF-A Tests installed\non it.\n\nChange-Id: Ic14ad87c2756762807ee71142f21d6973233144e\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "c1617386e332973c334b097ad7e188437ef8e1a7", "tree": "e1c0c7eaa58f802523f21037db0750d28d55a628", "parents": [ "3951dd9009a5bc3c5552dcc8dddcd80653ac8613", "d101967f4f9c36d18ee04bd8d9b735dc47a4fcda" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 11:56:16 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 15 11:56:16 2019 +0000" }, "message": "Merge changes from topic \"sb/exceptions\"\n\n* changes:\n Rework IRQ vector code\n Add CFI debug info to vector entries\n Improve readability of exceptions stubs code\n Fix comments in AArch64 exceptions code\n" }, { "commit": "3951dd9009a5bc3c5552dcc8dddcd80653ac8613", "tree": "94263ebf055db8a18c9cdaef293ee86888be54cb", "parents": [ "a17e77c53ba160e0394c331e6c37a4f3b271a78b" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jan 10 11:09:54 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 10:48:49 2019 +0100" }, "message": "Move unstable tests to a separate pool of tests\n\nSome tests have proven unreliable over time. They often time out and the\nroot cause of the problem is unknown as of today.\n\nThis root cause needs to be investigated and fixed but until then, this\npatch isolates these tests in their own pool. This allows us to set\ndifferent trust levels in our CI:\n - The stable tests are trusted to call out the validity of a patch.\n - The unstable tests are only informative.\n\nChange-Id: Ia8ebb5a29a523ef3a1f324dbd3ddddac02254fd8\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "d101967f4f9c36d18ee04bd8d9b735dc47a4fcda", "tree": "50d51deaa8b32f96037fd6e07e2db3732757be81", "parents": [ "452f360545f0b4d19720c2dfbaf80cf48c1aa3de" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 11 18:39:24 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 16:48:28 2019 +0100" }, "message": "Rework IRQ vector code\n\nJump straight to a function so that we are not constrained in the\n32-instruction limit. Turn the code saving and restoring\ngeneral-purpose registers into a macro (as opposed to a function),\nthus removing the need to save the link register before anything else.\n\nOverall, this makes the code more straight-forward as we can more\nclearly see that registers are saved from x0 to x30 (in this order)\nwithout any magic twist.\n\nChange-Id: Ic70ceee62bec5efc6f6b6a23a7bd4c1d6c2f8a97\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" } ], "next": "452f360545f0b4d19720c2dfbaf80cf48c1aa3de" }