)]}' { "log": [ { "commit": "5ab09e8174e1ec17d6b1c35483f268e0775a5b67", "tree": "3be81b31149a1c413293061bd39d41c94d2416e6", "parents": [ "060efe97ff6c31b7dbec96af9fde0b169db4183d", "089c9ad705c1f393d95dd911c76a6772af45d1fd" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "message": "Merge changes from topic \"hm/handoff-mb\"\n\n* changes:\n feat(handoff): add event log test\n feat(measured-boot): add measured boot drivers\n" }, { "commit": "b674809e4d937d44f85ef53aa2bdbb9f74b569b2", "tree": "3192a0624448d4503cb3679f0d939cb7c169ac22", "parents": [ "19620adc7cbcae26cc432a28a9c3b0944957cf13" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:03 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:25 2025 +0000" }, "message": "feat(measured-boot): add measured boot drivers\n\nIntroduces core measured boot support, including TPM event log handling,\nhashing infrastructure, and event formatting per TCG spec. The driver is\nimported from the existing implementation in TF-A.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: Ib2e6a88c86f110f9a6907c3e6dbb0dc736486de9\n" }, { "commit": "2230a5955d328b4a018e72163482690892f5ff59", "tree": "7ac3698bb9d614af35f74999fc42f4ffee5d7ee3", "parents": [ "37e3f3e1d237b6e8289fbc0a090b2b4dd2d4b9ec" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 17:19:34 2025 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 17:30:44 2025 +0000" }, "message": "feat(ras): add RAS system registers access test\n\nFEAT_RAS introduces EL1 system registers to query error records, those\nCPU specific parts of the RAS extension can be accessed independently of\nany FFH/KFH handling setup or any system specific RAS implementation.\n\nAdd a test to verify that those registers can be read, when the CPUID\nfield advertises the MPAM (CPU) extension.\n\nChange-Id: I7429fc815e7e0ee0cd736603966969b2cfb5f469\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "82cd82e9868b1f381a5c8d84195657e1583cfca1", "tree": "c7be244d493e784e55df370f501d8c3ba9275523", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jan 17 17:37:42 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Feb 04 15:01:14 2025 +0000" }, "message": "feat(rme): add tests for FEAT_MPAM on Realms\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6e138cbf121793bdaaa3a44824c0dbff74daced1\n" }, { "commit": "7b7ca22f1b54632558663f5816d103105ce3aaec", "tree": "e3a9111c51ba449327eeeecbb638f03b5dab3cc6", "parents": [ "566f07da79dc559c405e79327be47740b7a66686" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 13:33:18 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "test(SMCCC): test SMCCC_ARCH_FEATURE_AVAILABILITY\n\nThis test calls the function with each valid argument and checks that\nevery bit is set if its relevant feature is present in the system. It\nalso fails the test if any set bit in the return value has not been\nchecked. This should serve as a reminder to update this test for every\nnew feature that is implemented.\n\nOnly feature that tfa supports are tested with the expectation that new\nones will be added in the future.\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I801326a49810bb76bfc3b9d06780d416dcc32a40\n" }, { "commit": "566f07da79dc559c405e79327be47740b7a66686", "tree": "02ce87e53805217055fd73771267ba2f8f9edac0", "parents": [ "4e282424143dbd73cd0248d470d03cccb9005f42" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 13:31:48 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "refactor(SMCCC): use a macro to check for the SMCCC version\n\nThis is similar to other macros that skip the test if a condition is failed.\n\nChange-Id: If8ff8b29473151edf1872636bce9ee0950851c42\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "4e282424143dbd73cd0248d470d03cccb9005f42", "tree": "b5da9ecc48fe84d374c9e04de6a0d3e2c7f8aa0d", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 14:34:13 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:16 2025 +0000" }, "message": "feat: add register definitions needed for SMCCC_ARCH_FEATURE_AVAILABILITY\n\nAlso slightly optimised some redundant feature functions\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I6dcc11060a2f3697a8aa41443e9cfc665b2b7c74\n" }, { "commit": "d1a7f4d2bd6b4867a71366b58b00759724ef99d1", "tree": "7439900358c0026fe7c781e725e6ba0b1c3fd37b", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Tue Nov 26 12:50:47 2024 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 19 14:51:47 2024 +0000" }, "message": "feat: add tests to check SCTLR2, THE and D128 sysregs\n\nThis patch adds test cases for verifying that the system registers of\nFEAT_SCTLR2, FEAT_THE and FEAT_D128 (FEAT_SYSREG128) are working\ncorrectly by performing a series of reads and writes to the registers.\n\nChange-Id: I5c102daa358a7ec5d1801395bc875e9850e83939\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "1ab21e5e0f05680e5a30093fe6a7eff99fdcb150", "tree": "17c76bf9488a15d760977c0631fd35ef733554a1", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Nov 12 10:52:08 2024 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Nov 19 15:16:35 2024 -0600" }, "message": "feat(fpmr): test FPMR register access\n\nChange-Id: I326690564d01596fb4f4b449f4f314699ccfe3c4\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "7c78f7b4a74e58512ff6998f7a5438520e58c343", "tree": "ea7bd3a6363d1bf5686e5cfbd2a92cabec7a3df6", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Oct 25 11:44:32 2024 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Nov 19 10:10:16 2024 +0000" }, "message": "feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n\nWhen FEAT_DoubleFault2 is supported, TF-RMM must take into\naccount bit SCTLR2_EL1.EASE in order to decide whether to inject\na SEA into the sync exception vector or into the serror one.\n\nThe test on this patch verifies that TF-RMM injects the SEA\nto the right vector depending on SCTLR2.EASE bit.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c976fecb04d123e3efb96c5973b1466e241097f\n" }, { "commit": "72b7ce11edd6042d5a3fe75bba83fb5e7f58ee08", "tree": "6fba961e72767d7a0c58b914acc24723190802a3", "parents": [ "a62262f047c9c48c65021f4e23be7b709e8c2811" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Nov 04 13:44:39 2024 +0000" }, "committer": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Wed Nov 06 21:46:35 2024 +0100" }, "message": "feat(ls64): add LS64_ACCDATA test\n\nFEAT_LS64_ACCDATA introduces the system register ACCDATA_EL1, its value\nreplacing the first four bytes of the data provided to an ST64BV0\ninstruction. As this system register would need context switching\nbetween non-secure and secure worlds, there is an SCR_EL3 bit to allow\ntrapping accesses from lower ELs into EL3.\n\nIntroduce a check to verify that accesses to this system register do not\ntrap into EL3, if the CPUID registers advertise this feature.\nBits[63:32] of ACCDATA_EL1 are described as RES0, so mask those bits\nwhen comparing the read-back values with the written one.\n\nChange-Id: Ia32bcf7187356c701470a1757708b3d554e88629\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "8191621885dfc65789a19ef0eb590b8639ed87d1", "tree": "8fbbf09517a4e7de5976e8912a594be10cfb1f04", "parents": [ "0145ec3459750f35a6546b3f015906356b7dc6cd" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Aug 15 15:08:23 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 09:07:55 2024 -0500" }, "message": "feat: test if errata 2938996 and 2726228 workaround is applied\n\nThis patch confirms if access to trbe el1 register generates an undef\ninjection in affected cores. If a core is affected by errata 2938996/\n2726228 and it generates an undef injection on access to trbe el1 register then\nthe test passes. If it is an unaffected core then the test passes , but\nwhen undef injection doesn\u0027t happen in affected core, the test fails.\n\nChange-Id: I515a9aa4613c6d99ee73e579206089ebf89ffae8\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "3d88db7691467351726d05b20d629b94c1fb1b59", "tree": "10f847b91327aae17ae91a2d6a5342b0a1575e03", "parents": [ "b1ab5854ad384dd1e3abbe760a6b35d6cae9a0bc", "94963d4e739f3fb1accefddd4105cf9140989889" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 24 17:26:44 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 24 17:26:44 2024 +0200" }, "message": "Merge \"feat(fgt): add support for FEAT_FGT2 testing\"" }, { "commit": "cd6c94b20e7450e27254856a82008ca0595d84d1", "tree": "6a8146d2ef87f4c5a0f72f84b850e1577c57a4a4", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Feb 15 17:19:05 2022 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jul 23 14:06:14 2024 +0100" }, "message": "feat(ls64): add a test for 64byte loads/stores instructions\n\nThis patch adds a test to verify the 64 byte load and store\ninstructions introduced by FEAT_LS64.\nThe test primarily executes instructions:\n1. LD64B\n2. ST64B\nand ensures that the NS-EL2 has no dependency on EL3 while\nrunning them.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I7a4ca0ee4a2c18bf0de030c72e35eb218bc6364c\n" }, { "commit": "94963d4e739f3fb1accefddd4105cf9140989889", "tree": "904e5a3428384fae10f4cae54fd91589fc47da8c", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jun 13 17:19:56 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Mon Jul 22 16:21:01 2024 -0500" }, "message": "feat(fgt): add support for FEAT_FGT2 testing\n\nThis patch adds testcase that validates FEAT_FGT2 support\nby reading Fine-grained trap registers that are part of FEAT_FGT2.\nThese registers are only present when FEAT_FGT2 is implemented\n\nChange-Id: Ifc1106d12dbe03b956310d364600368d3f035491\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "2f2c959871723c303a833778271cd923910deaca", "tree": "a3b777765c3959ea183de411cbe73d18e45578b1", "parents": [ "b5103df4af352c9409fb0756579788d6c0732b87" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jun 06 16:34:28 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Jun 28 14:55:27 2024 -0500" }, "message": "feat(debugv8p9): test if EL3 has properly enabled FEAT_Debugv8p9\n\nWhen FEAT_Debugv8p9 is not enabled, access to MDSELR_EL1\ntraps to EL3. Access to FEAT_DEBUGV8P9 control registers\nmust be explicitly enabled in EL3,\n\nThis testcase uses this behavior to test if\nFEAT_Debugv8p9 is enabled or not.\n\nChange-Id: I2f9a0158e9f38eaffac2e27c40d44d3c520d508d\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "0945e23153c06ed196756ac094c81ab8627d9a95", "tree": "7bc1e57bb77a4cf09cf18b75974e18e60711da53", "parents": [ "8f6b131f44bf5355d07b274f6a43490f968590b2", "16de81046dbffdfc19ca4a30524f170860eac178" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jan 31 08:48:35 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 31 08:48:35 2024 +0100" }, "message": "Merge \"test(fvp): Test trusted key certificate corruption\"" }, { "commit": "16de81046dbffdfc19ca4a30524f170860eac178", "tree": "d70655f6090cd2e8befdae3a8270682f19f551ba", "parents": [ "84ad6157a4e83834fa925b80534ca5414c368586" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Fri Aug 18 08:50:30 2023 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Mon Jan 29 13:10:08 2024 -0600" }, "message": "test(fvp): Test trusted key certificate corruption\n\nThis also includes a test framework for use with corrupting the\nroot of trust private key certificate in the boot FIP, found\nusing its UUID.\n\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\nChange-Id: I988c517637edcf6fdcaf271628eb650781c276f8\n" }, { "commit": "13887ac63d4186a851ae2a916c112cb6229c6e63", "tree": "e49867e623b38a26d977d84b2a21b1f382f523cf", "parents": [ "ea94738603d09be1399337f0976f89f951c35e6a" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jan 04 15:22:52 2024 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Jan 16 12:43:23 2024 -0600" }, "message": "feat(mpam): add MPAM system registers access test\n\nAdded a test which reads MPAM system registers to ensure that\nEL3 is giving permission to Non-secure EL2 to access these registers.\n\nChange-Id: Ie701a19c9682df6d6aeaec086954e275afff1843\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "40de8ec10f4d9925c24d2b9dd22822e0c8fd4224", "tree": "30347a76b3f2429f8ab3d0f124526d860ee77503", "parents": [ "6bb95105b289a4d9015d74af7cb7254455b2344e" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Oct 12 21:45:12 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "feat(rmm-eac5): update RSI_VERSION, RMI_VERSION\n\nThis patch adds necessary support for RMI_VERSION\nand RSI_VERSION commands.\nMacro SMC_RSI_ABI_VERSION renamed to SMC_RSI_VERSION.\n\nNote.\nThis patch sets both RSI and RMI version numbers to\n1.0 as per RMM Specification 1.0-eac5.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If4eb14d93f657388e2fe64ceefee002403cc4ae8\n" }, { "commit": "82bf339c9e178e8200f763146f2f21abee9410ea", "tree": "d37718c9f321f866fbe0480ea758fb5175a5c032", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jul 28 18:32:27 2023 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Mon Jul 31 16:59:23 2023 +0100" }, "message": "fix(spm): stop spm from being built for in aarch32\n\nHafnium does not support Aarch32 therefore we do not want to build\nin this case. Move spm related test helpers into their own file\nand add FF-A tests to the aarch32_tests_to_skip.txt file\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ic5a83ddf4aae2b7dd4b1c30e4cc76b0447e5b405\n" }, { "commit": "4b22111264f612da90789dc207d2c874817d9291", "tree": "bebdd61a896deb479ef7598e9fc8f2f0f3615071", "parents": [ "2a856b5f0b1e9b9183292fb44d3def6fdd69ee7c" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 05 14:19:03 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Fri Apr 28 11:40:15 2023 +0100" }, "message": "refactor(rme): add helper macro for RME tests\n\nThis change adds SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP macro that\nchecks if FEAT_RME is present and RMM is not TRP.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I100e713d8f4fce2826e60909580079834585fddb\n" }, { "commit": "95d5d2764c2f44b06af709dd093e9ff0f17ced14", "tree": "b0d3d8d67c94521b107522dac8631e13bc90b9f8", "parents": [ "b3ffd3c17ea83c48a90d7165ab5c5140540bc81f" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Jan 16 17:58:47 2023 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Apr 28 00:51:01 2023 +0100" }, "message": "feat(sme): add basic SME2 tests\n\nFEAT_SME2 introduces an architectural register ZT0 to support\nlookup table feature. This patch ensures that EL3 has\nproperly enabled the SME2 for use at lower exception levels,\nthereby disabling the traps execution at lower exception levels,\nwhen instructions access ZT0 register to EL3.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I46d51184b74c1e82c88344530601f2a3c1aee8ea\n" }, { "commit": "b3ffd3c17ea83c48a90d7165ab5c5140540bc81f", "tree": "ae9e356822c85c2d410e761150dcc5fdce6ddb09", "parents": [ "d6325a6dee06c281d90e875bc5df2ca4fba9d7f5" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Feb 13 12:15:11 2023 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Apr 28 00:50:50 2023 +0100" }, "message": "feat(sme): update sme/mortlach tests\n\nFEAT_SME is an optional architectural extension from v9.2.\nPreviously due to the lack of support in toolchain, testing\nSME instructions were overlooked and minimal tests were added.\n\nThis patch addresses them, with additional tests to test\nthe SME instructions. In order to avoid toolchain requirements\nwe manually encode the instructions for accessing ZA array.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: Ia9edd2711d548757b96495498bf9d47b9db68a09\n" }, { "commit": "2f30f1030f186760b20cd06b59832e332b2bdd0a", "tree": "e06899ba1be405650b4a15603429900dac67ccc2", "parents": [ "2eb601b98a245df8a31e670a7dc322c2e8f153cf" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Mar 13 19:37:46 2023 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Mar 31 11:41:56 2023 +0200" }, "message": "feat(rme): add PMU Realm tests\n\nThis patch adds Realm PMU payload tests with\nPMU interrupt handling.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2\n" }, { "commit": "08b78604af08378bfa587eaeaf7092770bf9c20d", "tree": "5ca074e6b99e3e908e241a4fc23c78800914a318", "parents": [ "d17c6113997733fb39606aa3c3643896248ac44d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jan 24 15:54:50 2023 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 26 10:44:54 2023 +0000" }, "message": "fix(ff-a): tftf handling of its RXTX buffer pair\n\nThe way tftf was handling the RXTX buffer pair created a dependency\non a set of tests from \u0027test_ffa_setup_and_discovery.c\u0027. This was\nproblematic for test configurations for which the SPM tests are\nnot present.\n\nThis patch removes such dependency:\n- Delete the \u0027INIT_MAILBOX\u0027 macro, and \u0027init_mailbox\u0027 function;\n- RXTX buffer pair allocated within the \u0027get_tftf_mailbox\u0027.\nThey are mapped into the SPMC via FFA_RXTX_MAP, and are returned\nin the function\u0027s argument.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ia010ebd21f11ab7ca6582b574ffc9179693b1eed\n" }, { "commit": "35e3ca03ea641e61bb9e8dafc25fcb2d577c6ac8", "tree": "ec0ce15d0f947ca27bda67f5c8dd0e170569597d", "parents": [ "ba3f3f37a6a8952e416eaf2726f771fe794dceaf" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 10 16:39:45 2022 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Dec 06 16:08:17 2022 +0000" }, "message": "test(pmu): check if PMUv3 is functional\n\nThe PMU is tested for secure world leakage but there are no checks\nwhether it works in the first place.\n\nThe counter and event counters are exercised separately. This is because\nthe functionality of one does not imply the functionality of the other\n(EL3 has separate controls for both). This additionally catches a corner\ncase with FEAT_HPMN0 missing without failing all tests.\n\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I966d3155cdd6edfde01af32f7c50c3bb3644274a\n" }, { "commit": "002e569021f2e219456d02dfe239218eba5c7cfa", "tree": "4c2ea2d7cce38d168ce5e03849498161d537f1c2", "parents": [ "0fcfd47a5936180b754819ee928e8d5af173c5d2" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Mon Oct 10 12:36:46 2022 +0100" }, "committer": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Tue Nov 08 16:34:01 2022 +0000" }, "message": "feat: tftf realm extension\n\nThis patch adds Realm payload management capabilities to TFTF\nto act as a NS Host, it includes creation and destruction of a Realm,\nmapping of protected data and creation of all needed RTT levels,\nsharing of NS memory buffer from Host to Realm by mapping of\nunprotected IPA, create REC and auxiliary granules, exit Realm\nusing RSI_HOST_CALL ABI.\n\nOlder realm_payload name is used now for only R-EL1 test cases,\nRMI and SPM test cases have been moved to new file tests-rmi-spm.\n\nNew TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk,\nas an offset from where R-EL1 payload memory resources start.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7\n" }, { "commit": "889037307cd441431e448c752ad4fe0cebe8939b", "tree": "fc532db7e1e3ddae86c94b949d25022773e67bf6", "parents": [ "c19d208327f2ca05d261f8d2c4a40889eb2ffd33" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Sep 01 16:48:01 2022 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Oct 04 15:01:19 2022 -0500" }, "message": "fix(interrupts): dont enable virtual maintenance interrupts\n\nSPMC enables the following virtual maintenance interrupts by default\nfor each Secure Partition:\n \u003e MANAGED_EXIT_INTERRUPT_ID\n \u003e NOTIFICATION_PENDING_INTERRUPT_INTID\n\nHence, no need to send a request to SPs to enable them.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I7fc605b9b78ad759728909cd28ad2d2083c5de54\n" }, { "commit": "9303f4d1c196a1a193e6c49d19edaff41bb71bfd", "tree": "52dc8e057caa71e975e75150cba14107fb480570", "parents": [ "f70e2912afc18f4f8e6697e36c2d9e9b7341ac5b" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Jul 25 16:38:01 2022 -0400" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Tue Aug 16 14:47:58 2022 -0400" }, "message": "feat(rng_trap): add tests for FEAT_RNG_TRAP\n\nAdded 2 tests that expect a trap to be triggered when a read is\nperformed on:\n1. RNDR register\n2. RNDRRS register\nThe result will be a panic signal and the whole system will halt,\nas there is no handler set for such trap.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ia979e60a106b394cc09dfdf94115354fb72142d1\n" }, { "commit": "9ea16641579ee5b9b0e62ce56c52e7cc6b4ab4f3", "tree": "270c329d0258608e81b403ec34f76afe080df2ad", "parents": [ "e9a1d61bd0ea73bc9cf7cfe5f1a7ea8f92ff54af" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Tue Mar 01 19:39:59 2022 +0000" }, "committer": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Thu Jul 07 16:25:12 2022 +0100" }, "message": "feat(tftf): refactoring of some tftf function helpers\n\nThis refactoring is introduced in order to reuse some useful\nfunction helpers which already exist in the code base,\nby moving one function to test_helpers.c\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: If5c24da9062d100419220fe000409b73596e773c\n" }, { "commit": "ce386b12b15b33cc362cbca14514831e4459467f", "tree": "8ea080d30cc015cbdd5fe5b18f83051f806e3724", "parents": [ "6baf5b87ff121ceff5eb2f818dd8b409f2c30dc2" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Mar 29 18:36:36 2022 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Thu May 19 18:10:00 2022 +0100" }, "message": "test(spm): use ffa_helpers for ivy partition\n\nAllow the ivy partition to use the ffa_helpers functions.\n\nTo achieve this we create a common struct for ff-a calls that is\nused for both parameters and returns, this aligns with the Hafnium\nimplementation. We can then use preprocessor macros to pick either\nSMC or SVC as the conduit depending on the exception level the SP\nis running at.\n\nChange-Id: Ic9525baabcf40d15545b6f6d504cf954373f08f9\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\n" }, { "commit": "76c458a1fd6318f9d8fd7ab142985389d6b7db78", "tree": "afca4415b1d63c0c2378895f7cf14fb6c5bb4861", "parents": [ "cf67732e659b35777459456a495cdf03ca875101", "b31bc759af589bc95e3a88bbe5b525ad84d1ac89" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed May 18 22:03:20 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 18 22:03:20 2022 +0200" }, "message": "Merge \"feat(WFxT): add a test for WFxT instructions\"" }, { "commit": "d5c67b889678d4e05ab4c43c590e11aa8b58e7f0", "tree": "6fcef96d6d88bfb5ab28efdd22b83f69e42bec69", "parents": [ "a13b64bd4a2191b2c9715709b4db841b20fe7110" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Tue Mar 22 22:54:23 2022 +0000" }, "committer": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Wed May 18 11:35:21 2022 +0100" }, "message": "feat(ff-a): create function helper to setup FF-A mailbox\n\nFix test dependencies issue when SPM test is used individually.\nProvide an API function from SPM test suite to initialize the FF-A\nmailbox and enable FF-A based message with SP.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: I246491907f1641c47937a9a1c91cfd4a9b8bfe20\n" }, { "commit": "b31bc759af589bc95e3a88bbe5b525ad84d1ac89", "tree": "fd56860456f8fa8d5134e03e28d71c76ae60e0ec", "parents": [ "a13b64bd4a2191b2c9715709b4db841b20fe7110" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Dec 24 08:52:52 2021 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed May 18 10:52:18 2022 +0100" }, "message": "feat(WFxT): add a test for WFxT instructions\n\nThis patch adds the test to verify the WFET and WFIT instructions\nintroduced by FEAT_WFxT.\n\nWFET and WFIT instructions assist in generating local-timeout event\nand thereby act as wakeup event for the PE, when the virtual count\nin CNTVCT_EL0 (counter-timer virtual count) register equals or exceed\nthe timeout value passed with these instructions.\n\nAccordingly, this testcase verifies whether the time lapsed matches the\nvalue supplied with WFET and WFIT instructions.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I9aea5da869db8520e305e49989cb71f166a582eb\n" }, { "commit": "8c3da8beb712aa9992b73e02a6fd7d2fa10af035", "tree": "837fd7a9ce0c758cfe6665397a0ceee8676922b4", "parents": [ "98344d42bae5797a97f128176225043bbb28fd60" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Mon Jan 31 18:14:41 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Mon May 09 20:02:51 2022 +0200" }, "message": "feat(brbe): test that EL3 has properly enabled access to BRBE\n\nAccess to FEAT_BRBE control registers must be explicitly enabled in EL3,\nthis simple test just ensures that the registers are accessible or traps\nto EL3, similar to the TRBE test.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I0a25c5ce6beb6aa96b9428264b75cb3569ac535a\n" }, { "commit": "6328fb08e9a3821cb2fd2b9e57f97a3868a9276b", "tree": "4f90c521b82fb8114728fb2e115879c5650719de", "parents": [ "d3749b08d49a6cb4fd69e66da1e405dbbd3de57f" ], "author": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Fri Jan 14 15:48:16 2022 +0100" }, "committer": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Fri Mar 25 10:54:00 2022 +0100" }, "message": "test(cactus): add test for NS memory sharing between SPs\n\nDefine a new shared memory region in 48-bit address range\n(configured as NS in the TZC) in cactus-tertiary\u0027s manifest.\nSince SPs can share either secure or non-secure memory, propagate the\nsecurity information in the relevant cactus commands:\nCACTUS_REQ_MEM_SEND_CMD and CACTUS_MEM_SEND_CMD.\n\nChange-Id: I10af24c96ff8fc0d13c80a52b0264a1482a5cf56\nSigned-off-by: Federico Recanati \u003cfederico.recanati@arm.com\u003e\n" }, { "commit": "d3749b08d49a6cb4fd69e66da1e405dbbd3de57f", "tree": "ba6fa7fa5bbf622dd54281668f885ceaa9091f53", "parents": [ "0091af97592d9cd036a4b70433b70ac9c0ed22b0" ], "author": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Fri Jan 14 15:44:45 2022 +0100" }, "committer": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Fri Mar 25 10:54:00 2022 +0100" }, "message": "fix(plat/arm/fvp): make address space configurable\n\nMake FVP physical/virtual address space sizes configurable, with\ndefault at 34-bit (previously hard-coded value).\nMaximum tested value is 48-bit, FVP interconnect doesn\u0027t yet support\n52-bit PA.\nIncrease MAX_XLAT_TABLE and consequently NS_BL1U_RW_SIZE and\nNS_BLU2_LIMIT to accommodate the increased translation tables (based\non 48-bit max PA size).\n\nCustom PA size is passed to build system through the PA_SIZE define.\n\nFVP needs to be configured in a compatible way through the parameters:\n* cluster0.PA_SIZE, for each cluster;\n* bp.dram_size, setting a memory limit corresponding at least to\n PA_SIZE;\n* cci550.addr_width, interconnect address width should match PA_SIZE;\n* pci.pci_smmuv3.mmu.SMMU_IDR5, SMMU has to be configured as well if\n present.\n\nChange-Id: I57bc898fb2c9696c01fc8e20d00b4a3d09e22326\nSigned-off-by: Federico Recanati \u003cfederico.recanati@arm.com\u003e\n" }, { "commit": "6888feeb8e873b311b19b805990e3b2f25f7becf", "tree": "a917503f7b79fe7badd9e1b2dd84bef73f3ee590", "parents": [ "0c2a132bb2be5c1feb4a967952123f427ff0bcda" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Mar 08 13:35:56 2022 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Mar 08 14:25:14 2022 +0000" }, "message": "fix(tftf): remove invalid_access test from standard tests\n\nInvalid_access test suite performs negative tests by accessing invalid\nmemory and catching it in custom exception handler.\nThis test suite was made part of standard tests which is called for all\nplatforms and each EL3 configuration. This test was failing for the\ncase when EL3 was build with \"HANDLE_EA_EL3_FIRST \u003d 1\" causing\nexceptions to be trapped in EL3 and not forwarded to EL2 to be handled\nby custom exception handler.\n\nTo avoid this problem, remove this suite from standard test and\nintroduce a new test configuration.\n\nThis patch also fixes a minor compilation error in file\ncactus_test_memory_sharing.c\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I8a13617a01411be45c623dde2ccfc7d950f05f9a\n" }, { "commit": "9edbad6e741afee5f8c7e3a0603350f3fef82575", "tree": "9931bfbdd3121b2bfd4eb7bed90ed58c40563e16", "parents": [ "c0adf67dd803b6313a1368c1b4a0993faba2aacc", "82bbc57e7a496c6821eb1833cc1f8ce8354b3d9b" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Mar 02 14:58:05 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 02 14:58:05 2022 +0100" }, "message": "Merge changes from topic \"od/invalid-access-tests\"\n\n* changes:\n test(tftf): prevent realm region access from nwd\n test(cactus): prevent realm region access from swd\n feat(fvp): enable test to access el3 memory\n feat(tftf): add tests to access invalid memory\n" }, { "commit": "c0adf67dd803b6313a1368c1b4a0993faba2aacc", "tree": "4e727b4d413b8bacdef4ccdc43ead565342bbfb7", "parents": [ "1b6cb96f0c229c81c749a24b9c10b86e41204bb6", "0e4629fb041a2f643f401b61047e562dbcf03986" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Mar 01 18:49:27 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 01 18:49:27 2022 +0100" }, "message": "Merge \"test(el3-runtime): check DIT is retained on exception\"" }, { "commit": "5f513d692006ac52b8cb87fe91cbfb002dd98e13", "tree": "1542ce69e37c47bf127800e0adb39aa6b47104aa", "parents": [ "1b6cb96f0c229c81c749a24b9c10b86e41204bb6" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jan 17 11:05:53 2022 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Mar 01 17:41:47 2022 +0000" }, "message": "feat(tftf): add tests to access invalid memory\n\nAdd test framework to access memory addresses which are not accessible\nto tftf. The test only introduced for \"aarch64\" as there is no sync\nexception handler for \"aarch32\".\nThe test framework will catch the error and do graceful exit.\nFor now only test introduced is to access memory owned by EL3, which can\nbe easily extended to add more tests to access realm/secure(in RME\nenabled systems).\n\nPlatform needs to provide test address, if not then test will\nbe skipped.\n\nTest steps:\n\t1. Register a custom sync exception handler(try \u0026 catch)\n\t2. Access a protected memory, should give data abort.\n\t3. Exception handler should check if data abort then continue.\n\t4. Unregister custom exception handler.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Ib8b199acb9b96548c889539610ff1b58777d3d1d\n" }, { "commit": "0e4629fb041a2f643f401b61047e562dbcf03986", "tree": "1c2cb6651f17343e1dca96ea06670749ea894b2d", "parents": [ "a7ccb402229b3b9419ec17f311576ffdf1e037b7" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Oct 26 14:01:23 2021 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 02 11:36:02 2022 +0100" }, "message": "test(el3-runtime): check DIT is retained on exception\n\nAdd a test to check that the PSTATE bits not set in the\nAarch64.TakeException but set to a default when taking an exception to\nEL3 are maintained after an exception and that changes in TSP do not\neffect the PSTATE in TFTF and vice versa.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Id4d625c7e9cbb565ac236f844274319cc02c2335\n" }, { "commit": "82e1a253f909e30c8cc62decaba4f673dc8a8c0e", "tree": "b3ea2f736e7a0536a9bed4d43fad506c3ac75e5e", "parents": [ "589a112c6d96697529eb96cc3452c1a6d3d5af5a" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jan 04 13:45:31 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Jan 27 21:09:57 2022 +0000" }, "message": "feat(afp): add a test for Advanced floating-point\n\nThis test is to ensure that TFTF is allowed to write the FPCR register\nbits to control the floating-point operation when FEAT_AFP is\nimplemented.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I21ea288e698bbe706aac55740e28d5f6ccb700dc\n" }, { "commit": "79c08f110715360288554e93b6c994c02090a06b", "tree": "79d4c400ee827c3e6bfc91a8ae512af48fe8fbda", "parents": [ "bd909ac2ae1c2df76f0696702e583d416b4f4141" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 27 15:15:16 2021 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Nov 10 11:26:13 2021 +0000" }, "message": "feat: spm helper functions for MP tests\n\nAdded two helper functions to help with SPM tests in a MP setup.\n- spm_core_sp_init: to initialize an SP in a given core.\n- get_current_core_id: to get the current core ID.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Iad10d43f258f5ed05ce52b87c94a9333c228f26d\n" }, { "commit": "952e1f76f14711fcca68e08d73cedb3cc63e619b", "tree": "50e5285db716d0a1caed6778af6d8eec912630d0", "parents": [ "fbbbf62f13959b6a86f3d67fde45162ed29dc588" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Jul 30 17:19:09 2021 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 09 17:12:28 2021 +0000" }, "message": "refactor(spm): managed exit tests\n\nFactored out code to enable managed exit interrupt for a given SP, to\nreuse it in the context of testing the Schedule Receiver Interrupt\nSWd behavior, in the context of notifications feature work.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Idcecd486c7a952f0842ebf90c274adcea9e30152\n" }, { "commit": "f7535f4a81fb6015a3373f00f07f6ecb216df01c", "tree": "04e857c55b158c20807d186f56e18d165787f1b2", "parents": [ "269118a82af2c240513a716c1db2cb66ccce1e3e" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Jul 30 11:58:41 2021 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 09 17:10:19 2021 +0000" }, "message": "feat(cactus): count requests received\n\nMessage loop counts the amount of requests received in each core. The\ncounting can be accessed through newly added test command\nCACTUS_GET_REQ_COUNT_CMD.\nAdded such special command to be able to test delay Schedule Receiver\nInterrupt, in the context of the notifications feature.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Id0a5a9cf58e10d1221a1a0f0af6264474fe7e020\n" }, { "commit": "d56c53c062f506c6e3cab94fe0d93a2377d0a879", "tree": "3457399803dc23db82333b25d6e909049b9d1d10", "parents": [ "16d52d5109894be0eb2e81f4ce101edb8ef38a67" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jul 01 16:32:16 2021 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 29 11:36:51 2021 +0100" }, "message": "refactor(spm): helper functions for SPM\u0027s MP tests\n\nFactored out code to power on cpus from direct messaging test, and\nplaced in a helper function. To be used to test other multicore\nfunctionality.\nThe function expects the cpu on handler to be implemented in the scope\nof the functionality to be tested.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ic0074dc85e0a906bae9d7b8cc071aff476f94de5\n" }, { "commit": "6d0e1b60b8654409d9928a5b8a9ecdbc5f8d3c1f", "tree": "33a20b55fe8c1821f14bb764e40d401eef49add0", "parents": [ "2c518e5c677e7b39100784a0360387b717506564" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jul 09 13:58:28 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Aug 26 18:53:55 2021 +0100" }, "message": "feat(sys_reg_trace): add trace system registers access test\n\nAdded a test to read trace system registers to ensure that EL3\nis giving permission to non-secure EL2 to access these registers.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I0bdbb5aff81a78fc3a3766278c48b25bb6e1779f\n" }, { "commit": "2c518e5c677e7b39100784a0360387b717506564", "tree": "987cdd4b72d88830568278e5d26953f7f9555e7f", "parents": [ "87c03d1f4c06c1dea78abb359d9b1b4c24470f88" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Jul 08 16:36:57 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Aug 26 18:53:50 2021 +0100" }, "message": "feat(trf): add trace filter control registers access test\n\nAdded a test to read trace filter control registers to ensure that EL3\nis giving permission to non-secure EL2 to access these registers.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I9354d8592bd187206add717b9d3b0206382a06d3\n" }, { "commit": "87c03d1f4c06c1dea78abb359d9b1b4c24470f88", "tree": "0d242548dcd539f98ed7f330c3a34d3b333375d3", "parents": [ "cf664616030fbf634812c2a16595c434d642dd86" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jul 06 22:57:11 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Aug 26 18:17:28 2021 +0100" }, "message": "feat(trbe): add trace buffer control registers access test\n\nAdded a test to read trace buffer control registers to ensure that\nEL3 is giving permission to non-secure EL2 to access these registers.\n\nChange-Id: I70faa5bb7e0bc648fbc3d14cb9c1b8da3470a201\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "58757e88b7c70c3d238ba5b277918df386d5c638", "tree": "a9f2aace1a69fb80c9d375f287c53b1cce5d9dbe", "parents": [ "1235bcafe5b4a226e46412919d89b7aa9b665b55" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Jul 30 10:18:00 2021 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Aug 09 17:23:34 2021 +0200" }, "message": "feat(ff-a): update FF-A version to v1.1\n\nBump the required FF-A version in framework and manifests to v1.1 as\nupstream feature development goes.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: If3dc227635f1c65d0623ed36ad7e3766c5d5e132\n" }, { "commit": "d6715f10725c9e20bbca027681bcefc78208899e", "tree": "b25efd3be9d960f9a8009ea40b2fc8b8841e6544", "parents": [ "be7bf20271a3c76c13f67960d4f0cf911ec49367", "959be3383999fae2e82c4e24ed419b4762c99254" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Jun 30 11:51:10 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 30 11:51:10 2021 +0200" }, "message": "Merge \"feat(sve): enable SVE tests in tftf\"" }, { "commit": "959be3383999fae2e82c4e24ed419b4762c99254", "tree": "67f4c31cf13a9021321447ad75d2982eccb900cb", "parents": [ "ac84570b07556076b72aa9ea72a68695dd48687d" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Tue Mar 16 14:18:13 2021 +0000" }, "committer": { "name": "Maksims Svecovs", "email": "maksims.svecovs@arm.com", "time": "Tue Jun 29 12:28:52 2021 +0100" }, "message": "feat(sve): enable SVE tests in tftf\n\nAdding two tests to check that floating point context is preserved.\n1. Use SIMD instructions on SVE-enabled system.\n2. Use SVE instruction on a full-length vectors.\nBoth tests check that floating point context is preserved after\nreturning from the secure world.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: Idccff7c3f1658cc66b64e144cc00cda6e0aeea50\n" }, { "commit": "9f1952c9b7fe5b3f422e53bd7c1038fcd5764b2d", "tree": "bcfddb9641c785d3a5e00703e2cf586ab775619c", "parents": [ "08798acfce407339bc4433c095c6b3a5da31e12a" ], "author": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Mon Aug 24 11:32:32 2020 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jun 18 16:34:56 2021 +0100" }, "message": "SPM: Add shim layer to Ivy partition and enable PIE\n\nAdd a shim layer that runs at S-EL1 to the Ivy partition.\nAlso enable Ivy to be built with PIE.\n\nSigned-off-by: Ruari Phipps \u003cruari.phipps@arm.com\u003e\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: I821a8ac99d07200aec93ca29d182f8ab6716616c\n" }, { "commit": "103e056ba016d10809948657f6b4f0de93779bc4", "tree": "d527dceccfce849895db594fa9bac144d63ee59b", "parents": [ "db4a2a7453741f86e350a6e296879970da0ec9bf" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Thu Feb 04 16:58:31 2021 +0000" }, "committer": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Wed Feb 10 11:56:46 2021 +0000" }, "message": "[SPM] tidying common code to tftf and cactus\n\nThis patch moves the code used to test SPM functionality, not explicitly\ndescribed in FF-A specification, from ffa_helpers to spm_common which is\nbuilt for both tftf and cactus.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: I461efad977cc4d02701feea7b2215a61453716ef\n" }, { "commit": "0446930111eb5750c90aedcd4b2513ac990998a3", "tree": "3d446e4e82c950b149c02c5b049eeccdb0f05fa8", "parents": [ "4904c8632c255b6ac3fb77109f807b3a11cb910b" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 21 14:48:13 2021 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 21 14:51:06 2021 +0000" }, "message": "Nit: Change name from helper function and macro\n\nRemoved reference to Hafnium in name from helper function and macro to\nmake them generic.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I5bdba013b3a0478dc1ef9058e71747480ba5ff1d\n" }, { "commit": "d708c03b6a6c2fc5bfcdfb290ba916f691e9d37d", "tree": "dec4da51a50394edb4b7119c3958b558c84e0001", "parents": [ "83ede9be9c9397b4c46509ceb4475785c6858c15" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Nov 19 12:14:21 2020 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Dec 15 11:10:20 2020 +0000" }, "message": "TFTF: helpers for SPM tests\n\nAdded functions and macros to help check at the beginning of the test,\nthat system is as expected for SPM tests in which Hafnium is deployed as\nSPMC.\nThis includes:\n- Checking SPMC has expected FFA_VERSION;\n- Checking that expected FF-A endpoints are deployed in the system;\n- Getting global TFTF mailbox.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I9195bcff8ed93156e838b192bb70a9634e18fbbf\n" }, { "commit": "f1126f2b7ea4327b70957719de74c4af6fea72df", "tree": "29393cf3417d2cd5ae5f1d3f6d2a4d1b5a268556", "parents": [ "c031cc08ebd9948bb8b42423c13f9257cd4bafb9" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Nov 02 17:28:20 2020 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Dec 10 18:06:50 2020 +0000" }, "message": "SPM: RXTX map test on TFTF\n\nSome FF-A interfaces use RXTX buffers to exchange information with SPMC.\nTo avoid repetition of RXTX mapping across the spm-related tests, and\nprevent allocation of multiple pages for RXTX buffers within TFTF\nruntime:\n- Implemented test helpers that hold address of RXTX buffers;\n- Implemented test to FFA_RXTX_MAP ABI, that also sets value of RXTX\nbuffers;\n- Cleaned up memory sharing tests that previously implemented RXTX\nmapping.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I4a67982d3d185bf83809156e4fce03c6edb967d9\n" }, { "commit": "f474306a656c58b7698e486b9a857b73b5b7f4ee", "tree": "4c5b2096db913fa61efa146b8acf9e154be88459", "parents": [ "63cdaa7db7e132ade67b03e31ad73ae1bbcfa434" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Oct 27 19:39:57 2020 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Oct 29 10:16:35 2020 +0000" }, "message": "SPM: TFTF skip test if FFA endpoint absent\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I0f653ae7764ede3dda3e51bd4eb94b7025606203\n" }, { "commit": "953ec59b3ed74380c690e550c85eefe19b07716f", "tree": "2293a7fcfa63ed11dd88b4bb65e1249f9052c79b", "parents": [ "56c3942b4eaa2ad85749b11d5895fad6bfb5b61c", "7fac162cd9439783ef60aaf266d22ad454445ace" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 18 14:55:16 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 18 14:55:16 2020 +0000" }, "message": "Merge changes from topic \"af/add_branch_protection_makefiles\"\n\n* changes:\n TFTF: Add ARMv8.5 BTI support in makefiles\n TFTF: Add ARMv8.5 BTI support in xlat_tables_v2 library\n TFTF: Add ARMv8.5 BTI support in assembler files\n TFTF: Add ARMv8.5 BTI-related definitions\n" }, { "commit": "45ada40c895b1087de08c05d6d6a311cb0f47c79", "tree": "65a33e6efec3a2a0bb62d548bb76b876a9653cb1", "parents": [ "9cd75024bf2d3abb4e620f308d26876ee75c1c01" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 17 19:07:11 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Aug 18 14:52:39 2020 +0000" }, "message": "TFTF: Add ARMv8.5 BTI support in assembler files\n\nThis patch adds BTI support in assembler files\nwhich fully correspond to those in TF-A source tree.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ie6a7b248c967684c6b2b86b915f0499fe095bba3\n" }, { "commit": "ef507e4a7dc99a992f78eeed25f8f51408cc0f8f", "tree": "e08d4e061f3ad6d4ff43a1f07eb3b59dd0095cb1", "parents": [ "69cf580a8de8f2695ba1e178a327f29a42058842" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jun 05 08:41:42 2020 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Jul 20 17:07:03 2020 +0000" }, "message": "plat/arm: Move defines to platform specific header file\n\nSome platform specific defines found in \u0027fwu_nvm.h\u0027 header\nhence moved such define to platform specific header file.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I1cfd1c95306e2ded5b78d1d6424ad159a958c502\n" }, { "commit": "036854b119f7d055dfc04266d11377af27a313fe", "tree": "291485dc4c3047a62a1a034cbb507d7c46724495", "parents": [ "a09f6365152c08d7c8285a4841b0c0c3bb39bb0d", "24a4a7c5b3158804c866d3c7b43b9e1314b474f4" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jun 26 08:36:27 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 26 08:36:27 2020 +0000" }, "message": "Merge \"Update FIP corrupt address\"" }, { "commit": "8f08a05490ed3ce474cc821297929bf8df5691d2", "tree": "da0afb6bc23221c8fd9efe95b6fdc559245a7987", "parents": [ "87c9a5cc97c16f6c1c991fab334bfed4e4fce296" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 26 17:14:40 2020 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Jun 19 09:34:30 2020 +0100" }, "message": "SPM: TFTF test of FFA_VERSION interface\n\nImplemented test to FFA_VERSION interface:\n- \"test_ffa_version.c\" contains functions to test FFA_VERSION ABI;\n- Test suite for FFA_VERSION ABI in tests-spm.xml;\n- Helper macros changed in \"ffa_helpers.h\".\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I6b0e937e30fceaa21a57c4ba0761a62049b16c0d\n" }, { "commit": "24a4a7c5b3158804c866d3c7b43b9e1314b474f4", "tree": "363dc9c31c55c5e25d1f58f38e7dad4627ae48fe", "parents": [ "5861730b3d6333f936c2fcecaa034de0391cbd94" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jun 05 08:41:42 2020 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jun 09 13:24:39 2020 +0100" }, "message": "Update FIP corrupt address\n\nUpdated \"FIP_CORRUPT_OFFSET\" address which is used to corrupt\nBL2 in FIP. This address is being changed due to addition\nof fw-config image in FIP.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I003ccf9ba80b50646ed732b9306e5be757dbf4ff\n" }, { "commit": "945095ad9a97bc9469ca095f8dd057a4021297dd", "tree": "b0ef7e031939a3c397f5a4ab05cda9ff3bbc438f", "parents": [ "90f1d5caed95873e02071ef040191de52ee84a52" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Thu Apr 16 10:54:59 2020 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Wed Jun 03 13:30:29 2020 -0500" }, "message": "Test that TF-A supports ARMv8.6-ECV\n\nNote: This test will cause an unhandled exception in the case that TF-A\nis not doing its job and enabling ARMv8.6-ECV Self-Synch when the hardware\nsupports it.\n\nChange-Id: Iee19963f31fa47b0010e77d7b56b05b71ec1b507\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\n" }, { "commit": "90f1d5caed95873e02071ef040191de52ee84a52", "tree": "d1b7fb445f987d6f7ff226e9dd49b14c507fe8bf", "parents": [ "5da6f402dcc85a9a281eb93dc00d5af2eeabf3b0" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Thu Apr 16 10:54:51 2020 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Fri May 29 14:19:14 2020 -0500" }, "message": "Test that TF-A supports ARMv8.6-FGT\n\nNote: This test will cause an unhandled exception in the case that TF-A\nis not doing its job and enabling ARMv8.6-FGT when the hardware supports\nit.\n\nChange-Id: Iae0fe39895909248b5e7b07a1a73f7702adce7dd\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\n" }, { "commit": "7581c388980a78f2938633ff0ec467c798afed91", "tree": "1c92c095a79eea03da670c31dbee58d5fd13d416", "parents": [ "fa940145f77d1b9b625866b96108ba8eb8c62d46" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 07 18:34:20 2020 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 15 16:11:32 2020 +0100" }, "message": "SPCI is now called PSA FF-A\n\nSPCI is renamed as PSA FF-A which stands for Platform Security\nArchitecture Firmware Framework for A class processors.\nThis patch replaces the occurrence of SPCI with PSA FF-A(in documents)\nor simply FFA(in code).\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I17728c1503312845944a5ba060c252c2b98f3e91\n" }, { "commit": "61be4c1ce08b68577d6ea3df2c34357b5b98a547", "tree": "19498c7a6ad5fb41e5ed4bc0a5bf1b0d7d61058b", "parents": [ "55f79d6a83dc642b281f2df95b268417fef75cae" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Dec 06 17:45:07 2019 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Mar 20 14:37:01 2020 +0100" }, "message": "tftf: SPCI Beta1 add direct messaging test\n\nThis patch strips out former SPCI Alpha sample test code. Removing SPRT\nreferences will be done in another coming patch. Version check is adapted\nto SPCI Beta1. Version is now returned in x2.\n\nThe first test is a direct messaging test using SPCI_MSG_SEND_DIRECT_REQ\ntargetting a bare-metal cactus SP. TFTF expects a response from the SP\nreturning with SPCI_MSG_SEND_DIRECT_RESP.\n\nNote: this patch also provides an initial SPCI_RUN interface. This API\nmay not be used in the mid-term because VM to SP communication is supposed\nto be done only through direct messaging. Though the SPM boot-up for now\nis only launching the first SP in the list of declared SP in SPMC manifest.\nIn order to make 2nd-VM ready, TFTF has to \"boot-up\" the SP through a single\nSPCI_RUN invocation till it reaches SPCI_MSG_WAIT in the SP. Once SPM\nimplements boot up through all SPs, this SPCI_RUN invocation will no longer\nbe required.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I141abd3e348409b3d34a911d0552570f49e85846\n" }, { "commit": "c249d5e5cfbf2aa0f584001543c1d39953e1d6aa", "tree": "bae825efb76949c451188bb0e96de2ea1b120514", "parents": [ "1b5952a79ca1a6feb7b23372420285e886497852" ], "author": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Thu Feb 06 16:29:45 2020 -0600" }, "committer": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Tue Feb 11 09:22:12 2020 -0600" }, "message": "Switch AARCH32/AARCH64 to __aarch64__\n\nNOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.\n\nAll common C compilers pre-define the same macros to signal which\narchitecture the code is being compiled for: __arm__ for AArch32 (or\nearlier versions) and __aarch64__ for AArch64. There\u0027s no need for TF-A\nto define its own custom macros for this. In order to unify code with\nthe export headers (which use __aarch64__ to avoid another dependency),\nlet\u0027s deprecate the AARCH32 and AARCH64 macros and switch the code base\nover to the pre-defined standard macro. (Since it is somewhat\nunintuitive that __arm__ only means AArch32, let\u0027s standardize on only\nusing __aarch64__.)\n\nNOTE: This change is based on below TFA commit\nhttps://github.com/ARM-software/arm-trusted-firmware/commit/402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c\n\nSigned-off-by: Deepika Bhavnani \u003cdeepika.bhavnani@arm.com\u003e\nChange-Id: If2c3dbaeb01d4a9d8cfd95d906e5eaf4ae94417f\n" }, { "commit": "35d824e362df862215f987fdf844ccfb8d9ccd92", "tree": "e7f4d50abc003472cf6e2f8fb6cdc72232b6e45f", "parents": [ "584b3cb3aba5423c31496a4f46ea6a58e44dd7d9" ], "author": { "name": "Oliver Swede", "email": "oli.swede@arm.com", "time": "Tue Oct 01 13:50:36 2019 +0100" }, "committer": { "name": "Oliver Swede", "email": "oli.swede@arm.com", "time": "Mon Jan 13 16:04:58 2020 +0000" }, "message": "Make TFTF RFC 4122 compliant\n\nThis is a TFTF backport of a change that makes TF RFC 4122-compliant\nby converting the stored format of UUIDs from machine order (little\nendian) to network order (big endian).\n\nThis patch changes the data structure used to store the values in the\nsame way as in the related change in TF:\n033648652f2d66abe2454a75ded891a47cb13446.\n\nSigned-off-by: Oliver Swede \u003coli.swede@arm.com\u003e\nChange-Id: I052e570b80de61f87a049a08e347a2e5da7f841b\n" }, { "commit": "f1a45f767ad6dc31ebde044884f157a1deddbf3c", "tree": "3e9e306ba52936ca52fa73454eaa133335c5ba46", "parents": [ "2957ff7660eb3b14ed1ee7ade14218332410e3c0" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Tue Oct 08 16:51:45 2019 +0100" }, "committer": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Wed Oct 30 15:10:59 2019 +0000" }, "message": "Aarch32: Secure PMU counter leak tests\n\nThis patch adds Aarch32 support to the PMU counter leak tests.\n\nThese tests attempt to profile the Secure world by configuring\nEL0 system registers such that the PMU is told to increment\ncounters at Secure EL1, Secure EL2 and EL3. The tests fail if\nuseful information was leaked.\n\nThe Secure world defends against this type of attack with a\ncombination of configuring EL3 system registers and saving/restoring\nEL0 PMU registers. Exactly which defense is employed depends on the\narchitecture version.\n\nSigned-off-by: Petre-Ionut Tudor \u003cpetre-ionut.tudor@arm.com\u003e\nChange-Id: I2dcc9e786a18d9859ac089f8008b060d277bee3a\n" }, { "commit": "277fb7628c270c8a891c24dea80350f9c935d4c6", "tree": "05ffa6439c4713d68a8df2d4671139c531a7c751", "parents": [ "1ca3102141319bd514c296ddc256f92e321780a2" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Oct 08 12:10:45 2019 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Oct 08 12:23:38 2019 +0200" }, "message": "Add tests for MTE support\n\nTF-A now has support for the new Memory Tagging Extension in ARMv8.5,\nsee commit 91624b7fed52 (\"Merge changes from topic \"jc/mte_enable\"\ninto integration\").\n\nThis patch creates and enables tests to ensure that the extension is\nbeing properly enabled and that no undesired leakages occur.\n\nChange-Id: I7708fb23a12e2f35a97533f296aaa53db776ddd2\nSigned-off-by: Justin Chadwell \u003cjustin.chadwell@arm.com\u003e\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "f68ebdb9b45cc7a58f816f153f5e626c898dc0cf", "tree": "8eb48a5843eb4acfa86c3066173aaa2b0f898d4b", "parents": [ "0012dbc2a841abeff25be8be1113f19073ee4d2c" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Wed Sep 18 16:13:00 2019 +0100" }, "committer": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Fri Oct 04 09:35:00 2019 +0100" }, "message": "Try to leak counter values from secure world.\n\nThis patch introduces a series of tests that try to leak PMU counter values\nfrom EL3 and S_EL1.\n\nPMU events used:\n\t- CPU cycles via PMU counter PMCCNTR_EL0\n\t- Retired writes to PC via PMU counter PMEVCNTR0_EL0\n\nThis AARCH64-specific patch is for security fix:\nhttps://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1789\n\nThe AARCH32 versions of these tests will be in a future patch.\n\nSigned-off-by: Petre-Ionut Tudor \u003cpetre-ionut.tudor@arm.com\u003e\nChange-Id: Ib27948edadde30272e59a9ab208543703fa078bd\n" }, { "commit": "8790f025e12065ccccfe4d19fdcc672c80aa784b", "tree": "e5548628d170748a3f2d98973b4db315a76c88ef", "parents": [ "29ef1dd13dfb989008fc98f7f7c17f163e0479bf" ], "author": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Fri Mar 15 14:47:02 2019 +0000" }, "committer": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Mon Apr 08 14:34:42 2019 +0100" }, "message": "Add unit tests for Pointer Authentication\n\nAdd unit tests to:\n Test access to the key registers.\n Use the pointer authentication instructions.\n Call psci version and check the EL3 pointer authentication keys\n aren\u0027t leaked.\n Make a tsp call and check the secure world keys aren\u0027t leaked.\n\nChange-Id: Ic7940757e6f9fc905ccef8c035e0c22b47b35cd7\nSigned-off-by: Joel Hutton \u003cJoel.Hutton@Arm.com\u003e\n" }, { "commit": "f2218e7b6a4f8c2c3d6db00703caad95f5e5b157", "tree": "83f72bbabcabae7e25e82c3192d27718dea21f67", "parents": [ "960906b2d8fc2596f257b55606c69505d2bf1130" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Tue Mar 19 10:59:11 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Tue Mar 19 11:22:43 2019 +0000" }, "message": "Reintroduce Cactus-MM and SPM-MM tests\n\nThe code has been taken from commit 99f4fd283b6f (\"cactus: Use UART2\ninstead of UART0\") and modified slightly to be integrated in the current\nmaster.\n\nThere are three tests that are failing in the CI. They have been\ndisabled for the time being:\n\n- mem_attr_changes_tests() in cactus_main() in the file\n spm/cactus_mm/cactus_mm_main.c.\n\n- Two tests in the file tftf/tests/tests-spm-mm.xml.\n\nChange-Id: I6332cbff1cefeb82b9447fae1b613879e65186a1\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "602b7f58dd7668411c8a4032652b4552bd7fe934", "tree": "675e0939d19e306e01703359d7b8661d4f312d32", "parents": [ "8a573de8dda42258b747e56f19190311ea090d29" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 14:13:43 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Mar 04 12:20:38 2019 +0000" }, "message": "libc: Update includes\n\nReflect the changes in the structure of libc.\n\nNB: the include of stdarg.h in nvm_results_helpers.c is not in alphabetical\norder because it needs to be included before stdio.h. Fixing this would require\nfurther changes.\n\nChange-Id: I07f62a3450802833408ff3e1f950fd3b643e5e33\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "a2d516fc5215973b4df38fe072fb68a8899e4ae4", "tree": "18da625a1492e7d41a1dc89fab61e50d884354b9", "parents": [ "c1617386e332973c334b097ad7e188437ef8e1a7" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 16:34:19 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 16:40:07 2019 +0100" }, "message": "Always print file and line number in panic/unreachable macros\n\nRelease builds used to have a special variant of these macros without\nthe source code location information. This kind of mechanism is useful\nwhen writing software that needs both a development and production\nversion so that the source code information is not leaked when the\ndevice is in the field.\n\nHowever, in the context of TF-A Tests, it makes little sense, as it\u0027s\nunlikely somebody would ever ship a device with TF-A Tests installed\non it.\n\nChange-Id: Ic14ad87c2756762807ee71142f21d6973233144e\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "452f360545f0b4d19720c2dfbaf80cf48c1aa3de", "tree": "e0a61d5a614b9f7193a0b53357f346e7ec8f04c3", "parents": [ "80ddcc3286b61f40015b30296a47baf47c3e8fd0" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 13:49:22 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 13:51:17 2019 +0100" }, "message": "Add CFI debug info to vector entries\n\nThis is based on TF-A commit 31823b6961d35a5d53e81d3bf4977ad7b2be81dd.\n\nAdd Call Frame Information assembler directives to vector entries so\nthat debuggers display the backtrace of functions that triggered a\nsynchronous exception. For example, a function triggering a data abort\nwill be easier to debug if the backtrace can be displayed from a\nbreakpoint at the beginning of the synchronous exception vector.\n\nDS-5 needs CFI otherwise it will not attempt to display the backtrace.\nOther debuggers might have other needs. These debug information are\nstored in the ELF file but not in the final binary.\n\nChange-Id: I1129419f318465049f53b5e41c304ea61fa44483\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "750b7cca6af02a35e52eaf012b32f1f11dc18ceb", "tree": "857aab92ded199a089919bb4fb6e519483dcf11d", "parents": [ "411a6b26f73dfb85143603cdad09588b8e159b04" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Nov 08 14:10:18 2018 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Dec 13 16:07:05 2018 +0100" }, "message": "Do not print CPU MPID in mp_printf()\n\nmp_printf() should just be an MP-safe version of printf(), i.e. one\nthat takes the console lock before printing. It should not be\nresponsible for printing the CPU MPID as well, this decision should be\nleft to the caller.\n\nAlso make Cactus and Ivy use mp_printf(). Before that, they could not\ncall this function because they couldn\u0027t access the MPIDR_EL1 as\nS-EL0 images.\n\nChange-Id: I4eafee01ffc279296395b94dd4a07cfbb8e858e2\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "0b1ab4064a9f6414f8b91a33f1bac0be7a9adfad", "tree": "de8b41c5ec538bbcaefb0a21269627cfa2968b7d", "parents": [ "6fb5fb08f5cc71bec42bd0076797d13e64ea1484" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Dec 05 15:38:39 2018 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Tue Dec 11 15:04:14 2018 +0000" }, "message": "ivy: Introduce new test Secure Partition\n\nIn order to test multiple partitions it is needed to have at least two\ndifferent partitions with different services. This way it isn\u0027t possible\nto accidentally call partition A with a service of partition B and have\nit work correctly.\n\nCactus is meant to be the main test Secure Partition. It is the one\nmeant to have most of the tests that a Secure Partition has to do. Ivy\nis meant to be more minimalistic. In the future, Cactus may be modified\nto be a S-EL1 partition while Ivy will remain as a S-EL0 partition.\n\nChange-Id: I29d09b9f9400b58568f9b90344a4034332a6e6e1\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "652d20a9e6fa0c4ca85bdb7341e98225c28eb61d", "tree": "45d8f6dcbee5d803302cd9eef038bdd50ec085e4", "parents": [ "302d3d076fc41538850da09c318017f3e1ecb602" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Mon Dec 10 17:17:33 2018 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Mon Dec 10 17:17:33 2018 +0000" }, "message": "SPM: Test open and close handle\n\nThe tests request valid and invalid handles and close them.\n\nChange-Id: Ie421507d8dd4793e635e82f74c206529d9ba59d0\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "3cd87d77947ec4fc04440268ed122b4ed81c7781", "tree": "78fdee12b026b931029e434f29b4fe09835fe4c9", "parents": [], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Oct 09 11:12:55 2018 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Oct 10 12:34:34 2018 +0200" }, "message": "Trusted Firmware-A Tests, version 2.0\n\nThis is the first public version of the tests for the Trusted\nFirmware-A project. Please see the documentation provided in the\nsource tree for more details.\n\nChange-Id: I6f3452046a1351ac94a71b3525c30a4ca8db7867\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\nCo-authored-by: amobal01 \u003camol.balasokamble@arm.com\u003e\nCo-authored-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\nCo-authored-by: Asha R \u003casha.r@arm.com\u003e\nCo-authored-by: Chandni Cherukuri \u003cchandni.cherukuri@arm.com\u003e\nCo-authored-by: David Cunado \u003cdavid.cunado@arm.com\u003e\nCo-authored-by: Dimitris Papastamos \u003cdimitris.papastamos@arm.com\u003e\nCo-authored-by: Douglas Raillard \u003cdouglas.raillard@arm.com\u003e\nCo-authored-by: dp-arm \u003cdimitris.papastamos@arm.com\u003e\nCo-authored-by: Jeenu Viswambharan \u003cjeenu.viswambharan@arm.com\u003e\nCo-authored-by: Jonathan Wright \u003cjonathan.wright@arm.com\u003e\nCo-authored-by: Kévin Petit \u003ckevin.petit@arm.com\u003e\nCo-authored-by: Roberto Vargas \u003croberto.vargas@arm.com\u003e\nCo-authored-by: Sathees Balya \u003csathees.balya@arm.com\u003e\nCo-authored-by: Shawon Roy \u003cShawon.Roy@arm.com\u003e\nCo-authored-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nCo-authored-by: Thomas Abraham \u003cthomas.abraham@arm.com\u003e\nCo-authored-by: Vikram Kanigiri \u003cvikram.kanigiri@arm.com\u003e\nCo-authored-by: Yatharth Kochar \u003cyatharth.kochar@arm.com\u003e\n" } ] }