)]}' { "log": [ { "commit": "073a9e46483b51ecd45dbdbc39a5367523ff05f4", "tree": "464964bc7346ad41b5c6f30cbdc61690dcb97478", "parents": [ "83aa8e4b6d3abbaf43ab453c95befc3a8c281be8" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon May 11 16:45:56 2020 -0700" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Aug 17 21:39:10 2020 +0000" }, "message": "Tegra194: support for RAS corrected error testing\n\nThis patch introduces a test to inject RAS corrected errors for\nall supported nodes from all CPUs. On injecting an error, the CPU\nverifies that the error was detected with the help of an IRQ.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I4a679e432d36e20aac64e7062fbaab438e96dfc0\n" }, { "commit": "83aa8e4b6d3abbaf43ab453c95befc3a8c281be8", "tree": "510478efec0a8257c56d20dab899683aedf87dd0", "parents": [ "a5799c9f986eb0deb4838e95bc535f7e1b04b117" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Fri Apr 24 18:15:39 2020 -0700" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Aug 17 21:39:03 2020 +0000" }, "message": "Tegra194: introduce RAS uncorrectable error injection tests\n\nPlatform vendors have some tests that are specific to their platforms.\nThis patch introduces a test suite for Tegra194 platfoms. As the first\ntest, the platform will inject the RAS uncorrectable errors and verify\nthat the platform detects and reports them.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: Id7b26d35dd4c638c2bd92959f18f12423ec1fd8b\n" }, { "commit": "9bc1ee80937bd3affc4384f7b6380e3b26b25fb3", "tree": "de17544e0c4f57ebb6065accc74866fd3e629a6e", "parents": [ "8a669d956699e967ca7f298d4bf74111c10dd164" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Jul 23 20:30:25 2020 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jul 28 13:35:32 2020 +0100" }, "message": "Update SMCCC_ARCH_SOC_ID test case\n\nSkip the test result if SMCCC_ARCH_SOC_ID feature is not available\nfor the platform and also, return failure in case of SMCCC_ARCH_SOC_ID\nfeature is available but platform unable to provide either\nsoc-revision or soc-version information.\n\nChange-Id: I447adb78814a902a4344d98e4f7fafe67000316f\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "c32f47899de53f58b08c549aff396062b256c029", "tree": "01a3353098f3d59ee75de560c45e8e5780cf8816", "parents": [ "40eb6a2ee493beb61d617f249af91e4f52453700" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Tue Jun 23 09:41:15 2020 +0100" }, "committer": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Mon Jul 27 13:36:01 2020 +0100" }, "message": "Cactus: FFA_PARTITION_INFO_GET test.\n\nCalls FFA_PARTITION_INFO_GET API from secure virtual FFA-A instance.\n * Gets information about primary SP.\n * Gets information about secondary SP.\n * Gets information about all SP running.\n * Attempts to get information about non-existing SP.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: Ief4de45b4d7decb1e1dba9bdb0e7e05516062dd2\n" }, { "commit": "40eb6a2ee493beb61d617f249af91e4f52453700", "tree": "55bf174271d54fad16fb0f1d7b1e25f67216f1cb", "parents": [ "c17c1d3ad278e007b551617be23b09e13b577ef0" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Mon Jun 08 11:15:30 2020 +0100" }, "committer": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Mon Jul 27 13:36:01 2020 +0100" }, "message": "Cactus: FFA_FEATURES test.\n\nCalls FFA_FEATURES API from the secure virtual FF-A instance which is serviced by SPMC.\nExpected responses should be edited according to the feature\nimplementation progress.\nRemoving obsolete SPRT version check and cactus_tests_misc.c as a\nresult.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: I8a2e569a3bce31a735e1af04994984fda2168296\n" }, { "commit": "c17c1d3ad278e007b551617be23b09e13b577ef0", "tree": "678e8f04c0832315e5a08062d0e32d063cc1625e", "parents": [ "d07b682769c1861bf12ef3a9177c62796c5c9d2b" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Thu Jun 11 15:03:01 2020 +0100" }, "committer": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Mon Jul 27 13:36:01 2020 +0100" }, "message": "SPM: TFTF test of FFA_FEATURES interface.\n\nForwards FFA_FEATURES call to SPMC via SPMD from the normal world.\nExpected responses should be edited according to the feature\nimplementation progress.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: I057100b4086108b0779e3fa76fbd86e0818f765c\n" }, { "commit": "69cf580a8de8f2695ba1e178a327f29a42058842", "tree": "af6040068c0a3e6c23132a9a022fbe0411516d4c", "parents": [ "ec87d759429e9496947aa917e012f85e98d9d5fa", "d9fcb247c43e326808eb46a01b23059477b55b56" ], "author": { "name": "joanna.farley", "email": "joanna.farley@arm.com", "time": "Fri Jul 17 13:23:33 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jul 17 13:23:33 2020 +0000" }, "message": "Merge \"remove dashes and and sort tests\"" }, { "commit": "d9fcb247c43e326808eb46a01b23059477b55b56", "tree": "febf223f10ca780ab4098ddab69d098c91aa930c", "parents": [ "8499afc44a1642b50fce554d4fdc9356d07d53a0" ], "author": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Tue Jul 14 11:09:45 2020 -0500" }, "committer": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Tue Jul 14 11:09:45 2020 -0500" }, "message": "remove dashes and and sort tests\n\nremove dashes on \u0027make help_tests\u0027 output aligns a bit more to main \u0027make\nhelp\u0027 output. Also, sort tests sets so users find quicker the name of the test.\n\nSigned-off-by: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\nChange-Id: If09992ddff95865233b1a311f9a52600d3756556\n" }, { "commit": "29278a9151fe90167ef57d5edc93e3e7551b65ff", "tree": "d603e87c26482243003a36dc3dffd8e5b0c9095e", "parents": [ "a117303c1eeab7599588eab35f220eaeca282a24" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jun 15 16:56:50 2020 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jun 30 10:42:58 2020 +0100" }, "message": "TFTF doesn\u0027t need to boot Secondary Cactus\n\nRemoved code that was booting Cactus Secondary, using FFA_RUN interface\nfrom TFTF\u0027s SPM tests. Hafnium now boots all partitions according to\n\"boot-order\" field value in the partition manifests.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I31a3507c92bffe81f78036da121259a5c19924cd\n" }, { "commit": "5aecd986f29140537d6a95f8e1961ecae57139e6", "tree": "e15f9641fc902dc862c9aebc0f06ead0563ed286", "parents": [ "a09f6365152c08d7c8285a4841b0c0c3bb39bb0d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jun 11 10:25:33 2020 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Jun 26 13:04:01 2020 +0100" }, "message": "Tidying FFA helpers\n\nMoved SP specific functions/macros to \"sp_helpers.c/h\".\nPlaced ffa interfaces/symbols shared between tftf and SPs in\n\"ffa_helpers.c/h\".\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I4cf967f87837ce3e7d0f7244f9cc0677f608f9cd\n" }, { "commit": "8f08a05490ed3ce474cc821297929bf8df5691d2", "tree": "da0afb6bc23221c8fd9efe95b6fdc559245a7987", "parents": [ "87c9a5cc97c16f6c1c991fab334bfed4e4fce296" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 26 17:14:40 2020 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Jun 19 09:34:30 2020 +0100" }, "message": "SPM: TFTF test of FFA_VERSION interface\n\nImplemented test to FFA_VERSION interface:\n- \"test_ffa_version.c\" contains functions to test FFA_VERSION ABI;\n- Test suite for FFA_VERSION ABI in tests-spm.xml;\n- Helper macros changed in \"ffa_helpers.h\".\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I6b0e937e30fceaa21a57c4ba0761a62049b16c0d\n" }, { "commit": "00ed5a4b3b0ddfeb925708e3afb037cc89ebd816", "tree": "bf3c91e4eebda0e129be310642d0ebdaad9302ee", "parents": [ "607d8d662b717d80d0587c6a0e2c1df278687062" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Wed May 06 10:30:59 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:36:28 2020 -0700" }, "message": "tests: arm_arch_svc: introduce support for NVIDIA Denver CPUs\n\nThis patch introduces support for NVIDIA Denver CPUs and variants in the\nSMCCC_ARCH_WORKAROUND_1 test.\n\nVerified with TFTF ARM_ARCH_SVC test on Tegra194.\n\n\u003csnip\u003e\n\nRunning test suite \u0027ARM_ARCH_SVC\u0027\nDescription: Arm Architecture Service tests\n\n\u003e Executing \u0027SMCCC_ARCH_WORKAROUND_1 test\u0027\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\n TEST COMPLETE Passed\n\n\u003csnip\u003e\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: Ibe179b43fd6a43c4fb5c6cdc7b0c78904efb1b5e\n" }, { "commit": "9060e3e68241a3fc1ad8588c20a97218c34c6c68", "tree": "1ef0aaf51b7a762d72ccf11a35f5b08764ca1c69", "parents": [ "0825704538540fa183851de902f83f7e22f69f0f", "945095ad9a97bc9469ca095f8dd057a4021297dd" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jun 03 20:46:29 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 03 20:46:29 2020 +0000" }, "message": "Merge changes from topic \"jb/8.6-features\"\n\n* changes:\n Test that TF-A supports ARMv8.6-ECV\n Test that TF-A supports ARMv8.6-FGT\n" }, { "commit": "945095ad9a97bc9469ca095f8dd057a4021297dd", "tree": "b0ef7e031939a3c397f5a4ab05cda9ff3bbc438f", "parents": [ "90f1d5caed95873e02071ef040191de52ee84a52" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Thu Apr 16 10:54:59 2020 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Wed Jun 03 13:30:29 2020 -0500" }, "message": "Test that TF-A supports ARMv8.6-ECV\n\nNote: This test will cause an unhandled exception in the case that TF-A\nis not doing its job and enabling ARMv8.6-ECV Self-Synch when the hardware\nsupports it.\n\nChange-Id: Iee19963f31fa47b0010e77d7b56b05b71ec1b507\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\n" }, { "commit": "90f1d5caed95873e02071ef040191de52ee84a52", "tree": "d1b7fb445f987d6f7ff226e9dd49b14c507fe8bf", "parents": [ "5da6f402dcc85a9a281eb93dc00d5af2eeabf3b0" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Thu Apr 16 10:54:51 2020 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Fri May 29 14:19:14 2020 -0500" }, "message": "Test that TF-A supports ARMv8.6-FGT\n\nNote: This test will cause an unhandled exception in the case that TF-A\nis not doing its job and enabling ARMv8.6-FGT when the hardware supports\nit.\n\nChange-Id: Iae0fe39895909248b5e7b07a1a73f7702adce7dd\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\n" }, { "commit": "480d0985aab3c50c5afbe7db7b0f9a8244207e19", "tree": "fd169daa7c6d701b2e20cab4f4e72ad9eef5ca68", "parents": [ "5da6f402dcc85a9a281eb93dc00d5af2eeabf3b0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Mar 17 16:46:31 2020 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu May 28 05:41:40 2020 -0500" }, "message": "Bug fix in Multicore IRQ spurious test.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Iaf160c8bc9c5807fc9263f5250c0aeedc20e5a8a\n" }, { "commit": "7581c388980a78f2938633ff0ec467c798afed91", "tree": "1c92c095a79eea03da670c31dbee58d5fd13d416", "parents": [ "fa940145f77d1b9b625866b96108ba8eb8c62d46" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 07 18:34:20 2020 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 15 16:11:32 2020 +0100" }, "message": "SPCI is now called PSA FF-A\n\nSPCI is renamed as PSA FF-A which stands for Platform Security\nArchitecture Firmware Framework for A class processors.\nThis patch replaces the occurrence of SPCI with PSA FF-A(in documents)\nor simply FFA(in code).\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I17728c1503312845944a5ba060c252c2b98f3e91\n" }, { "commit": "bc93a34c0db8adc674450b3452868ff3a1ec7503", "tree": "6b6acd48039dd7808c0e632fcbc2acb73b12b4e6", "parents": [ "705f66bd03095c14e76342c90e30fa3b76671951" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Apr 28 17:59:32 2020 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Apr 29 18:10:11 2020 +0100" }, "message": "Add test case for SMCCC_ARCH_SOC_ID feature\n\nAdded test case for \"SMCCC_ARCH_SOC_ID\" SMC call.\nThis SMC call is used to retrieve SOC version and SOC revision\n\nTest execution output is as below:\n\n\u003e Executing \u0027SMCCC_ARCH_SOC_ID test\u0027\n TEST COMPLETE Passed\nSOC Rev is not implemented\nSOC Ver \u003d 0x43b0000\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I48668ce22bb5d5767dadb42ce9526d77fd916bed\n" }, { "commit": "3f14f5ebffbe55fb2c4801d7626cc1b844fc6827", "tree": "16d5c3233bfa583c90c666a9521cd0abf2be3a25", "parents": [ "f7396b960a16695c09aebbc297b51911297c8a1d" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Mar 25 23:31:37 2020 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Mar 26 14:49:24 2020 +0100" }, "message": "tftf: spci: probe if SPMC is OP-TEE at S-EL1\n\nFor pre-Armv8.4 platform, the supported model is that SPMC runs at\nS-EL1. The candidate is OP-TEE with SPCI protocol adaptation. This patch\nperforms a version check through direct messaging and determines if\nOP-TEE runs as SPMC by checking version responses. If this does not\nmatch, then it assumes SPMC runs at S-EL2 with two Cactus instances\nrunning at S-EL1.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I34194b6e8b3d447a25f2153bbac1be2631cd7a5e\n" }, { "commit": "294a6362f65098a1fcfa75e9048c986c6dbe7288", "tree": "23dbdebb2180f2812109d34366c1eaa61177b3d6", "parents": [ "48e6d26e60ec5151a9771625bc4e9a1bed36bf31" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Dec 20 09:23:57 2019 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Mar 23 15:39:43 2020 +0100" }, "message": "tftf: re-introduce spm tests in the flow\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I3a80e023c71426605abb13303d466a9b93f3123e\n" }, { "commit": "61be4c1ce08b68577d6ea3df2c34357b5b98a547", "tree": "19498c7a6ad5fb41e5ed4bc0a5bf1b0d7d61058b", "parents": [ "55f79d6a83dc642b281f2df95b268417fef75cae" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Dec 06 17:45:07 2019 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Mar 20 14:37:01 2020 +0100" }, "message": "tftf: SPCI Beta1 add direct messaging test\n\nThis patch strips out former SPCI Alpha sample test code. Removing SPRT\nreferences will be done in another coming patch. Version check is adapted\nto SPCI Beta1. Version is now returned in x2.\n\nThe first test is a direct messaging test using SPCI_MSG_SEND_DIRECT_REQ\ntargetting a bare-metal cactus SP. TFTF expects a response from the SP\nreturning with SPCI_MSG_SEND_DIRECT_RESP.\n\nNote: this patch also provides an initial SPCI_RUN interface. This API\nmay not be used in the mid-term because VM to SP communication is supposed\nto be done only through direct messaging. Though the SPM boot-up for now\nis only launching the first SP in the list of declared SP in SPMC manifest.\nIn order to make 2nd-VM ready, TFTF has to \"boot-up\" the SP through a single\nSPCI_RUN invocation till it reaches SPCI_MSG_WAIT in the SP. Once SPM\nimplements boot up through all SPs, this SPCI_RUN invocation will no longer\nbe required.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I141abd3e348409b3d34a911d0552570f49e85846\n" }, { "commit": "c249d5e5cfbf2aa0f584001543c1d39953e1d6aa", "tree": "bae825efb76949c451188bb0e96de2ea1b120514", "parents": [ "1b5952a79ca1a6feb7b23372420285e886497852" ], "author": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Thu Feb 06 16:29:45 2020 -0600" }, "committer": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Tue Feb 11 09:22:12 2020 -0600" }, "message": "Switch AARCH32/AARCH64 to __aarch64__\n\nNOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.\n\nAll common C compilers pre-define the same macros to signal which\narchitecture the code is being compiled for: __arm__ for AArch32 (or\nearlier versions) and __aarch64__ for AArch64. There\u0027s no need for TF-A\nto define its own custom macros for this. In order to unify code with\nthe export headers (which use __aarch64__ to avoid another dependency),\nlet\u0027s deprecate the AARCH32 and AARCH64 macros and switch the code base\nover to the pre-defined standard macro. (Since it is somewhat\nunintuitive that __arm__ only means AArch32, let\u0027s standardize on only\nusing __aarch64__.)\n\nNOTE: This change is based on below TFA commit\nhttps://github.com/ARM-software/arm-trusted-firmware/commit/402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c\n\nSigned-off-by: Deepika Bhavnani \u003cdeepika.bhavnani@arm.com\u003e\nChange-Id: If2c3dbaeb01d4a9d8cfd95d906e5eaf4ae94417f\n" }, { "commit": "09ed710aab26073c0f066d6c06093a89b19ed338", "tree": "9e8cf9150fedc1fa1c0ce613d7d9fae57173248d", "parents": [ "f9f31112a66ab0d01e677c972271f260d2548db7" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jan 30 14:06:28 2020 +0000" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jan 30 14:06:28 2020 +0000" }, "message": "TF-TF: Store boot parameters\n\nThis patch adds support for storing fw_config and hw_config\naddresses passed as arg0 and arg1 parameters in x0, x1 from\nBL31.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I58ae379bb4a7ef1b6ce60a4e252c65d34dc14464\n" }, { "commit": "35d824e362df862215f987fdf844ccfb8d9ccd92", "tree": "e7f4d50abc003472cf6e2f8fb6cdc72232b6e45f", "parents": [ "584b3cb3aba5423c31496a4f46ea6a58e44dd7d9" ], "author": { "name": "Oliver Swede", "email": "oli.swede@arm.com", "time": "Tue Oct 01 13:50:36 2019 +0100" }, "committer": { "name": "Oliver Swede", "email": "oli.swede@arm.com", "time": "Mon Jan 13 16:04:58 2020 +0000" }, "message": "Make TFTF RFC 4122 compliant\n\nThis is a TFTF backport of a change that makes TF RFC 4122-compliant\nby converting the stored format of UUIDs from machine order (little\nendian) to network order (big endian).\n\nThis patch changes the data structure used to store the values in the\nsame way as in the related change in TF:\n033648652f2d66abe2454a75ded891a47cb13446.\n\nSigned-off-by: Oliver Swede \u003coli.swede@arm.com\u003e\nChange-Id: I052e570b80de61f87a049a08e347a2e5da7f841b\n" }, { "commit": "81042e36ea7603a1c31e8f8984757029bad5db1e", "tree": "713cdf78866ab6ccce8e00d177ce047290425978", "parents": [ "e00ab6c5018a3be8b9837b126784c850a38a906f" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Thu Jul 11 14:49:47 2019 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Dec 23 13:13:34 2019 +0000" }, "message": "debugfs: add debug filesystem tests\n\nChange-Id: Idc36627dabe5af0076fe300ee0c071dce1662a0d\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\n" }, { "commit": "2198e9a1fb8c48c68dc9aa5180ef6ceaca135c29", "tree": "571c838e8334bbff2970330c7db0491fb7478c12", "parents": [ "fc0b20764ec1d613ae41f7985485d8be81c5e526" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Dec 12 14:14:55 2019 +0000" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Dec 12 14:16:13 2019 +0000" }, "message": "TFTF: Add missing D-cache invalidation\n\nThis patch adds missing D-cache invalidation of RW memory\nin tftf_entrypoint to safeguard against possible corruption\nof this memory by dirty cache lines in a system cache as\na result of use by an earlier boot loader stage.\nRef. GENFW-3455\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I595344c307502a6c24c2e62d3e3f2f9d7a810dfa\n" }, { "commit": "caaa306fe24a503c6fa0eb77b2f9ae718d7335d7", "tree": "daa05562daec46c6cb3d1406330636ea3d138033", "parents": [ "640af3a32b645e1b54003081d93739a6d05527dc", "c783c0b82c4803fd666c3e02c1250d8aeca9e378" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 05 15:29:16 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Dec 05 15:29:16 2019 +0000" }, "message": "Merge \"Support for extended register usage in SMCCC v1.2 spec\"" }, { "commit": "640af3a32b645e1b54003081d93739a6d05527dc", "tree": "92d207902d36a0cb6991cd8f0e148c113c4fe503", "parents": [ "535f1be59d83351423aa6e712f8fcf49a7116450", "0f305470237c19a73979d558e740fb90f8449a59" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 29 11:59:13 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 29 11:59:13 2019 +0000" }, "message": "Merge \"TFTF: Add support for FVP platforms with SMT capabilities\"" }, { "commit": "c783c0b82c4803fd666c3e02c1250d8aeca9e378", "tree": "97fe58cabb4ee3ab15363d1663f2fca69fe45b72", "parents": [ "a78c8203e8ce7b901c13ae9fb25d8863c1bcd5bc" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 14 23:52:37 2019 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 21 19:45:07 2019 -0600" }, "message": "Support for extended register usage in SMCCC v1.2 spec\n\nThe new version of SMC Calling Convention spec makes X0-X7/W0-W7/R0-R7\nregisters available for returning results and X1-X7/W1-W7/R1-R7 for\npassing arguments during SMC calls.\n\nThis patch makes necessary changes to support the update in register\nusage and also enhances existing test case to check for expected\nbehavior across SMC call.\n\nLink to the SMCCC spec:\nhttps://developer.arm.com/docs/den0028/c\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I9e5a3e4f9de388cb9a7426b0eae1c0fa1229292a\n" }, { "commit": "a78c8203e8ce7b901c13ae9fb25d8863c1bcd5bc", "tree": "020a08e5301ef72cbad7a68b00304921083b2911", "parents": [ "891a3dd13b63ebf3a290a13f6c0026eb192da953", "2cb7c521285bc1d0f4d7c6841a6ad9b0823d19e0" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Nov 13 07:53:48 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 13 07:53:48 2019 +0000" }, "message": "Merge \"`requested_irq_received` must be initialized for all tests\"" }, { "commit": "0f305470237c19a73979d558e740fb90f8449a59", "tree": "6aeedf76e1b3567e559b8ca88d84b1c0f0d013bb", "parents": [ "2957ff7660eb3b14ed1ee7ade14218332410e3c0" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Oct 29 14:06:54 2019 +0000" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Nov 07 10:30:09 2019 +0000" }, "message": "TFTF: Add support for FVP platforms with SMT capabilities\n\nThis patch adds support for Simultaneously MultiThreaded (SMT)\ncores on FVP models. Number of threads per CPU is passed in\nFVP_MAX_PE_PER_CPU build parameter which can be set either to\n1 or 2. This option defaults to 1.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ib0e2afe429e8f24b8a74ad6ee98750ed1ac121fb\n" }, { "commit": "f1a45f767ad6dc31ebde044884f157a1deddbf3c", "tree": "3e9e306ba52936ca52fa73454eaa133335c5ba46", "parents": [ "2957ff7660eb3b14ed1ee7ade14218332410e3c0" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Tue Oct 08 16:51:45 2019 +0100" }, "committer": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Wed Oct 30 15:10:59 2019 +0000" }, "message": "Aarch32: Secure PMU counter leak tests\n\nThis patch adds Aarch32 support to the PMU counter leak tests.\n\nThese tests attempt to profile the Secure world by configuring\nEL0 system registers such that the PMU is told to increment\ncounters at Secure EL1, Secure EL2 and EL3. The tests fail if\nuseful information was leaked.\n\nThe Secure world defends against this type of attack with a\ncombination of configuring EL3 system registers and saving/restoring\nEL0 PMU registers. Exactly which defense is employed depends on the\narchitecture version.\n\nSigned-off-by: Petre-Ionut Tudor \u003cpetre-ionut.tudor@arm.com\u003e\nChange-Id: I2dcc9e786a18d9859ac089f8008b060d277bee3a\n" }, { "commit": "1a18c4aa386cdcb331d7db6b0e0cb40894505927", "tree": "80096321569c78d9ae80bdb711f5b4294b31c4d2", "parents": [ "6f97b12dac69d3a8ee51fed7af1c32ae33f987c8", "8108c9a3a7e627a7464affb5fdb169202c3012b1" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Oct 21 08:26:49 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 21 08:26:49 2019 +0000" }, "message": "Merge \"Extend SYSTEM_OFF test case\"" }, { "commit": "8108c9a3a7e627a7464affb5fdb169202c3012b1", "tree": "5ef1ae7c9c8e2253744ed436cf5814206550523c", "parents": [ "0012dbc2a841abeff25be8be1113f19073ee4d2c" ], "author": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Fri Sep 06 21:48:56 2019 +0300" }, "committer": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Fri Oct 18 11:52:48 2019 -0500" }, "message": "Extend SYSTEM_OFF test case\n\nExtend SYSTEM_OFF to involve more than just the lead CPU.\n\nThe typical way to use SYSTEM_OFF is to use calls to CPU_OFF on\nall online cores except for the last one, which instead uses SYSTEM_OFF.\n\ntest_system_off_cpu_other_than_lead() case is added to turn on any\nrandom CPU other then lead CPU and perform SYSTEM_OFF from the CPU which\nwas turned ON.\n\nSigned-off-by: Deepika Bhavnani \u003cdeepika.bhavnani@arm.com\u003e\nChange-Id: Ice62d0e7ef0db63ccb030e8dc1a83d9bd55e70f2\n" }, { "commit": "2cb7c521285bc1d0f4d7c6841a6ad9b0823d19e0", "tree": "108656c2ca2165c93c802be3ef98cac2b18106eb", "parents": [ "6f50bd61931ad36152b2a437622593dd11633eb1" ], "author": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Mon Oct 14 12:48:04 2019 -0500" }, "committer": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Mon Oct 14 12:48:04 2019 -0500" }, "message": "`requested_irq_received` must be initialized for all tests\n\nrequested_irq_received is used to confirm if the CPU is\nwoken by IRQ, it is set as part of `requested_irq_handler`.\nDefault it should be cleared for all CPU\u0027s under test,\nun-intialized value resulted in random failure based on\nprevious state of variable.\n\nSigned-off-by: Deepika Bhavnani \u003cdeepika.bhavnani@arm.com\u003e\nChange-Id: Ia3af99a11f3297c2e8fc1ef52e7f18107e2fdfc8\n" }, { "commit": "85926bc3d544111d412472e24cdd86668175c831", "tree": "f6b8ef0e128d0b7a211b601855843d7d5408284d", "parents": [ "6f50bd61931ad36152b2a437622593dd11633eb1" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Wed Oct 09 10:56:39 2019 +0100" }, "committer": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Thu Oct 10 10:06:09 2019 +0100" }, "message": "Bugfix for PMU leakage test\n\nThis patch fixes a bug where integer underflow causes the tests\nto wrongly fail.\n\nSince event counts are register values, they are unsigned in TFTF.\nWhen the event count is less on the SMC being profiled than the\nbaseline SMC event count, subtraction causes an underflow which\ngoes beyond the allowed deviation and makes the test fail.\n\nSigned-off-by: Petre-Ionut Tudor \u003cpetre-ionut.tudor@arm.com\u003e\nChange-Id: I58bc18ca4afd28b6d1b1354a9af9f70d616d2c32\n" }, { "commit": "6f50bd61931ad36152b2a437622593dd11633eb1", "tree": "1523a86b02b5349c08d546b6f3b53d47453f303b", "parents": [ "d5a9e7a17f687edd620cad1bfb702781de3cf92e", "fb003380a01843d0de71ba3374394a798289c64f" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Oct 08 19:16:32 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 08 19:16:32 2019 +0000" }, "message": "Merge \"TFTF: ARMv8.3-PAuth test code enhancements\"" }, { "commit": "fb003380a01843d0de71ba3374394a798289c64f", "tree": "47e9fd3c2ba55dea7e2488e68b11534e865464c6", "parents": [ "1ca3102141319bd514c296ddc256f92e321780a2" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Oct 04 16:13:47 2019 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Oct 08 16:15:59 2019 +0100" }, "message": "TFTF: ARMv8.3-PAuth test code enhancements\n\nThis patch provides the following feature and makes\nmodification listed below:\n- ARMv8.3-PAuth tests now check for all keys being in use\n (e.g. APIAKey when the test suite is built with\n `ENABLE_PAUTH\u003d1` option) and program new key values otherwise.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ifa4a288274822029da585073563c68a1434f5de7\n" }, { "commit": "277fb7628c270c8a891c24dea80350f9c935d4c6", "tree": "05ffa6439c4713d68a8df2d4671139c531a7c751", "parents": [ "1ca3102141319bd514c296ddc256f92e321780a2" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Oct 08 12:10:45 2019 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Oct 08 12:23:38 2019 +0200" }, "message": "Add tests for MTE support\n\nTF-A now has support for the new Memory Tagging Extension in ARMv8.5,\nsee commit 91624b7fed52 (\"Merge changes from topic \"jc/mte_enable\"\ninto integration\").\n\nThis patch creates and enables tests to ensure that the extension is\nbeing properly enabled and that no undesired leakages occur.\n\nChange-Id: I7708fb23a12e2f35a97533f296aaa53db776ddd2\nSigned-off-by: Justin Chadwell \u003cjustin.chadwell@arm.com\u003e\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "1ca3102141319bd514c296ddc256f92e321780a2", "tree": "24f574d395c7abe26334c9b6dc25c7d7dfddfe92", "parents": [ "7d3054a7a194a43546b65b7c5d814b8212e2e01e", "807c61553fde97d41d29713b7e0159536f3ab680" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Oct 04 14:56:26 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 04 14:56:26 2019 +0000" }, "message": "Merge \"Added SYSTEM_RESET test case\"" }, { "commit": "7d3054a7a194a43546b65b7c5d814b8212e2e01e", "tree": "4d9056c3d3cc86fb248ca312c6a8b75b7cd039fb", "parents": [ "7edf1a5ef3153f761c094c035da3eb10501b7247", "719714f1895399e6d64049bed3b03c2597d95402" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Oct 04 14:15:59 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 04 14:15:59 2019 +0000" }, "message": "Merge \"TF-A Tests: Enable PAuth on warm boot path\"" }, { "commit": "719714f1895399e6d64049bed3b03c2597d95402", "tree": "eb40c8e9ffd2dae7a99f42a8a72254c6152a85f3", "parents": [ "e73248e004d971adb6259000d463c929f756a345" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 10:57:53 2019 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Oct 04 14:20:21 2019 +0100" }, "message": "TF-A Tests: Enable PAuth on warm boot path\n\nThis patch provides the following features and makes\nmodifications listed below:\n- `plat_init_apiakey()` function is replaced with `init_apkey()`\n which returns 128-bit value and uses Generic timer physical counter\n value to increase the randomness of the generated key.\n The new function can be used for generation of all ARMv8.3-PAuth keys.\n- Source file `pauth.c` moved from `plat/common/aarch64`\n to `lib/extensions/pauth/aarch64` folder which contains PAuth specific\n code.\n- Individual APIAKey key generation for each CPU on every warm boot.\n- Per-CPU storage of APIAKey added in `tftf_suspend_context` structure.\n- APIAKey key is saved/restored in arch context on entry/exit from\n suspended state.\n- Added `pauth_init_enable()` function which generates, programs\n and enables APIAKey in EL1/EL2.\n- Changes in documentation related to ARMv8.3-PAuth support.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I964b8f964bb541cbb0b2f772cb0b07aed055fe36\n" }, { "commit": "7edf1a5ef3153f761c094c035da3eb10501b7247", "tree": "49fc71545c6e941eebdeb6d5601884a87a7f944a", "parents": [ "e73248e004d971adb6259000d463c929f756a345", "f68ebdb9b45cc7a58f816f153f5e626c898dc0cf" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Oct 04 10:21:36 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 04 10:21:36 2019 +0000" }, "message": "Merge \"Try to leak counter values from secure world.\"" }, { "commit": "f68ebdb9b45cc7a58f816f153f5e626c898dc0cf", "tree": "8eb48a5843eb4acfa86c3066173aaa2b0f898d4b", "parents": [ "0012dbc2a841abeff25be8be1113f19073ee4d2c" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Wed Sep 18 16:13:00 2019 +0100" }, "committer": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Fri Oct 04 09:35:00 2019 +0100" }, "message": "Try to leak counter values from secure world.\n\nThis patch introduces a series of tests that try to leak PMU counter values\nfrom EL3 and S_EL1.\n\nPMU events used:\n\t- CPU cycles via PMU counter PMCCNTR_EL0\n\t- Retired writes to PC via PMU counter PMEVCNTR0_EL0\n\nThis AARCH64-specific patch is for security fix:\nhttps://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1789\n\nThe AARCH32 versions of these tests will be in a future patch.\n\nSigned-off-by: Petre-Ionut Tudor \u003cpetre-ionut.tudor@arm.com\u003e\nChange-Id: Ib27948edadde30272e59a9ab208543703fa078bd\n" }, { "commit": "807c61553fde97d41d29713b7e0159536f3ab680", "tree": "ca02366b01ff30a9c6322a94645b7da43626b602", "parents": [ "0012dbc2a841abeff25be8be1113f19073ee4d2c" ], "author": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Tue Sep 10 23:24:36 2019 +0300" }, "committer": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Tue Oct 01 18:18:55 2019 +0300" }, "message": "Added SYSTEM_RESET test case\n\nSigned-off-by: Deepika Bhavnani \u003cdeepika.bhavnani@arm.com\u003e\nChange-Id: Ie946e83d4365679d6daa1d3b25142a9380cffe2f\n" }, { "commit": "65c4653fb16e46d1ace12c33cbd9d2b4abd9e84b", "tree": "5a9e54f115fc3ae26b72016689a695fe695ddffa", "parents": [ "0012dbc2a841abeff25be8be1113f19073ee4d2c" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Sep 30 11:43:23 2019 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Sep 30 11:43:23 2019 +0100" }, "message": "TF-A Test Framework: Rename `ptrauth` to `pauth`\n\nThis patch renames folder and source file names according to\nmatch with TF-A naming:\n- `ptrauth` folder in `tftf\\tests\\extensions\u0027 renamed to `pauth`,\n- `test_ptrauth.c` source file to `test_pauth.c`\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ida47e175e158e77e33270ee93ba6b3104eb0b5db\n" }, { "commit": "0012dbc2a841abeff25be8be1113f19073ee4d2c", "tree": "7ea4030213ff226769f46328b29717651d8b81ea", "parents": [ "f19b16dba6d867b71cd68bbc1b2f086b14be978c", "2129608e9ab970909c924a934a93a501099ab3bc" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Sep 30 06:47:17 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 30 06:47:17 2019 +0000" }, "message": "Merge \"Separate shutdown and stats after shutdown tests\"" }, { "commit": "f19b16dba6d867b71cd68bbc1b2f086b14be978c", "tree": "6f8b8038f5ed040e7274b462df191cc77e89ce90", "parents": [ "cdba6c95f558304f77b062d58c6c398b3655ef93", "1c97f9418db19942656072435955874c83027124" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Sep 27 15:46:41 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 15:46:41 2019 +0000" }, "message": "Merge \"Allowing zeroes in trusted OS SMC return values\"" }, { "commit": "1c97f9418db19942656072435955874c83027124", "tree": "4289d6f078487d87f03dfd62f834f5df51cb508c", "parents": [ "2676b99a81b4f886b7b79189cbe432705843977b" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Mon Sep 23 16:44:03 2019 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Thu Sep 26 22:51:20 2019 +0200" }, "message": "Allowing zeroes in trusted OS SMC return values\n\nTrusted OSes should preserve or fill by zeroes the values of x1-x3\nregisters across an SMC call in order to prevent data leakage. The\nbehaviour of OP-TEE regarding to this has changed recently from\npreserving values to filling them by zeroes. This patch utilitizes the\nnewly added allow_zeros[] parameter of the smc_check_match function to\nmake the tests compatible with OP-TEE commit 6e558fa94ab0 or later.\n\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\nChange-Id: I52ddfb69261833a3fba76c5f89d27d1ea13043b0\n" }, { "commit": "1b92611fddb4b3360ca1d6db3b91a2c3b7bf99bb", "tree": "8e34cf61f431a255cf7f3004d9e3cce4c6e74530", "parents": [ "2676b99a81b4f886b7b79189cbe432705843977b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Sep 16 14:46:31 2019 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Sep 24 12:10:43 2019 -0500" }, "message": "Fix a false fail for SMC WORKAROUND2 test on Cortex-A76\n\nSome platforms with A76 core do not require the dynamic\nmitigation using SMCCC_ARCH_WORKAROUND_2 call. Test which\nverifies such workaround can be skipped in such scenario.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Iacf27da7181828a2fd1166bd6eeb069ba27da0c5\n" }, { "commit": "2129608e9ab970909c924a934a93a501099ab3bc", "tree": "68fee8b5582b4ba8c366fe13e51f7f9a67ce862b", "parents": [ "2676b99a81b4f886b7b79189cbe432705843977b" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Wed Sep 18 14:53:33 2019 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Mon Sep 23 14:50:12 2019 -0500" }, "message": "Separate shutdown and stats after shutdown tests\n\nCreating new test suite for System shutdown and stats after shutdown\ntests separate from the other manual tests since the others have been\nautomated for some platforms. This test suite is intended to be used\nfor manual testing for the upcoming release.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I3725b28528696fa51d4c1f3af60f8a6e61e1a702\n" }, { "commit": "2676b99a81b4f886b7b79189cbe432705843977b", "tree": "9c16d690c69f9d9cdab479da158472dd7f688e21", "parents": [ "4c213e5eb22269da1a92b53c01a91e8f36439a0e", "89391603d63fd409c18e00e45c864dc9749f2f25" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Aug 16 15:27:53 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 16 15:27:53 2019 +0000" }, "message": "Merge \"Create new xml to split Juno reboot tests\"" }, { "commit": "89391603d63fd409c18e00e45c864dc9749f2f25", "tree": "f8c42818b8d0345db9f19d438597078e37e7e8bd", "parents": [ "6927d85a0429bd247cb76b7cb4201e330fc745a1" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Wed Jul 31 15:33:07 2019 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Aug 08 10:15:51 2019 -0500" }, "message": "Create new xml to split Juno reboot tests\n\nCreating a new xml to separate Juno TFTF reboot tests by those that are expected to pass and\nthose that aren\u0027t (2 RESET2 tests).\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I101de828aeedd33e0601597b70e00056b884ceba\n" }, { "commit": "ee3e7cd720887077ad27f48f4c8e681926c16587", "tree": "b2be6933f915effc206f73faf1ce5a73118751c7", "parents": [ "6927d85a0429bd247cb76b7cb4201e330fc745a1" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Wed Jul 03 16:44:49 2019 +0100" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Thu Aug 01 11:34:18 2019 +0100" }, "message": "ld: Separate code and RO data sections\n\nThis prevents the execution of the read-only data.\n\nThis is done in a similar way in TF-A when the build flag\nSEPARATE_CODE_AND_RODATA is enabled.\n\nThe build flag is probably not needed in TF-A Tests.\n\nChange-Id: I2bdc0237c00377beb2febeb47207770c85036192\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "513be4966f8a9db2fe3166efdc03843f5010cdfe", "tree": "d775a570f1b96baed834b921b7d411c1a6a499d9", "parents": [ "7bdfa0b07a52e487a443394aad89bcd37fbc02a8" ], "author": { "name": "lauwal01", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jul 09 10:58:01 2019 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Fri Jul 26 12:36:12 2019 -0500" }, "message": "Creating separate xml for Reboot tests\n\nSeparating the manual tests xml to only include reboot tests so these\ncan be automated.\n\nChange-Id: Ib1dfe7f215811e9ecb5b8f439965465187b3fe9b\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\n" }, { "commit": "e36bf03bb7ec22a463e8077aace4fda1ea90d87d", "tree": "07e42b8ab8a08c40959c15f5e4a53ce93177c676", "parents": [ "39b397af7566135498e6995102698c0efb0dc90c" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jun 26 15:36:23 2019 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jun 27 11:01:52 2019 +0200" }, "message": "Add missing testsuites in extensive set of tests\n\nThe extensive set of tests is meant to be a superset of the standard\nset. However, 2 testsuites were present in the standard set and were\nmissing from the extensive one.\n\nChange-Id: Idc5d6abd9a2bcdfcfa41421e823a88095ab4e16e\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "d64e1539d505e537282f6c31e42f16474a6b5bda", "tree": "7a7a86f914f48342f8b1e482195df01a2de5b95d", "parents": [ "a3ccf4b875dc5500662262a9a15a29525da04312" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jul 09 13:10:21 2018 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Jun 18 10:53:05 2019 +0100" }, "message": "Add test to measure latencies when turning ON a cluster\n\nChange-Id: If698dc76c1873fb79ffe63ac6ee0c808186310ac\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "cae91ca61cc36462c3e1b639c2725535a0c05df4", "tree": "7bc7490da8fab528fc151eb712adc02efa5a414d", "parents": [ "68759a8015fc997aeeb2fb0caf6b55bbbec73d02" ], "author": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Sun May 12 16:06:09 2019 +0100" }, "committer": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Fri May 24 14:10:51 2019 +0100" }, "message": "Fix AMU non-zero counters test\n\nThe condition checked in one of the AMU tests (AMU counters always\nnon-zero) does not always hold. The counter that counts the memory stall\ncycles, under certain circumstances, can be zero. Hence, the test is\nadjusted accordingly and, consequently, renamed.\n\nChange-Id: I8c7300481c2b45825101ee87f61c68c2ab51758a\nSigned-off-by: John Tsichritzis \u003cjohn.tsichritzis@arm.com\u003e\n" }, { "commit": "68759a8015fc997aeeb2fb0caf6b55bbbec73d02", "tree": "25fb8d86e88f96e86ed9cdfa50f717662b641ff0", "parents": [ "16a32f7e388fc3246b1e1d06c815a0fa09cd7818" ], "author": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Sun May 12 15:10:27 2019 +0100" }, "committer": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Mon May 20 12:43:55 2019 +0100" }, "message": "Remove unexecuted code for AMU group 1 counters\n\nThis patch removes from the AMU tests the part that iterates over group\n1 counters. The reasons for this are the following:\n\n1) Currently the AMU tests are executed only in FVP but FVP doesn\u0027t\nhave/expose group 1 counters.\n\n2) Even if some platform implements group 1 counters in the future, we\ndon\u0027t know what they will be counting. As such we cannot know what the\nvalid values for those counters will be. Hence, we can\u0027t establish a\nspecific test at this moment to validate the group 1 counter values.\n\n3) Even now that the loop exists in the code, the macro defining the\ngroup 1 counters is defined as zero. Which means that the loop is\nalready not executed, despite being there (dead code).\n\nHowever, the architecture defines how group 1 counters should be\nimplemented. For this reason, the assembly helper functions that access\nthe group1 counters are left intact. This will allow us to easily extend\nthe AMU tests again in the future to include group 1 counters.\n\nChange-Id: I5a6f119c7e817de9dc5e510c3fadd008820bd564\nSigned-off-by: John Tsichritzis \u003cjohn.tsichritzis@arm.com\u003e\n" }, { "commit": "96e250320b9c1cec90946e93d87f27fdafac5092", "tree": "9805a9ad3d674ccd3d5d2f7dc83696955a1c947d", "parents": [ "1f018ba629bd534a14bbf133d4e9fa61e2f09686" ], "author": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Tue May 07 10:42:22 2019 +0100" }, "committer": { "name": "John Tsichritzis", "email": "john.tsichritzis@arm.com", "time": "Tue May 07 10:51:44 2019 +0100" }, "message": "Fix AArch32 build error\n\nPointer authentication code should be conditionally compiled only if\nTFTF is built for AArch64 since AArch32 doesn\u0027t support pointer\nauthentication. This was previously causing a compilation error.\n\nChange-Id: I97a0ea66f562cf2ebb41478b1b31a26bcaf815b2\nSigned-off-by: John Tsichritzis \u003cjohn.tsichritzis@arm.com\u003e\n" }, { "commit": "5394feaf2190cb0a80ff0b633d2702a9add337a2", "tree": "140067e4ede341c460971103a6bb3adbec3de091", "parents": [ "26b3864c09add32f2b5a8e3798c9731fc856e9a5" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Apr 17 13:12:10 2019 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Apr 17 13:14:48 2019 +0100" }, "message": "quark: Introduce simple TFTF test\n\nIntroduce test to verify that Quark is present in the system.\n\nChange-Id: Ia31e65e737b8909f7caecae830fcb217e88a9b01\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "26b3864c09add32f2b5a8e3798c9731fc856e9a5", "tree": "224a51e581518b4acb6d1e8b960fee5134474cae", "parents": [ "1d03668d7ebe6286b70808097d80b72d624be0a2" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Mar 28 13:16:04 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Apr 17 13:14:48 2019 +0100" }, "message": "quark: Introduce Quark Secure Partition\n\nTest partition designed to have a virtual address space as small as\npossible in order to test the extension ARMv8.4-TTST. This Secure\nPartition doesn\u0027t have print capabilities. The only service it provides\nis one that returns a magic number to verify that it has been loaded.\n\nChange-Id: I431f6c65f2926d486836d12ddfefe05e83b0c47f\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "6a6f48338312f1b8e5637fa85d7942e6bb9d8bab", "tree": "758dea2b85bfd8e97a5d86f65b73a81a7f93d15e", "parents": [ "8790f025e12065ccccfe4d19fdcc672c80aa784b" ], "author": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Mon Apr 08 15:46:36 2019 +0100" }, "committer": { "name": "Joel Hutton", "email": "Joel.Hutton@arm.com", "time": "Fri Apr 12 15:43:03 2019 +0100" }, "message": "Makefile: Enable strict align arch minor version\n\nAdd -mstrict-align flag, and -march minor version. These are needed to\nprevent compilers generating unaligned accesses and enable\narchitectural features respectively.\n\nEnable the SCTLR.A and SCTLR.SA alignment checks in all images.\n\nTF test has several cases of code which enable the alignment checks.\n\nChange-Id: I9a0413786caf94d0abf376aa1b4fb54fc7f2f355\nSigned-off-by: Joel Hutton \u003cJoel.Hutton@Arm.com\u003e\n" }, { "commit": "8790f025e12065ccccfe4d19fdcc672c80aa784b", "tree": "e5548628d170748a3f2d98973b4db315a76c88ef", "parents": [ "29ef1dd13dfb989008fc98f7f7c17f163e0479bf" ], "author": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Fri Mar 15 14:47:02 2019 +0000" }, "committer": { "name": "Joel Hutton", "email": "Joel.Hutton@Arm.com", "time": "Mon Apr 08 14:34:42 2019 +0100" }, "message": "Add unit tests for Pointer Authentication\n\nAdd unit tests to:\n Test access to the key registers.\n Use the pointer authentication instructions.\n Call psci version and check the EL3 pointer authentication keys\n aren\u0027t leaked.\n Make a tsp call and check the secure world keys aren\u0027t leaked.\n\nChange-Id: Ic7940757e6f9fc905ccef8c035e0c22b47b35cd7\nSigned-off-by: Joel Hutton \u003cJoel.Hutton@Arm.com\u003e\n" }, { "commit": "372b675ac20e2addc1c13f36ce61e5f90749f40d", "tree": "e788daebf2b14c2ea79f1b4763aac97b010d2203", "parents": [ "fae77720145bf50b0965b90d0055015a21923aef", "f152f8f480f36b448d1f8b02e4902ae30523cca5" ], "author": { "name": "Antonio Niño Díaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Apr 04 10:06:38 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 04 10:06:38 2019 +0000" }, "message": "Merge changes from topic \"an/xlat-v2-tests\"\n\n* changes:\n xlat v2: Alignment tests\n xlat v2: Stress tests\n Increase virtual address space size in AArch64\n xlat v2: Add unit tests\n" }, { "commit": "fae77720145bf50b0965b90d0055015a21923aef", "tree": "a11e91b812f0c1bd4a62fd3aa644b82947877907", "parents": [ "88e96a1d790ca47c500a254dea32426e41e4e369" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Thu Mar 07 10:17:15 2019 +0000" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Apr 01 11:08:40 2019 +0100" }, "message": "Introduce test for SVE support\n\nWhen SVE extension is enabled, test that it correctly performs simple\noperations.\n\nGenerating SVE instructions requires O3 compilation optimization. Since\nthe build structure does not allow compilation flag modification for\nspecific files, the function testing SVE support has been pre-compiled\nand added as an assembly file.\n\nChange-Id: Id9ba7d9e1de9bcbae3065cad2dd3e1dbe87ef03a\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "f152f8f480f36b448d1f8b02e4902ae30523cca5", "tree": "76ff0aa3a6e67366fa3d4e5cc5381955788e9941", "parents": [ "402b269ccd3926feab74ba4dfb39d6f0dc703c4d" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Oct 05 15:18:45 2018 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Mar 29 13:00:08 2019 +0000" }, "message": "xlat v2: Alignment tests\n\nChange-Id: I6a689998a74f7841c668ccbb4be7b03d36b355b2\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "402b269ccd3926feab74ba4dfb39d6f0dc703c4d", "tree": "9dbcc4070eb546b9b5234b0f59f9deb6f4b6db5a", "parents": [ "f00940b6a36458d0a321e1defbe2599453f29913" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Oct 05 15:11:38 2018 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Mar 29 13:00:08 2019 +0000" }, "message": "xlat v2: Stress tests\n\nChange-Id: I2b5de1b884db78eea6d83ab8b31de32b5c23b316\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "54959b0c9989faccec05d420aee14ff865d60fab", "tree": "a73e3908a4a82b89ff2d31f5cb346411305dc751", "parents": [ "88e96a1d790ca47c500a254dea32426e41e4e369" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Mar 29 12:59:35 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Mar 29 12:59:35 2019 +0000" }, "message": "xlat v2: Add unit tests\n\nAdd basic unit tests for the xlat tables library v2.\n\nChange-Id: I814470d2aceec8a7d1da5190c7c5b355178b1a54\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "3b725db7bb951cb43e9119fbd96cf60eb2e23a92", "tree": "98bd1da412d0a9d2845987c763565941b7de2384", "parents": [ "b4ddca80b1b20bf2f1870e9623b18e5c11139847", "eb1a41684e7cfd40beeff12a518a5e7c23d9c8c7" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 21 15:54:38 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 21 15:54:38 2019 +0000" }, "message": "Merge changes from topic \"an/fix-spm-mm\"\n\n* changes:\n SPM-MM: Re-enable disabled tests\n SPM-MM: Fix call preemption test\n" }, { "commit": "eb1a41684e7cfd40beeff12a518a5e7c23d9c8c7", "tree": "0fba84f97074295030779c22f546b70356cdccff", "parents": [ "81d507ef3c46760d1a67460eaeaac20cb50ee48c" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Mar 20 16:03:49 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Mar 21 13:54:52 2019 +0000" }, "message": "SPM-MM: Re-enable disabled tests\n\nThe tests are actually passing now.\n\nChange-Id: I0f9ef11dabded51daf791c42ce0e22ff222425db\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "81d507ef3c46760d1a67460eaeaac20cb50ee48c", "tree": "18af1e706cd8af726df6a9ca964ba106dd0d132d", "parents": [ "f2218e7b6a4f8c2c3d6db00703caad95f5e5b157" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Mar 21 13:49:23 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Mar 21 13:54:52 2019 +0000" }, "message": "SPM-MM: Fix call preemption test\n\nThe timer was being set up for 1 ms rather than 1 second.\n\nChange-Id: I16d6ea69d42abf28dc9591e97d6bfb302d5f8127\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "b4ddca80b1b20bf2f1870e9623b18e5c11139847", "tree": "7538138fb153c315c8103eb2191c93dd563a1754", "parents": [ "f2218e7b6a4f8c2c3d6db00703caad95f5e5b157", "9c9f92c4c4cd07ea75ea72a42f15b32ed4c01bf0" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Mar 20 17:28:50 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 20 17:28:50 2019 +0000" }, "message": "Merge changes from topic \"an/pauth\"\n\n* changes:\n Add ARMv8.3 pointer authentication support\n Remove pointer authentication test\n" }, { "commit": "f2218e7b6a4f8c2c3d6db00703caad95f5e5b157", "tree": "83f72bbabcabae7e25e82c3192d27718dea21f67", "parents": [ "960906b2d8fc2596f257b55606c69505d2bf1130" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Tue Mar 19 10:59:11 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Tue Mar 19 11:22:43 2019 +0000" }, "message": "Reintroduce Cactus-MM and SPM-MM tests\n\nThe code has been taken from commit 99f4fd283b6f (\"cactus: Use UART2\ninstead of UART0\") and modified slightly to be integrated in the current\nmaster.\n\nThere are three tests that are failing in the CI. They have been\ndisabled for the time being:\n\n- mem_attr_changes_tests() in cactus_main() in the file\n spm/cactus_mm/cactus_mm_main.c.\n\n- Two tests in the file tftf/tests/tests-spm-mm.xml.\n\nChange-Id: I6332cbff1cefeb82b9447fae1b613879e65186a1\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "960906b2d8fc2596f257b55606c69505d2bf1130", "tree": "4954a1fe21024c8f407e0a74964f64119fe76788", "parents": [ "bf8f1b887d2f03757ca6d06ce21e455e4fd5e71c" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Feb 08 11:32:05 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Mar 18 14:23:35 2019 +0000" }, "message": "Check arguments when building manual tests\n\nManual tests require setting USE_NVM\u003d1 and NEW_TEST_SESSION\u003d0\notherwise they will not function properly (as test results will\nnot be preserved across reboots). We should check that these\nvariables have the required values during the build.\n\nChange-Id: I72fc8a4badf107fe2ebd6bfb88631828e14a77b3\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "bf8f1b887d2f03757ca6d06ce21e455e4fd5e71c", "tree": "599434ad1c200ac1967fbc1c87310398ba75c2a2", "parents": [ "f1837f87275147f6bf8c277445367b9d5a9c805d" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Mar 18 13:42:54 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Mar 18 14:23:35 2019 +0000" }, "message": "Remove tests-fwu.mk from tests-standard.mk\n\nThe FWU test components are being built as part of the\ntests-standard.mk configuration but tests-standard does not\nactually run any FWU tests (see tests-standard.xml). These FWU\ntest components do not need to be built.\n\nChange-Id: I11a9012fcf79f4066947b0b2801c64d053f38d42\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "f1837f87275147f6bf8c277445367b9d5a9c805d", "tree": "30f56073a5b481254e2c6029deb2940e262e8748", "parents": [ "d606e7485b57f2e2dac769e3dfcb651840e4024b" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Feb 08 11:51:46 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Mar 18 14:23:35 2019 +0000" }, "message": "Remove manual tests from tests-standard.mk\n\nThese tests require build variables to be set to non-default values\n(USE_NVM\u003d1 and NEW_TEST_SESSION\u003d0). This conflicts with other tests that\nare part of tests-standard (the default set of tests) and so the\nproposed solution is to remove them from this set.\n\nChange-Id: Id54148aab9410002dace33ad595ac1b0cf4678ca\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "9c9f92c4c4cd07ea75ea72a42f15b32ed4c01bf0", "tree": "50e83b79b1c811db525e3c2e64b99951a59fed4e", "parents": [ "4ac64eb32c8fcb3a00aecda6c943768505e3282a" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Mar 13 13:57:39 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Mar 13 13:57:39 2019 +0000" }, "message": "Add ARMv8.3 pointer authentication support\n\nARMv8.3-PAuth adds functionality that supports address authentication of\nthe contents of a register before that register is used as the target of\nan indirect branch, or as a load.\n\nThis feature is supported only in AArch64 state.\n\nThis feature is mandatory in ARMv8.3 implementations.\n\nThis patch adds the functionality needed for platforms to provide\nauthentication keys for the TF-A Test Framework, and a new option\n(ENABLE_PAUTH) to enable pointer authentication in the framework itself.\nThis option is disabled by default.\n\nPointer authentication support has been added to FVP.\n\nChange-Id: Id2d5c978deb68ae60107879f1c3d0b231cba9f42\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "4ac64eb32c8fcb3a00aecda6c943768505e3282a", "tree": "0776c82d8df17eeb715a090cde8e3654ab94909a", "parents": [ "d606e7485b57f2e2dac769e3dfcb651840e4024b" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Feb 06 13:05:18 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Wed Mar 13 13:54:57 2019 +0000" }, "message": "Remove pointer authentication test\n\nThis test only makes sure that the pointer authentication registers can\nbe read, which isn\u0027t a useful test now that the TFTF is going to support\nusing pointer authentication.\n\nChange-Id: I01735677353ab08ba26f6faad1b900d98654c0d2\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "d6e806d35599bf003c575d7d113367b8de910448", "tree": "cd4ccb353ae8b91e6504057c20eaf641cd13ab63", "parents": [ "602b7f58dd7668411c8a4032652b4552bd7fe934" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 14:34:26 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Mar 04 12:20:48 2019 +0000" }, "message": "libc: Update makefiles\n\nAdded includes and sources of libc to the makefiles.\n\nChange-Id: I8e84db9634e0df7d51caa5c5858311672dd3a8d1\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "602b7f58dd7668411c8a4032652b4552bd7fe934", "tree": "675e0939d19e306e01703359d7b8661d4f312d32", "parents": [ "8a573de8dda42258b747e56f19190311ea090d29" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 14:13:43 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Mar 04 12:20:38 2019 +0000" }, "message": "libc: Update includes\n\nReflect the changes in the structure of libc.\n\nNB: the include of stdarg.h in nvm_results_helpers.c is not in alphabetical\norder because it needs to be included before stdio.h. Fixing this would require\nfurther changes.\n\nChange-Id: I07f62a3450802833408ff3e1f950fd3b643e5e33\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "6d7047dcb24325e0a782b47c0ad507b6a5b32746", "tree": "7e8496ca50786a6f38e42a9d00c944c73738f1b7", "parents": [ "09a00ef98c6108fec75dafcc7dbdddacb2ee2e91", "a43b003acd6c8e8991a57e993f7bfcdfaa04f980" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 28 07:40:15 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 28 07:40:15 2019 +0000" }, "message": "Merge changes from topic \"sb/exception-dump\"\n\n* changes:\n Dump some registers when hitting an unexpected exception\n Improve readability of TFTF exceptions code\n" }, { "commit": "09a00ef98c6108fec75dafcc7dbdddacb2ee2e91", "tree": "77b585708a4fd850f0dac3a3f0fcaf34576fa8c9", "parents": [ "9e550b6f75f064b53d74a4ad3c8672332d87451c" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Jan 11 13:12:58 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 25 08:23:20 2019 +0000" }, "message": "Sanitise includes of include/drivers across codebase\n\nEnforce full include path for includes.\n\nThe reason for this change is that having a global namespace for\nincludes isn\u0027t a good idea. It defeats one of the advantages of having\nfolders and it introduces problems that are sometimes subtle (because\nyou may not know the header you are actually including if there are two\nof them with the same name).\n\nChange-Id: I45e912b16c9fff81f50840dad7e7f90ed6637b2a\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "a43b003acd6c8e8991a57e993f7bfcdfaa04f980", "tree": "52e7bbdc784f3fcd6cf629d76b21b692acca1652", "parents": [ "e760449e0759d351b849c5934cfa2ee06bde89a7" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 14:04:32 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jan 24 08:59:54 2019 +0100" }, "message": "Dump some registers when hitting an unexpected exception\n\nAt the moment, no information is printed on the UART whenever we hit\nan unexpected exception, not even an error message. This is not great\nfrom the user\u0027s perspective, who has got no idea of what is going on.\n\nNow we print an error message, as well as the state of some of the\nregisters. This includes general-purpose registers, as well as some\nsystem registers.\n\nThis is implemented for TFTF running:\n\n- in AArch64 state, at EL2;\n- in AArch64 state, at NS-EL1;\n- in AArch32 state.\n\nWe might want to dump more registers in the future but this patch\nat least provides a basis we can build upon.\n\nAlso, the SP_EL0 has been removed from the list of registers saved in\nthe CPU context because TFTF always uses SP_ELx and does not touch\nSP_EL0 at all.\n\nChange-Id: I56e4afa917b53b5ccccff1d5d09ac8ccfaa6ae49\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "e760449e0759d351b849c5934cfa2ee06bde89a7", "tree": "52d0550dfa247e432bff782182544bae38f5afbd", "parents": [ "9e550b6f75f064b53d74a4ad3c8672332d87451c" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 09:37:28 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jan 24 08:59:54 2019 +0100" }, "message": "Improve readability of TFTF exceptions code\n\nThe only exceptions that TFTF expects are IRQs from the current\nexception level. All other exceptions are unhandled and put the TFTF\ninto an irrecoverable state. Introduce an unhandled_exception macro\nthat makes it clearer.\n\nChange-Id: Ia64600d540007a648c14d8663c91c60c8591eae6\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "a2d516fc5215973b4df38fe072fb68a8899e4ae4", "tree": "18da625a1492e7d41a1dc89fab61e50d884354b9", "parents": [ "c1617386e332973c334b097ad7e188437ef8e1a7" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 16:34:19 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 16:40:07 2019 +0100" }, "message": "Always print file and line number in panic/unreachable macros\n\nRelease builds used to have a special variant of these macros without\nthe source code location information. This kind of mechanism is useful\nwhen writing software that needs both a development and production\nversion so that the source code information is not leaked when the\ndevice is in the field.\n\nHowever, in the context of TF-A Tests, it makes little sense, as it\u0027s\nunlikely somebody would ever ship a device with TF-A Tests installed\non it.\n\nChange-Id: Ic14ad87c2756762807ee71142f21d6973233144e\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "c1617386e332973c334b097ad7e188437ef8e1a7", "tree": "e1c0c7eaa58f802523f21037db0750d28d55a628", "parents": [ "3951dd9009a5bc3c5552dcc8dddcd80653ac8613", "d101967f4f9c36d18ee04bd8d9b735dc47a4fcda" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 11:56:16 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 15 11:56:16 2019 +0000" }, "message": "Merge changes from topic \"sb/exceptions\"\n\n* changes:\n Rework IRQ vector code\n Add CFI debug info to vector entries\n Improve readability of exceptions stubs code\n Fix comments in AArch64 exceptions code\n" }, { "commit": "3951dd9009a5bc3c5552dcc8dddcd80653ac8613", "tree": "94263ebf055db8a18c9cdaef293ee86888be54cb", "parents": [ "a17e77c53ba160e0394c331e6c37a4f3b271a78b" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jan 10 11:09:54 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jan 15 10:48:49 2019 +0100" }, "message": "Move unstable tests to a separate pool of tests\n\nSome tests have proven unreliable over time. They often time out and the\nroot cause of the problem is unknown as of today.\n\nThis root cause needs to be investigated and fixed but until then, this\npatch isolates these tests in their own pool. This allows us to set\ndifferent trust levels in our CI:\n - The stable tests are trusted to call out the validity of a patch.\n - The unstable tests are only informative.\n\nChange-Id: Ia8ebb5a29a523ef3a1f324dbd3ddddac02254fd8\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "d101967f4f9c36d18ee04bd8d9b735dc47a4fcda", "tree": "50d51deaa8b32f96037fd6e07e2db3732757be81", "parents": [ "452f360545f0b4d19720c2dfbaf80cf48c1aa3de" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 11 18:39:24 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 16:48:28 2019 +0100" }, "message": "Rework IRQ vector code\n\nJump straight to a function so that we are not constrained in the\n32-instruction limit. Turn the code saving and restoring\ngeneral-purpose registers into a macro (as opposed to a function),\nthus removing the need to save the link register before anything else.\n\nOverall, this makes the code more straight-forward as we can more\nclearly see that registers are saved from x0 to x30 (in this order)\nwithout any magic twist.\n\nChange-Id: Ic70ceee62bec5efc6f6b6a23a7bd4c1d6c2f8a97\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "452f360545f0b4d19720c2dfbaf80cf48c1aa3de", "tree": "e0a61d5a614b9f7193a0b53357f346e7ec8f04c3", "parents": [ "80ddcc3286b61f40015b30296a47baf47c3e8fd0" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 13:49:22 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 13:51:17 2019 +0100" }, "message": "Add CFI debug info to vector entries\n\nThis is based on TF-A commit 31823b6961d35a5d53e81d3bf4977ad7b2be81dd.\n\nAdd Call Frame Information assembler directives to vector entries so\nthat debuggers display the backtrace of functions that triggered a\nsynchronous exception. For example, a function triggering a data abort\nwill be easier to debug if the backtrace can be displayed from a\nbreakpoint at the beginning of the synchronous exception vector.\n\nDS-5 needs CFI otherwise it will not attempt to display the backtrace.\nOther debuggers might have other needs. These debug information are\nstored in the ELF file but not in the final binary.\n\nChange-Id: I1129419f318465049f53b5e41c304ea61fa44483\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "8b170a247ef0d45d0186cdc8b22257a9ee1f2a3f", "tree": "76b5e04a5964b6d658e0564ad2ac08131499abac", "parents": [ "a17e77c53ba160e0394c331e6c37a4f3b271a78b" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 11 18:47:26 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 14 13:51:15 2019 +0100" }, "message": "Fix comments in AArch64 exceptions code\n\nChange-Id: I88216c14056bee4405233b3e47b59cd3ea355322\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "dddec6bc4834e4e83c7d6d3a24abcc4dd6b631e5", "tree": "3225788c372e74a584857ad2b4f7cd6515629d09", "parents": [ "9e7d37e7d4de365e56c4a6e1a38950378ae0c841" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Dec 18 15:45:01 2018 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 07 16:31:16 2019 +0000" }, "message": "Explain why we set HCR.TGE bit\n\nChange-Id: Id55a62e8610f0b162a26a0eeb8f69e4a87910ed7\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "9e7d37e7d4de365e56c4a6e1a38950378ae0c841", "tree": "eab764b40f2ba4413f967b14d3c9bac6565ebbbe", "parents": [ "48ea56b221c113834a02334a71661dbeea26a091", "c5d315e6eecedfec609870f0cce6e31d927850cf" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 07 15:56:12 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 07 15:56:12 2019 +0000" }, "message": "Merge changes from topic \"sb/smc-tests-tos\"\n\n* changes:\n Relax SMC tests when Trusted OS is present\n Make UUID buffer optional for is_trusted_os_present()\n" }, { "commit": "48ea56b221c113834a02334a71661dbeea26a091", "tree": "bfe75e58d8032a54cb54195509d5c3e84b8d52c2", "parents": [ "bbdb2762062547ef279256d0163e4d743f21474a", "10a0254708efb96397890ce53265adac3fc94153" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 07 15:55:07 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 07 15:55:07 2019 +0000" }, "message": "Merge changes from topic \"an/spm\"\n\n* changes:\n SPM: Test interrupt preemption\n SPM: Test blocking requests while busy\n" }, { "commit": "c5d315e6eecedfec609870f0cce6e31d927850cf", "tree": "623ae84f4e89b287e8ac6d95ae4466d1dbbb2e91", "parents": [ "cab5e3693738743255bd9a8a8f36dccdd74ca495" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 07 10:44:32 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 07 13:00:26 2019 +0100" }, "message": "Relax SMC tests when Trusted OS is present\n\nWhen receiving an invalid SMC function ID, the Trusted OS is free to\nreturn any error code in x0 but it should at least preserve the values\nof x1-x3. The SMC tests expected the Trusted OS to return -1 in x0,\nwhich is too strong of an assumption. This patch relaxes them to check\nx1-x3 but ignore x0.\n\nChange-Id: I6d516319afeaee9af6aa3674a48c13dba6f7af69\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "bbdb2762062547ef279256d0163e4d743f21474a", "tree": "4d6cda2ba961c39aeecd9bc870581ff149060821", "parents": [ "3f556ebf53fb3c25eb1e85110643a593e5fe5d26", "39caa2cfde26781c98b44f1696f684e58cd4a287" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 04 11:52:41 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 04 11:52:41 2019 +0000" }, "message": "Merge changes from topic \"sb/init-code\"\n\n* changes:\n Share AArch32 arch. init code between cold/warm boot code\n Rework TFTF AArch64 entry point code\n" }, { "commit": "39caa2cfde26781c98b44f1696f684e58cd4a287", "tree": "a30fbc9de8455665e14cb19e8fcaca249da2313e", "parents": [ "a1948da02c0dbc90264d7664ef2799b3d2f87710" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Dec 18 10:53:34 2018 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 04 11:52:08 2019 +0000" }, "message": "Share AArch32 arch. init code between cold/warm boot code\n\nChange-Id: I3062f88a09b481f7cb8d03210ea99e33a6a98774\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "3f556ebf53fb3c25eb1e85110643a593e5fe5d26", "tree": "1986260a41935607f45ec86213fee4c5206ec737", "parents": [ "1779506e5be07e4e136d35b75d2672680067fdb6" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Nov 16 14:00:40 2018 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jan 03 10:51:21 2019 +0100" }, "message": "Add some tests for all types of SMCs\n\nExercise all combinations of SMCs: fast or yielding, SMC32 or SMC64\ncalling convention, from a 32-bit caller or a 64-bit one.\n\nChange-Id: I6d23549818db7f1b3fd0cb4b46e5a592b04b5289\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "1779506e5be07e4e136d35b75d2672680067fdb6", "tree": "36783422ce62b29e98899d0c14ab99993536caa0", "parents": [ "485cee0e136763febc859b8eddd5c54520987725" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Dec 13 16:02:41 2018 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jan 03 10:51:21 2019 +0100" }, "message": "Rename SMC first argument\n\n\u0027fid\u0027 (short for \u0027function ID\u0027) makes for a more explicit name.\n\nChange-Id: I41d90c39979162142b0377a68f4be90dc31de253\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "485cee0e136763febc859b8eddd5c54520987725", "tree": "c578ab7cb2a16dd3f7687c98d5ce62ad8732a9ae", "parents": [ "ba7695b39bb82d5ceba093b0c18dd38cc9af61c3", "dfa5ed9fc80f7aad9a0b284a1844aae3251fe75e" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Dec 21 09:48:17 2018 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 21 09:48:17 2018 +0000" }, "message": "Merge changes from topic \"sb/terse-output\"\n\n* changes:\n Remove redundant error message in tftf_initialise_timer()\n Remove prints from VExpress NOR flash driver\n Remove prints in get_overall_test_result()\n Remove SHELL_COLOR build flag\n Do not print CPU MPID in mp_printf()\n Use vprintf() inside mp_printf()\n Add vprintf() in standard C library\n" } ], "next": "10a0254708efb96397890ce53265adac3fc94153" }