)]}' { "log": [ { "commit": "cb38be8da24189798aad6b02ff95c7c30cbc2fce", "tree": "a722f9f0fb5aaa48e685ddafccac89ab40fb4ce2", "parents": [ "80b143f91f178b4b3e62015aba2a9b510f0af20c" ], "author": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Thu Nov 06 12:06:46 2025 -0600" }, "committer": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Fri Nov 07 11:09:12 2025 -0600" }, "message": "test(SMCCC): update SMCCC_ARCH_FEATURE_AVAILABILITY test\n\nUpdate the SMCCC_ARCH_FEATURE_AVAILABILITY test\nto include FEAT_MEC support.\n\nSince MDCR_EL3.EnPM2 bit is set unconditionally, even when\nFEAT_PMUv3p9 is not present, modify the check to be always\npresent.\n\nSigned-off-by: Sona Mathew \u003cSonaRebecca.Mathew@arm.com\u003e\nChange-Id: Ifd727c15fe03afce5fcb2c04ee1d19b7b06a3608\n" }, { "commit": "80b143f91f178b4b3e62015aba2a9b510f0af20c", "tree": "01c334accfb4b579553d628632229284b74594a9", "parents": [ "062073104f71dde3054755add4b76519b7526811", "0860f29e52eaf265cf824c1bd5104ca8197c4d54" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Nov 05 13:51:09 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 05 13:51:09 2025 +0000" }, "message": "Merge \"feat(smccc): add FEAT_EBEP to FEATURE_AVAILABILITY\"" }, { "commit": "0860f29e52eaf265cf824c1bd5104ca8197c4d54", "tree": "01c334accfb4b579553d628632229284b74594a9", "parents": [ "062073104f71dde3054755add4b76519b7526811" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Nov 04 10:14:31 2025 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Nov 04 13:21:06 2025 +0000" }, "message": "feat(smccc): add FEAT_EBEP to FEATURE_AVAILABILITY\n\nChange-Id: Ia545d5c226d3504cd821c704e765542b7d2b838c\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "062073104f71dde3054755add4b76519b7526811", "tree": "cd369dc6cc274616abe1e0f9560470a6c66066aa", "parents": [ "355710eb888e89fb739c5492639ddbdc7c0e9897", "66e1ec89263e3454eb5a7210cad96df11ba75abb" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Nov 04 09:56:29 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 04 09:56:29 2025 +0000" }, "message": "Merge changes from topic \"bk/gicv5_full\"\n\n* changes:\n feat(realm): set the PMU IRQ number depending on GIC version\n feat(fvp): set the timer IRQ number depending on GIC version\n refactor(gic): defer IRQ handler management to the GIC driver\n refactor(gic): make the concept of SGI generic\n feat(gicv5): add a GICv5 driver\n feat(gicv5): add GICv5 instructions and register accessors\n" }, { "commit": "66e1ec89263e3454eb5a7210cad96df11ba75abb", "tree": "cd369dc6cc274616abe1e0f9560470a6c66066aa", "parents": [ "9134748e4a1faabd97cb29fa71069cd656107a4a" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 16:09:52 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 15:17:24 2025 +0000" }, "message": "feat(realm): set the PMU IRQ number depending on GIC version\n\nDespite the PPI number being the same, the INTID is different - it needs\nto be labelled as PPI on GICv5. Add a helper to switch this.\n\nChange-Id: I600ab121135b0826f8405202de222943392c36ec\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "9134748e4a1faabd97cb29fa71069cd656107a4a", "tree": "4d56558da5148277f1dd71831263000367062549", "parents": [ "055adff8d7e5431174672c7aac0bc530c4e7a778" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:53:57 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "feat(fvp): set the timer IRQ number depending on GIC version\n\nChange-Id: I8039ee2104effdf052141e52059d45675ca09127\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "055adff8d7e5431174672c7aac0bc530c4e7a778", "tree": "2968cec4c85ea200c4838a268ccd13dba9a5c7ad", "parents": [ "6d144db95cd1ee317bf66efade0fd5d4e0909c3c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:34:12 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "refactor(gic): defer IRQ handler management to the GIC driver\n\nInterrupt groups are not generic between GIC versions. SGIs and eSPIs\ndisappear, while SPIs and LPIs subtly change function. So abstract all\nof this away and hide it behind each individual GIC driver.\n\nChange-Id: Iaa55014b2940969508b290736c43134688e8c422\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "6d144db95cd1ee317bf66efade0fd5d4e0909c3c", "tree": "0b57d1214fe208e82a5b56ba03b06cec0074700f", "parents": [ "e5629bd4c6ab6088e21e7f4e2f4a27495945e21a" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:04:53 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "refactor(gic): make the concept of SGI generic\n\nSoftware generated interrupts (SGIs) are a GICv2/3/4 concept. However,\nthey are deeply embedded in how TFTF handles wake ups. This patch\npromotes the SGI to an abstract concept that can be performed\nindependently of the interrupt controller, largely the same as it is\nused today. To do that the interrupt interface for an SGI is separated\nfrom the general IRQ and each SGI is assigned a linear index from 0\nonwards. Translating from SGI to IRQ is done via a hook in arm_gic.c\nthat will be multiplexed to the appropriate driver. For GIC \u003c\u003d v3 this\nis a thin wrapper around the identity mapping as SGIs map to INTIDs from\n0 through 15. For GICv5 the mapping is different and an SGI is an LPI\nand calculated as recommended by chapter 2.5 in the spec.\n\nAdditionally, the definitions of SGI numbers are made generic as no\nplatform has utilised the difference.\n\nChange-Id: I7e6a5fbe655098c5e235b98f6dda8a14619a5904\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "e5629bd4c6ab6088e21e7f4e2f4a27495945e21a", "tree": "4034af170e7cd7109f9e4fdf2ba91d8438f2f495", "parents": [ "b731b11b6ad6db96ff34fc2a430cbeef56ed14e5" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 16 11:45:34 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "feat(gicv5): add a GICv5 driver\n\nChange-Id: I10e125c3866e50ed5adde2e4944245f47e50f2e6\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "b731b11b6ad6db96ff34fc2a430cbeef56ed14e5", "tree": "7d4c7a173bb10d0338ad1a38f38592c8db8ca9e5", "parents": [ "355710eb888e89fb739c5492639ddbdc7c0e9897" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jun 26 12:25:35 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "feat(gicv5): add GICv5 instructions and register accessors\n\nChange-Id: I1960b6f0a3bf00ae31c0baadd6202e5d3c894600\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "355710eb888e89fb739c5492639ddbdc7c0e9897", "tree": "1e3ffddb7a8bc8e05494121fcba4ad4435255db1", "parents": [ "49e1706dd57ffc22494a3a47e05e5a28e984675d", "fe1c9b82b5ecc91778eada953135051a180b5237" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Nov 03 11:45:37 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 03 11:45:37 2025 +0000" }, "message": "Merge \"feat(planes): test SIMD access from plane N\"" }, { "commit": "49e1706dd57ffc22494a3a47e05e5a28e984675d", "tree": "12edd4aed8d7989463e1c0226f1aaa91dd195504", "parents": [ "bedd612ed9bc80d60dda50bddeb3823eb62bde21", "6a1ffac35e88673635a124c2a100696d51b8bea9" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Oct 31 15:02:53 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 31 15:02:53 2025 +0000" }, "message": "Merge \"fix(debugv8p9): fix access to mdselr_el1\"" }, { "commit": "6a1ffac35e88673635a124c2a100696d51b8bea9", "tree": "12edd4aed8d7989463e1c0226f1aaa91dd195504", "parents": [ "bedd612ed9bc80d60dda50bddeb3823eb62bde21" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Oct 29 15:32:26 2025 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Oct 30 20:14:36 2025 -0500" }, "message": "fix(debugv8p9): fix access to mdselr_el1\n\nWhen 16 or fewer breakpoints are implemented, MDSELR_EL1 is\nimplemented as RAZ/WI, it is IMPLEMENTATION DEFINED whether\nthe trap controls have any effect on accesses to MDSELR_EL1.\n\nRef: https://developer.arm.com/documentation/111107/2025-09/AArch64-Registers/MDSELR-EL1--Breakpoint-and-Watchpoint-Selection-Register?lang\u003den\n\nChange-Id: I40215ca074e01d5e5dfb184c6aba656fc9077018\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "fe1c9b82b5ecc91778eada953135051a180b5237", "tree": "5c9df9ece7049e83dd728aa62d96de6c7a2122b2", "parents": [ "bedd612ed9bc80d60dda50bddeb3823eb62bde21" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Oct 02 18:07:49 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Oct 30 13:02:11 2025 +0000" }, "message": "feat(planes): test SIMD access from plane N\n\nAdd tests to exercise access to SIMD functinality from Plane N.\nThe tests alternate execution of \u0027rdvl\u0027 instruction from Plane 0 and\nPlane N in different sequences and combinations of TRAP_SIMD values.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I55b9bf55b43b72419e8244f228c505a58c2a819c\n" }, { "commit": "bedd612ed9bc80d60dda50bddeb3823eb62bde21", "tree": "0279fe90658bd378acdfaa5f34d67ce9ce1e7c2b", "parents": [ "bf96263e9162322d57a512fc0e744f08ec86da1e", "5955a6208de318a67dc41a3900e868c7d0378c4d" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Wed Oct 29 16:21:42 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 29 16:21:42 2025 +0000" }, "message": "Merge \"docs: fix Sphinx build errors in maintainers and platform docs\"" }, { "commit": "bf96263e9162322d57a512fc0e744f08ec86da1e", "tree": "4b27b1a61763ef28567a156fd2f551ef73aee0c0", "parents": [ "8530c4e871eb6544c78d1871b843715ff518e7ea", "7919d6dee09f135ed7178cab22df405d7aa530ad" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Oct 28 11:15:17 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 28 11:15:17 2025 +0000" }, "message": "Merge \"docs: update toolchain requirements to 14.3.Rel1\"" }, { "commit": "8530c4e871eb6544c78d1871b843715ff518e7ea", "tree": "93314ef0e22cfa4bcff22c07b59918eca21c487e", "parents": [ "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e", "b32ccfe7950e0dfd33aa89b465274a2b38a0950f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Oct 27 11:06:13 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 27 11:06:13 2025 +0000" }, "message": "Merge \"test(sdei): SDEI event signaling state (registered, enabled, unmasked)\"" }, { "commit": "5955a6208de318a67dc41a3900e868c7d0378c4d", "tree": "c7e948e75b457aa2497b0f045bebde921653b79e", "parents": [ "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Oct 24 13:44:27 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Oct 24 14:27:46 2025 -0500" }, "message": "docs: fix Sphinx build errors in maintainers and platform docs\n\nDefine substitutions for |M|, |G| and |F| in maintainers.rst\nand add missing GitHub link targets to resolve Sphinx “undefined\nsubstitution” and “unknown target name” errors.\n\nAlso fixed indentation , code-block directive and\nthe underline length errors.\n\nChange-Id: I8a25a2c9a063ce04ef8e538e82d96c26ae82361c\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "b32ccfe7950e0dfd33aa89b465274a2b38a0950f", "tree": "93314ef0e22cfa4bcff22c07b59918eca21c487e", "parents": [ "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Thu Feb 27 23:48:45 2025 +0100" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Oct 24 14:26:27 2025 -0500" }, "message": "test(sdei): SDEI event signaling state (registered, enabled, unmasked)\n\nThis patch adds a test to check whether only a registered, enabled\nand unmasked SDEI event can be signaled successfully.\n\nIn other conditions the event signaling process should fail early.\n\nChange-Id: I3ce76ed060bc32648cea43dcce65b707d97c3a78\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "7919d6dee09f135ed7178cab22df405d7aa530ad", "tree": "f2098de161848b1ee8951448fd86aa7c2c008cbd", "parents": [ "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Oct 02 15:06:51 2025 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Oct 24 09:26:13 2025 +0100" }, "message": "docs: update toolchain requirements to 14.3.Rel1\n\nTF-A tests have been validated with toolchain version 14.3.Rel1.\nUpdate documentation to reflect this as the current supported version.\n\nChange-Id: I3d88f2eec209c60e16b133392c2ed72b4b4acc4a\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e", "tree": "b5f90cc65be3aa63bebaaeda7bb4c5919dc55e48", "parents": [ "f543e954e2887cf5927b05ae19759c35710c4e4d", "fa0259bf3db29c31d853ea1c0b1824e28719162f" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Oct 23 09:58:33 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 23 09:58:33 2025 +0000" }, "message": "Merge \"feat(mbedtls): update mbedtls 3.6.5\"" }, { "commit": "fa0259bf3db29c31d853ea1c0b1824e28719162f", "tree": "b5f90cc65be3aa63bebaaeda7bb4c5919dc55e48", "parents": [ "f543e954e2887cf5927b05ae19759c35710c4e4d" ], "author": { "name": "Slava Andrianov", "email": "slava.andrianov@arm.com", "time": "Thu Oct 16 14:32:48 2025 -0500" }, "committer": { "name": "Slava Andrianov", "email": "slava.andrianov@arm.com", "time": "Tue Oct 21 16:32:48 2025 -0500" }, "message": "feat(mbedtls): update mbedtls 3.6.5\n\nChange-Id: Iad177d211b86b3b92f7f3c8c3738f63132895441\nSigned-off-by: Slava Andrianov \u003cslava.andrianov@arm.com\u003e\n" }, { "commit": "f543e954e2887cf5927b05ae19759c35710c4e4d", "tree": "d002b09e7453e10e2ea444ce942c5b98d44f10a7", "parents": [ "4c04f4a824aa3fa2b58b399ebdfc7a5d4248b17b", "466f182aefcd2523f7a12b6315e23507b13c97a6" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Oct 16 15:30:18 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 16 15:30:18 2025 +0000" }, "message": "Merge changes from topic \"amd_pm_tests\"\n\n* changes:\n feat(amd): add test for get reset status EEMI API\n feat(amd): add test for force powerdown EEMI API\n feat(amd): add test for query data EEMI API\n feat(amd): add test for self suspend EEMI API\n feat(amd): add test for pll EEMI APIs\n feat(amd): add test for system shutdown EEMI API\n feat(amd): add test for operating characteristics EEMI API\n feat(amd): add test for TF-A register sgi API\n feat(amd): add test for TF-A feature check API\n feat(amd): add test for trustzone version API\n feat(amd): add test for init finalize EEMI API\n feat(amd): add test for pin EEMI APIs\n feat(amd): add test for clock EEMI APIs\n feat(amd): add test for node EEMI APIs\n feat(amd): add test for IOCTL EEMI API\n feat(amd): add test for register notifier EEMI API\n feat(amd): add platform specific test cases\n" }, { "commit": "4c04f4a824aa3fa2b58b399ebdfc7a5d4248b17b", "tree": "a14e26c5df9b2f417ce758ce619602896747fabd", "parents": [ "a75b61043527655ffdca008a8d47fbb4cc17431b", "f02375764dad0e5f1531fbdb2a17370497b27858" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Tue Oct 14 16:29:22 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 14 16:29:22 2025 +0000" }, "message": "Merge changes I5a64f51b,I89a45bec\n\n* changes:\n feat(smccc): availability test: add FEAT_AIE and FEAT_PFAR checks\n fix(spe): turn assert into warning for newer SPE versions\n" }, { "commit": "a75b61043527655ffdca008a8d47fbb4cc17431b", "tree": "32db39cc1beed611b52f1c7aa44b3ca0a9e993ea", "parents": [ "ed52bf5682c652e9d82a5a2e6869774bb300ed08", "adc86ecbe0aff82859a5f2f215d8199b77409413" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Oct 14 12:11:52 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 14 12:11:52 2025 +0000" }, "message": "Merge \"fix(versal2): correct SLCR base for timer interrupt\"" }, { "commit": "f02375764dad0e5f1531fbdb2a17370497b27858", "tree": "48babcccbde99dc320ebe8d051ea344cc6af9723", "parents": [ "0fe74ee1f2b40f416d5e5945441f1dada67c6ec0" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Oct 07 15:08:17 2025 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Oct 13 15:18:59 2025 +0100" }, "message": "feat(smccc): availability test: add FEAT_AIE and FEAT_PFAR checks\n\nARMv8.8 introduced FEAT_PFAR and FEAT_AIE, which each have a trap bit\nin SCR_EL3.\n\nAdd the respective ID register fields and check for those two features\nin the SMCCC feature availability test, to verify that EL3 has enabled\nthe right bits in the SCR_EL3 availability value.\n\nFix some whitespace damage in the MEC field definitions on the way.\n\nChange-Id: I5a64f51ba6bcc04c271ddf1e7456ed584da6a1af\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "0fe74ee1f2b40f416d5e5945441f1dada67c6ec0", "tree": "a5b9d53613499f7160058eee0a911cf599a3f6d5", "parents": [ "ed52bf5682c652e9d82a5a2e6869774bb300ed08" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Oct 09 18:15:35 2025 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Oct 13 15:18:43 2025 +0100" }, "message": "fix(spe): turn assert into warning for newer SPE versions\n\nFEAT_SPE gets some updates in the architecture from time to time,\nincreasing the value in the ID_AA64DFR0_EL1.PMSVer field. The Arm ARM\npromises that higher numbers only add features, so any tests for a lower\nversion should always be valid, even if the hardware supports more\nfeatures.\n\nTurn the assert into a warning, so we still log that the test might need\nto be upgraded, but don\u0027t fail the test anymore.\n\nChange-Id: I89a45bec9b22dae15f754a22f310fc6ea8def714\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "ed52bf5682c652e9d82a5a2e6869774bb300ed08", "tree": "4a4cb1c859ce181d3a0dbb9ca6975d042d851a68", "parents": [ "a297106fffd8ceea66065ca17a25bb641ce2028b", "6db21fa1e8ef4df32d743b178d86489c8da3db4a" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Oct 09 17:14:48 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 09 17:14:48 2025 +0000" }, "message": "Merge \"fix(smccc): make feat discovery testcase to use SMC64\"" }, { "commit": "a297106fffd8ceea66065ca17a25bb641ce2028b", "tree": "39a89d1b3ea5b81eefe52296188d8fff72e348aa", "parents": [ "c72fd11ff7cd96fbce3f1052b72ccda02134eca4", "b2ca2dc3806ef8cebd55c568c8873d300763d641" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Oct 09 10:07:37 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 09 10:07:37 2025 +0000" }, "message": "Merge \"fix(ff-a): no NS attribute in hypervisor retrieve request\"" }, { "commit": "c72fd11ff7cd96fbce3f1052b72ccda02134eca4", "tree": "f94be6511eceb4eb72c82769ce47ddaaa4027ef6", "parents": [ "595833773c4de78f4e2d53217f704b453625ab5a", "3bb031c9f8ed31fbdbfe6241f7f46e29f2a1c2a3" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Oct 08 21:51:29 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 08 21:51:29 2025 +0000" }, "message": "Merge \"fix(fuzzing): resolve script issue\"" }, { "commit": "6db21fa1e8ef4df32d743b178d86489c8da3db4a", "tree": "5c60256ba83d3f812e34fdee37a61357e8fdef69", "parents": [ "595833773c4de78f4e2d53217f704b453625ab5a" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Sep 19 10:17:06 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Oct 08 14:38:54 2025 -0500" }, "message": "fix(smccc): make feat discovery testcase to use SMC64\n\nCommit a0fa44b48 fixed SMCCC_ARCH_FEAT_AVAILABILITY to use aarch64\nvalue, this patch updates tftf to reflect the change.\n\nChange-Id: I29fa8c5dca21a350dad4895822c87357c1e71a88\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "b2ca2dc3806ef8cebd55c568c8873d300763d641", "tree": "192aac3add05bf9e116b48761d72d335a750e9f4", "parents": [ "595833773c4de78f4e2d53217f704b453625ab5a" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 08 12:26:06 2025 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 08 15:57:23 2025 +0100" }, "message": "fix(ff-a): no NS attribute in hypervisor retrieve request\n\nWhen validating the return of the hypervisor retrieve request, tftf\nwas expecting the NS attribute. Which is not meaningful in the context\nof the NWd.\n\nChange-Id: Icee86f458b14b67716ceea208f56e68dd85fc047\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "adc86ecbe0aff82859a5f2f215d8199b77409413", "tree": "aa900b3570f13f346bb6117335a882d79e98f666", "parents": [ "595833773c4de78f4e2d53217f704b453625ab5a" ], "author": { "name": "Saivardhan Thatikonda", "email": "saivardhan.thatikonda@amd.com", "time": "Wed Sep 24 09:09:42 2025 +0000" }, "committer": { "name": "Saivardhan Thatikonda", "email": "saivardhan.thatikonda@amd.com", "time": "Mon Oct 06 06:28:45 2025 +0000" }, "message": "fix(versal2): correct SLCR base for timer interrupt\n\nTSP suspend/resume tests were failing because the timer interrupt did\nnot occur after registration, due to an incorrect SLCR (System Level\nControl Registers) base address mapping.\nUpdated the SLCR base address to align with the AMD Versal Gen 2\nregister mapping and configured the TTC (Triple Timer Counter) base\nto TTC0.\n\nChange-Id: I64e3bbed20e440a8fd6f26295ee72ef421392360\nSigned-off-by: Saivardhan Thatikonda \u003csaivardhan.thatikonda@amd.com\u003e\n" }, { "commit": "595833773c4de78f4e2d53217f704b453625ab5a", "tree": "b1046eeb5ecebb324455284ad9466f2a18c712df", "parents": [ "a26539f5a882d35ece2a238c28e02f6e29a7fe1e", "24b2cf7d07ba4cb55ac8a3d66eac6c42ffe3087d" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Oct 02 15:07:42 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 02 15:07:42 2025 +0000" }, "message": "Merge \"refactor(ffa-notification): deprecate per-vCPU notification test coverage\"" }, { "commit": "a26539f5a882d35ece2a238c28e02f6e29a7fe1e", "tree": "f630867caf5b73c8693ca9503b4c4549bc77f796", "parents": [ "84529f26a1c5b6729856a9f27ddba1ebdea1cd80", "cce10bd1c0ec3ac1573da7715da8abe94808fc54" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Sep 29 09:05:12 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 29 09:05:12 2025 +0000" }, "message": "Merge \"fix: incorrect expectation for FFA_ABORT interface in ffa_features\"" }, { "commit": "84529f26a1c5b6729856a9f27ddba1ebdea1cd80", "tree": "7e9b0f4b3da745f79e108e0c947de96ce504ad9f", "parents": [ "dcf9d6f994ef8b803fe6ea270a8c06634c97f8fc", "caca5cc7406eea453bcd93df1639ba2407ae80ef" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Sep 26 15:05:58 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 26 15:05:58 2025 +0000" }, "message": "Merge \"feat(mbedtls): update mbedtls to version 3.6.4\"" }, { "commit": "caca5cc7406eea453bcd93df1639ba2407ae80ef", "tree": "7e9b0f4b3da745f79e108e0c947de96ce504ad9f", "parents": [ "dcf9d6f994ef8b803fe6ea270a8c06634c97f8fc" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Jul 10 14:28:24 2025 -0500" }, "committer": { "name": "Slava Andrianov", "email": "slava.andrianov@arm.com", "time": "Fri Sep 26 09:27:48 2025 -0500" }, "message": "feat(mbedtls): update mbedtls to version 3.6.4\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I3ed56c27d7c67f5386d9c9a69b45b90a4a5f4b60\n" }, { "commit": "466f182aefcd2523f7a12b6315e23507b13c97a6", "tree": "8f43c4f3a54acad84b94c3b63ae4970b11f22cda", "parents": [ "ceec9a5f8ea70599d0190b2519764067708b7b9a" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Aug 29 01:14:01 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for get reset status EEMI API\n\nAdd a test for the get reset status EEMI API within the TF-A test\nframework. The test validates the functionality of the API to read the\ndevice reset state.\n\nChange-Id: I3f35e27eb25fc7d6bbb2b71b7c3e46db775420c8\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "ceec9a5f8ea70599d0190b2519764067708b7b9a", "tree": "cb4725f55c2623f6e6b52fc7f470c7d4336122c7", "parents": [ "0a30387ca351f1603f3be15fa134ba60cda5ec84" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Thu Aug 28 22:08:46 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for force powerdown EEMI API\n\nAdd tests for the EEMI APIs that handle force power down and request\nwakeup within the TF-A test framework. The force power down API is\nused to terminate an unresponsive subsystem and automatically release\nits resources. The request wakeup API is used to power up a CPU node\nwithin the same PU or to power up another PU.\n\nChange-Id: I4fa6da87a3044c52834ab34621141cce5e136948\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "0a30387ca351f1603f3be15fa134ba60cda5ec84", "tree": "c4ffb9c066f389ebe5a589ad1168fc4a0c3ae89c", "parents": [ "2623513dbbbaee21ac309fb9f14eba748806fd47" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Wed Aug 27 04:15:25 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for query data EEMI API\n\nAdd a test for the query_data EEMI API within the TF-A test framework.\nThe test validates the functionality of the API for querying platform\nresource information.\n\nNote: This initial test focuses on validating the API interface and\ndoes not cover all query IDs\n\nChange-Id: I8488d08c3682613fcfc796acee6e76e384bbc39e\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "2623513dbbbaee21ac309fb9f14eba748806fd47", "tree": "ea9ae57b314a55cbf31e4cc68bbfea6b72168d47", "parents": [ "7fad289c38edda310b73a1072b4ffab2460385de" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Tue Aug 26 00:23:47 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for self suspend EEMI API\n\nAdd tests for setting wakeup source and self-suspend EEMI APIs.\nThe purpose of these tests is to validate the setting up of wake up\nsource and for a cpu to declare that it is about to suspend itself.\n\nChange-Id: I93374924703e03663b0d038a2aa79298e1cdb6f6\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "7fad289c38edda310b73a1072b4ffab2460385de", "tree": "57fd7d079cd6684679cf6ddc3663dbaee3760025", "parents": [ "952291944c14a2837610a3f2ba4b167bbdf64b90" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 23:51:41 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for pll EEMI APIs\n\nAdd test for pll EEMI APIs within the TF-A test\nframework. The purpose of this test is to validate\nfunctionality and reliability of various pll operations\n\nTest cover the following EEMI APIs:\n- xpm_pll_set_parameter\n- xpm_pll_get_parameter\n- xpm_pll_get_mode\n- xpm_pll_set_mode\n\nChange-Id: I1a2c88edc247dd4783ed52bc7e731b1d18b139e9\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "952291944c14a2837610a3f2ba4b167bbdf64b90", "tree": "1a17c36d70a12d92b64ff01e7b9ac4c4d58558b5", "parents": [ "0559174098d9d200f7aeafab5ada401a71b9d292" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 23:29:29 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:41 2025 -0700" }, "message": "feat(amd): add test for system shutdown EEMI API\n\nAdd test for xpm_system_shutdown EEMI API within the TF-A test\nframework. The purpose of this test is for a subsystem to\nshutdown self or restart self, Ps or system.\n\nNote: Only the subsystem restart scenario is executed in this test.\nPerforming a system shutdown would prevent the execution of\nany subsequent tests.\n\nChange-Id: Iaf8a7cad96ad6b6137187214c902434f90a78802\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "0559174098d9d200f7aeafab5ada401a71b9d292", "tree": "ddd8987d30526a2c8801f1f253930d5a575ddc5c", "parents": [ "db5542aaeb6c7c4f04346a4f51aec205a3595261" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 22:56:05 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:41 2025 -0700" }, "message": "feat(amd): add test for operating characteristics EEMI API\n\nAdd test for the get_op_characteristics API within the TF-A test\nframework. The purpose of this test is to request the power\nmanagement controller to return information about an operating\ncharacteristic of a component.\n\nChange-Id: I3b8346a82742c1b59dacc724c29235e4dbd6e753\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "db5542aaeb6c7c4f04346a4f51aec205a3595261", "tree": "3d0330d61d98ec5748703cd68338676b05260792", "parents": [ "6b1f473108203a65977d503c5a743e3bb1ebc988" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 22:24:47 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:41 2025 -0700" }, "message": "feat(amd): add test for TF-A register sgi API\n\nAdds a test to verify the tf_a_register_sgi() API, which registers\nthe IPI interrupt with the system.\n\nChange-Id: I3be28dc6c4ddec274cb64c8148fe0b61a1ab7b34\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "6b1f473108203a65977d503c5a743e3bb1ebc988", "tree": "7387741b6c9d23c4843450f5b05c23174936d820", "parents": [ "4cb875e37ac1a0423d3e772dbe266f9415e249bf" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 22:12:44 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:41 2025 -0700" }, "message": "feat(amd): add test for TF-A feature check API\n\nAdd test for the tf_a_feature_check API within the TF-A test\nframework. The purpose of this test is retrieve the supported\nAPI Version.\n\nChange-Id: I3d03661aec29814132d2635e7187442fb52af067\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "4cb875e37ac1a0423d3e772dbe266f9415e249bf", "tree": "c934b5b295eec8d21ab33b46591e76584ba949b4", "parents": [ "5c80b54add25bfa575c64b20f63a225c65dc90cd" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 21:51:55 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for trustzone version API\n\nAdds a test to verify the get_trustzone_version() API, which retrieves\nthe current TrustZone version from the firmware.\n\nChange-Id: I92876df6ccf970b5474eb86f48f97af9168704bb\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "5c80b54add25bfa575c64b20f63a225c65dc90cd", "tree": "7356fae8000f1953f504377e4d6606cc5b35ee6f", "parents": [ "453f76f08a6ed1a176d669ef5805531e1318c51e" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 21:31:17 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for init finalize EEMI API\n\nAdds a test to verify the init_finalize EEMI API, which notifies the\npower management controller that power management initialization is\ncomplete.\n\nChange-Id: I84a36b3cd0cadb0c462fdad2d1fd18b1821dedbd\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "453f76f08a6ed1a176d669ef5805531e1318c51e", "tree": "a3ac828b95b98efd1420ad2e8abea01dc2c2b32c", "parents": [ "d514d2bbc464cf128cb7487f6a4df0c8d341db55" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 06:50:50 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for pin EEMI APIs\n\nAdd test for the pin-related EEMI APIs within the TF-A test\nframework. The purpose of these tests is to validate the\nfunctionality and reliability of various pin operations.\n\nTest cover the following EEMI APIs:\n- xpm_pinctrl_request\n- xpm_pinctrl_release\n- xpm_pinctrl_set_function\n- xpm_pinctrl_get_function\n- xpm_pinctrl_set_parameter\n- xpm_pinctrl_get_parameter\n\nNote: This initial test does not cover all the pin ids, as the\npurpose of the test is to validate the pin EEMI APIs interface.\n\nChange-Id: I50142ee110e5cb7427ffaeae7f413aa0e6662006\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "d514d2bbc464cf128cb7487f6a4df0c8d341db55", "tree": "da6b66fc10f0505c0acf4f127f3d6dff9237e6ba", "parents": [ "9743f7d31c0d86290c711f0d439e5b333881cad3" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 06:25:32 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for clock EEMI APIs\n\nAdd test for the clock-related EEMI APIs within the TF-A test\nframework. The purpose of these tests is to validate the\nfunctionality and reliability of various clock operations.\n\nTest cover the following EEMI APIs:\n- xpm_clock_get_status\n- xpm_clock_enable\n- xpm_clock_disable\n- xpm_clock_set_parent\n- xpm_clock_get_parent\n- xpm_clock_set_divider\n- xpm_clock_get_divider\n\nNote: This initial test does not cover all the clock ids, as the\npurpose of the test is to validate the clock EEMI APIs interface.\nThe HW design must have QSPI nad GEM clocks enabled to pass this\ntest, otherwise the test will fail.\n\nChange-Id: Ie0d7dc844d4e58d1000a9fd6d669528103b097c7\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "9743f7d31c0d86290c711f0d439e5b333881cad3", "tree": "50c4bf05d441e646cdc351bb8f9696c1d732394f", "parents": [ "7faf8caa04992a21ce0691c1fb41f4586462aa93" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 05:39:36 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for node EEMI APIs\n\nAdd test for the node-related EEMI APIs within the TF-A test\nframework. The purpose of these tests is to validate the\nfunctionality and reliability of various node operations.\n\nTest cover the following EEMI API functionalities:\n- Retrieving node status\n- Setting node requirements\n- Setting maximum latency\n- Releasing an already released node\n- Requesting an already requested node\n\nNote: This initial test does not cover all the node ids, as the\npurpose of the test is to validate the node EEMI APIs interface.\nThe HW design must include USB and RTC device nodes in order to pass\nthis test, otherwise the test will fail.\n\nChange-Id: I1883abb20ae7e602530e504f3c39b20d02f57004\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "7faf8caa04992a21ce0691c1fb41f4586462aa93", "tree": "110bc5550359aaccbf30a5d8fdbc14c8a2c2665b", "parents": [ "ed5bda84f7ca1098bde39cd0348fb8e86bffbff9" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 04:59:09 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for IOCTL EEMI API\n\nAdd a new test case for the IOCTL EEMI API within the TF-A test\nframework. The objective of this test is to verify the functionality\nand behavior of the IOCTL commands.\n\nTest cover following IOCTL IDs:\n- IOCTL_GET_RPU_OPER_MODE\n - To get the RPU operating mode like split or lockstep\n- IOCTL_SET_RPU_OPER_MODE\n - To set the RPU operating mode like split or lockstep\n\nThese IOCTL Ids require RPU to be enabled either as the default\nsubsystem or as a RPU subsytem.\n\nNote: This initial test does not cover all IOCTL IDs, as the purpose\nof the test is to validate the IOCTL EEMI API interface.\n\nChange-Id: I9c95facaab171af862ad633f7fdcab0b18b7f9e4\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "ed5bda84f7ca1098bde39cd0348fb8e86bffbff9", "tree": "91ada1008018df3933281377a8697f4be3d03d2a", "parents": [ "00d869a0ada0724771e2056606db28a6c2885ea9" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 04:01:16 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for register notifier EEMI API\n\nAdd a test case to validate the register notification handling\nfunctionality of the EEMI API in the TF-A test framework. The test:\n\n- Registers a notifier using `test_register_notifier()`.\n- Waits for a notification within a predefined timeout.\n- If received, unregisters the notifier using\n `test_unregister_notifier()`.\n\nChange-Id: I4454ef8644851a2dedc0a224fa220062fed1d635\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "00d869a0ada0724771e2056606db28a6c2885ea9", "tree": "1e886618edc7081dd3b1c2476e86e742ec633c02", "parents": [ "1dfffbafd2f71cda49f298c08fe8901c9af566f9" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 06:17:34 2025 +0000" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:54:20 2025 -0700" }, "message": "feat(amd): add platform specific test cases\n\nAdd test cases in the TF-A test framework to validate the\nfunctionality of the EEMI APIs.\nAlso add client infrastructure to call PM APIs.\n\n-get_api_version\n-get_chipid\n-feature_check\n\nNote: As of now these changes are just for versal platform. We\u0027ll\nrefactor some of files in future to make it generic for all the\nplatforms.\n\nChange-Id: Id55de9eadaeaf96ccab4aaa1a494620108c25a19\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "dcf9d6f994ef8b803fe6ea270a8c06634c97f8fc", "tree": "cc760f3bae7d7fec7fc8c1c1faee06af4ee53a65", "parents": [ "6cc4372c4036066a940a2bb82debf2ce311070e7", "595bd11a476e81d2bdc22095cac74db51c717a6b" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Sep 25 14:28:37 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 25 14:28:37 2025 +0000" }, "message": "Merge changes from topic \"rfa-related-fixes\"\n\n* changes:\n fix: remove dependency on fixed PSCI version in smc32_fast\n fix: ignore errors on optional General service queries\n fix(psci): mask MBZ bits in PSCI target_cpu arguments\n" }, { "commit": "6cc4372c4036066a940a2bb82debf2ce311070e7", "tree": "8c8a7a8d3e248341b5761af58641563570e4afeb", "parents": [ "93904af65895bb46263ea7b7817acc102c4e37cc", "0f04afb8feca0e823abfe7f60dfba52f6e9925f6" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Sep 25 09:17:59 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 25 09:17:59 2025 +0000" }, "message": "Merge \"feat(debugfs): add oob debugfs test case\"" }, { "commit": "595bd11a476e81d2bdc22095cac74db51c717a6b", "tree": "3dc9314f2b9a52bbb80d9d0fac596b0cd2ddd211", "parents": [ "76369fa34d075217ab4c25a22be7dc8d77041ca9" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Mon Sep 08 17:34:54 2025 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Wed Sep 24 18:51:56 2025 +0200" }, "message": "fix: remove dependency on fixed PSCI version in smc32_fast\n\nEliminate the dependency on a fixed PSCI version when testing single\nreturn register SMC calls.\n\nChange-Id: Iea8fd1bd450615cf2b7409cb5e0dd09e5b804534\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "76369fa34d075217ab4c25a22be7dc8d77041ca9", "tree": "c61594e7ed37f889dabb9df46ad58285a2abb953", "parents": [ "b1467682a26053428c34eb363ba06391dcbf77eb" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Fri Sep 05 16:37:17 2025 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Wed Sep 24 18:51:27 2025 +0200" }, "message": "fix: ignore errors on optional General service queries\n\nIgnore SMC_UNKNOWN errors on optional \u0027General service queries\u0027 defined\nin SMCCC Section 6.2.\n\nChange-Id: Iaf3d0b2f1750c83b104e2fd3e8640318493da062\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "24b2cf7d07ba4cb55ac8a3d66eac6c42ffe3087d", "tree": "22d7ac655c3d2237669b36f57fa3a8a84415c4c4", "parents": [ "93904af65895bb46263ea7b7817acc102c4e37cc" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jul 29 12:22:17 2025 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Sep 23 14:05:06 2025 +0100" }, "message": "refactor(ffa-notification): deprecate per-vCPU notification test coverage\n\n* Per-vCPU notification support is now optional as per FF-A v1.3\n specification.\n\n* Hafnium does not maintain global state for per-vCPU notification\n bindings, and does not support dual-mode reuse of a notification ID\n as both global and per-vCPU.\n\n* This patch deprecates all TF-A test cases that validate per-vCPU\n notification signaling between VMs and SPs.\n\nChange-Id: I33fdf6c71d9476568b925dd7412bdaffc7cafb9f\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "0f04afb8feca0e823abfe7f60dfba52f6e9925f6", "tree": "e0dee4aabc8251d926c6f73226018c13a7a16d23", "parents": [ "1cb7d971ed9c81d00a041bffebe65280b137cfa0" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 18 11:07:12 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Sep 23 08:01:59 2025 +0000" }, "message": "feat(debugfs): add oob debugfs test case\n\nChange-Id: I8f00f74e9584c211cf13576d27db7ee385f8ab98\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "cce10bd1c0ec3ac1573da7715da8abe94808fc54", "tree": "52094b61862fe7ac01d2ea6c146802382e7a28f0", "parents": [ "93904af65895bb46263ea7b7817acc102c4e37cc" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Sep 22 15:31:32 2025 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Sep 22 15:41:32 2025 -0500" }, "message": "fix: incorrect expectation for FFA_ABORT interface in ffa_features\n\nFFA_ABORT_32/64 ABIs are prohibited at NWd FF-A instance but are\nsupported at SWd FF-A instances.\n\nThis patch fixes the tests to remove the checks for these ABIs from\ncommon pool of FFA_FEATURES validation and puts in private pool\ntargeting tftf and SPs separately.\n\nChange-Id: I14f765c78ba1d18cb34e59e96dec7452345d7ce7\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "93904af65895bb46263ea7b7817acc102c4e37cc", "tree": "c70a2e4a97ba0c630724a3846f64d4b71c26d530", "parents": [ "1cb7d971ed9c81d00a041bffebe65280b137cfa0", "799225ffb1e2f3ea86d7a026b8fe3e2193d2000c" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Mon Sep 22 15:59:59 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 22 15:59:59 2025 +0000" }, "message": "Merge \"feat(neg-boot): tftf invalid rotpk test\"" }, { "commit": "3bb031c9f8ed31fbdbfe6241f7f46e29f2a1c2a3", "tree": "b983cf2210a317901209895daf79c483074c1723", "parents": [ "1cb7d971ed9c81d00a041bffebe65280b137cfa0" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Mon Aug 25 10:28:38 2025 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Mon Sep 22 15:53:07 2025 +0000" }, "message": "fix(fuzzing): resolve script issue\n\nFix scripting error to resolve CI failures.\n\nChange-Id: If5b77a6471227ea9a2c357190bbb60f14a0bc193\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "1cb7d971ed9c81d00a041bffebe65280b137cfa0", "tree": "3cf614b280f33173a2c4edeef9edd6919b83bd46", "parents": [ "e32ac3b57ce89c30d0ff77fffeee4e8e85d4a45c", "3225df9d6bdf3f70ca4b45206a79b45e9f1b3cdb" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Sep 22 12:37:30 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 22 12:37:30 2025 +0000" }, "message": "Merge changes from topic \"ja/ffa_v1_3\"\n\n* changes:\n test(spm): bump partitions to FF-A v1.3\n fix: the FF-A version compatibility check\n chore: drop unused FF-A version macros\n test(ff-a): bump FF-A version to v1.3\n" }, { "commit": "799225ffb1e2f3ea86d7a026b8fe3e2193d2000c", "tree": "7b8ffe88db797e7bb5a6d763c4e3186e4935122f", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Thaddeus Gonzalez-Serna", "email": "Thaddeus.Gonzalez-Serna@arm.com", "time": "Mon Jun 02 09:42:49 2025 -0500" }, "committer": { "name": "Thaddeus Gonzalez-Serna", "email": "Thaddeus.Gonzalez-Serna@arm.com", "time": "Fri Sep 19 11:23:02 2025 -0500" }, "message": "feat(neg-boot): tftf invalid rotpk test\n\nTest to improve code coverage in scenario with corrupt rotpk in fip certificate\n\nChange-Id: I995ab6d9f1488fda44e10ae9ef70c9056d780a89\nSigned-off-by: Thaddeus Gonzalez-Serna \u003cThaddeus.Gonzalez-Serna@arm.com\u003e\n" }, { "commit": "e32ac3b57ce89c30d0ff77fffeee4e8e85d4a45c", "tree": "50d23ce1ee22bd8b1613789ff9f413e87a2fc2c5", "parents": [ "1dfffbafd2f71cda49f298c08fe8901c9af566f9", "fe0c1e428ff3891c1506debf0b41ce7d9b4da87e" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Sep 19 08:28:09 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 19 08:28:09 2025 +0000" }, "message": "Merge \"fix(versal-net): update test skip list\"" }, { "commit": "1dfffbafd2f71cda49f298c08fe8901c9af566f9", "tree": "f33516764de57dd4acc8d31c1516e3ef964ee70e", "parents": [ "d84996abcc2ba42292f223fe880d572b8cea58ef", "04315990a63abb68da3ea135c96b5b1390bf063f" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Sep 17 11:23:15 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 17 11:23:15 2025 +0000" }, "message": "Merge changes from topic \"hm/evlog\"\n\n* changes:\n build(measured-boot)!: move to ext event log lib\n feat(libtl): bump version to get event log funcs\n" }, { "commit": "d84996abcc2ba42292f223fe880d572b8cea58ef", "tree": "14c5d8d93a0a8fc2f5c169f83f8951f0e7b314d6", "parents": [ "c5eae3cf22ef0859ad81e56c9ce5314fa61f4752", "6e191237b069712f613e42592fd08fe326da1ffc" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Tue Sep 16 21:14:24 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 16 21:14:24 2025 +0000" }, "message": "Merge \"fix(psci): skip PSCI OSI mode tests if not supported\"" }, { "commit": "c5eae3cf22ef0859ad81e56c9ce5314fa61f4752", "tree": "b9952ee03fbaaa9465a43f262ba9ddbff17ed5e6", "parents": [ "8bcaf3a5280d074fb53436c13f8ea386f77aae32", "2fb7522d68553139a45c418bbe74b376b10e8d78" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Tue Sep 16 20:58:16 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 16 20:58:16 2025 +0000" }, "message": "Merge changes from topic \"rfa-related-fixes\"\n\n* changes:\n feat(psci): accept v1.2 and v1.3 PSCI versions\n fix: correct cntfrq_check log message\n" }, { "commit": "8bcaf3a5280d074fb53436c13f8ea386f77aae32", "tree": "070e85a6ed0ce94c01dbb34ef5533179663a06d7", "parents": [ "a4afb12510e4467390a5c2556e96ca71d257c421", "5bc1da5c4bd0c7dd6b5daa1764eb271503bd0ad7" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Sep 16 14:23:02 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 16 14:23:02 2025 +0000" }, "message": "Merge \"fix(smmuv3): use an SMMUv3TestEngine that can issue Secure accesses\"" }, { "commit": "5bc1da5c4bd0c7dd6b5daa1764eb271503bd0ad7", "tree": "614a84843c428efd6ac6facca2d6d691889f2aa6", "parents": [ "6a010a32ac092ff392c34b80179b21e8036731f4" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Sep 15 16:05:45 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 16 14:18:48 2025 +0100" }, "message": "fix(smmuv3): use an SMMUv3TestEngine that can issue Secure accesses\n\nPCIe can only relay whether an access is NS or realm. So when Cactus\ninstructs the test engine to go talk to the SMMU pretending to be a\nSecure device we\u0027re relying on behaviour that shouldn\u0027t be possible.\n\nModels up to version 11.28 didn\u0027t check this so it would work despite\nbeing incorrect. At some point after this release, though, a check has\nbeen added making these accesses report failure (CMD reads\nENGINE_MIS_CFG when read back).\n\nThe fix is to not use a PCIe connected test engine. This can be done by\nusing a dma330x4 that can be converted to a test engine with\n`-C pci.dma330x4.use_smmuv3testengine_not_dmacs\u003d1`.\n\nThis now works on older and newer models.\n\nChange-Id: I76a8deef78c640c4958d0a94df19ac29d3759cc0\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "b1467682a26053428c34eb363ba06391dcbf77eb", "tree": "af2c57fb047817f280270ffa4bb4c275064359b3", "parents": [ "6e191237b069712f613e42592fd08fe326da1ffc" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Thu Aug 28 14:38:36 2025 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Tue Sep 16 14:57:48 2025 +0200" }, "message": "fix(psci): mask MBZ bits in PSCI target_cpu arguments\n\nThe PSCI specification defines the target_cpu values almost the same as\nthe MPIDR_EL1 register value, however it only contains the Aff0-3 fields\nand the rest is declared as MBZ. Mask the MBZ bits to follow the PSCI\nspecification.\n\nChange-Id: I4196b5039aa774b357cb6932d3c2c24060f1f228\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "6e191237b069712f613e42592fd08fe326da1ffc", "tree": "09c86ecadefdc71659ffa4ab38ad5c52e9882505", "parents": [ "2fb7522d68553139a45c418bbe74b376b10e8d78" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Wed Aug 06 16:28:57 2025 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Tue Sep 16 14:56:38 2025 +0200" }, "message": "fix(psci): skip PSCI OSI mode tests if not supported\n\nSkip the relevant tests if PSCI_FEATURES(CPU_SUSPEND) does not report\nthe OS initiated mode support.\n\nChange-Id: I28908cafa701f66709991f87f649955151c34568\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "2fb7522d68553139a45c418bbe74b376b10e8d78", "tree": "687c2b7fa3f9148809d14ac2d0bdf9c38238a5fe", "parents": [ "939c19ed3944643e4caf27c843f086aff1f071c6" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Wed Aug 06 16:26:23 2025 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Tue Sep 16 14:56:38 2025 +0200" }, "message": "feat(psci): accept v1.2 and v1.3 PSCI versions\n\nAdd PSCI version 1.2 and 1.3 to the allowed version list.\n\nChange-Id: I84a3e46112397d4b75ff3a8614a0bfc5f2682f31\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "939c19ed3944643e4caf27c843f086aff1f071c6", "tree": "e0c8364021ecec6506d0c12be900c3d909d2e6e9", "parents": [ "a4afb12510e4467390a5c2556e96ca71d257c421" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Wed Aug 06 16:24:24 2025 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Tue Sep 16 14:56:38 2025 +0200" }, "message": "fix: correct cntfrq_check log message\n\nFix new line character at the end of the log message in cntfrq_check.\n\nChange-Id: Id58ad9e18a7825d54797eea01d1ed5cdb68c3fa3\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "04315990a63abb68da3ea135c96b5b1390bf063f", "tree": "48d235d6d7cc4f6af7e5d27894dadccbb94649d8", "parents": [ "95a7af102c04cc9cea69fd7b0e6297b63064853a" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Aug 26 13:55:51 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Sep 16 11:38:33 2025 +0000" }, "message": "build(measured-boot)!: move to ext event log lib\n\nRemoves in-tree Event Log library implementation and updates all\nreferences to use the external submodule. Updates include paths,\nMakefile macros, and platform integration logic to link with lib as a\nstatic library. Some of the event log utilities related to firmware\nhandoff have been moved into that library, accordingly bump the version\nof LibTL.\n\nIf you cloned TFTF without the `--recurse-submodules` flag, you can\nensure that this submodule is present by running:\n\n git submodule update --init --recursive\n\nBREAKING-CHANGE: LibEventLog is now included in TFTF as a submodule.\n Please run `git submodule update --init --recursive` if you encounter\n issues after migrating to the latest version of TFTF.\n\nChange-Id: I5c681ab7621c8bcdfc06793a81781af3439964a6\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "95a7af102c04cc9cea69fd7b0e6297b63064853a", "tree": "28a5c49ae404720de4dca11b7f57be13be375057", "parents": [ "6a010a32ac092ff392c34b80179b21e8036731f4" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Aug 28 13:02:44 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Sep 16 11:37:42 2025 +0000" }, "message": "feat(libtl): bump version to get event log funcs\n\nLibTL now provides APIs for handling event logs from a transfer list.\nBump to that version and get rid of existing functions that duplicate\nthat behaviour.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: I4967144657765741b390cf6cda56e08a2da0eadf\n" }, { "commit": "a4afb12510e4467390a5c2556e96ca71d257c421", "tree": "952fa1238d51e9b91f607ab556d24dfe39742575", "parents": [ "6a010a32ac092ff392c34b80179b21e8036731f4", "9eacfa1b5a4bc77e8752a6d8620ba33df5f796c2" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Sep 15 17:02:16 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 15 17:02:16 2025 +0000" }, "message": "Merge \"refactor: print error codes and func ID\"" }, { "commit": "6a010a32ac092ff392c34b80179b21e8036731f4", "tree": "dd6f31da6a94933db431d633e815002c92bbe08c", "parents": [ "2338ffcc695072c9ba1883b40473b1bb358a967f", "31f6f653bbc0eb6f2df84eb1fdb4574170bfba16" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Sep 15 12:07:44 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 15 12:07:44 2025 +0000" }, "message": "Merge changes from topic \"rmm-planes\"\n\n* changes:\n fix(rme): RMM is not taking PSTATE into account on PN entry/exit\n feat(rme): update tests to alp14\n feat(rme): uplift RSI_SYSREG_READ/WRITE tests to alp13\n" }, { "commit": "2338ffcc695072c9ba1883b40473b1bb358a967f", "tree": "d78c15ef224e15b121a728b672f36cf564f51e1e", "parents": [ "79aff977ca65c6344d1c04ac3391afd001845863", "046835b1fd180406994374ac868423de7f4ff8c0" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Sep 15 08:59:18 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 15 08:59:18 2025 +0000" }, "message": "Merge \"fix(ff-a): ivy shim receives NPI feature\"" }, { "commit": "31f6f653bbc0eb6f2df84eb1fdb4574170bfba16", "tree": "0f58b61fa0d5a182ce062c876d70f8f385051b97", "parents": [ "049b469008f0901d9aa75444f10f1c5bc195cc78" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Aug 05 18:20:55 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Sep 12 17:58:28 2025 +0100" }, "message": "fix(rme): RMM is not taking PSTATE into account on PN entry/exit\n\nPlane 0 is notified, through RsiPlaneExit.pstate field of RMM PSTATE\nupon plane N exit. Also, plane 0 needs to provide RMM PSTATE value upon\ncalling RsiPlaneEnter through RsiPlaneEnter.pstate value.\n\nThis patch implements that behavior on the existing tests for planes\nas it was not implemented before.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I45af6c5863af2d2b7cc92005e16b80b895639f07\n" }, { "commit": "79aff977ca65c6344d1c04ac3391afd001845863", "tree": "5a0615fd0d4c03e2130c41b59cecb37bdba2ae66", "parents": [ "0b9f575377a7bdfdb1319eb2af60cbb668b127aa", "c609e4b7a08c3e32b10e0bac1e14201520ed99dc" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Sep 12 12:35:36 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 12 12:35:36 2025 +0000" }, "message": "Merge \"test: FFA_ABORT ABI not supported at Nwd interface\"" }, { "commit": "9eacfa1b5a4bc77e8752a6d8620ba33df5f796c2", "tree": "01b50fb0fe98fd3a4f57117fcafcc14cf6f39c8e", "parents": [ "0b9f575377a7bdfdb1319eb2af60cbb668b127aa" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Jan 10 11:56:58 2025 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Sep 12 12:31:23 2025 +0100" }, "message": "refactor: print error codes and func ID\n\nFunction helpers from the spm_common.c have been refactored,\nto print the FF-A func and error names.\n\nThis changes adds the respective hex integer return to the\nlogs as well.\n\nUseful when the *_name functions print \"unknown\".\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I375a1e09820e1d4c9fc1a37f8f3626d39a4b62ae\n" }, { "commit": "046835b1fd180406994374ac868423de7f4ff8c0", "tree": "510193ca3b027980ead5f461a0856a5073a66342", "parents": [ "0b9f575377a7bdfdb1319eb2af60cbb668b127aa" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 14:35:56 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Sep 12 12:12:48 2025 +0100" }, "message": "fix(ff-a): ivy shim receives NPI feature\n\nIvy can be deployed with shim and without.\nWith shim the partition is loaded as S-EL1\npartition. Which means the NPI feature via\nFFA_FEATURES ABI should be reported.\n\nThis patch handles the shim being present or\nnot in the respective test.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I1de94c77928e60164949f4801db1e82058eb89ad\n" }, { "commit": "3225df9d6bdf3f70ca4b45206a79b45e9f1b3cdb", "tree": "213fd95e9b007c5445006cf956b481461968a249", "parents": [ "74041faa3dab7c6dcd39471ed1eccf6ad69e4d97" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Sep 02 10:36:47 2025 +0100" }, "committer": { "name": "Joao Alves", "email": "joao.alves@arm.com", "time": "Thu Sep 11 17:08:26 2025 +0000" }, "message": "test(spm): bump partitions to FF-A v1.3\n\nChange the FF-A version of Cactus and Ivy to FF-A v1.3.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Iba069062712e3e88b5ba31ce07da117ca85d143c\n" }, { "commit": "0b9f575377a7bdfdb1319eb2af60cbb668b127aa", "tree": "9d4bda7de5f2c1640670949c0aa8fb382bc31fee", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b", "794b0ac8cdb01aa8c5ad630d4592b3743f6782cd" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Sep 10 13:43:57 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 10 13:43:57 2025 +0000" }, "message": "Merge changes from topic \"bk/gicv5_full\"\n\n* changes:\n refactor(gic): unify SGI exception data\n fix(gic): don\u0027t access a GIC register if it\u0027s not supported\n refactor(gic): add a is_feat_gic_supported() standard helper\n refactor(gic): make the GIC driver generic\n refactor(gic): prepare for a new GIC revision\n" }, { "commit": "049b469008f0901d9aa75444f10f1c5bc195cc78", "tree": "e564191843668b2c2f96f9fb71b31885884af317", "parents": [ "4a9ffd52277103082ea78d7873e5f5732ed6fdcc" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Jun 02 20:01:02 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Wed Sep 10 13:19:20 2025 +0100" }, "message": "feat(rme): update tests to alp14\n\nRMI_RTT_AUX_{MAP, UNMAP}_UNPROTECTED have been modified on alp14.\nThis patch updates the RME tests to align with the new spec.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Icefb26de4fb66b1199a19d99496fa800f6abc2bc\n" }, { "commit": "4a9ffd52277103082ea78d7873e5f5732ed6fdcc", "tree": "7465ab700d8557cd0027ccbfce37a9637ed1bcf8", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu May 22 14:45:48 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Wed Sep 10 13:18:57 2025 +0100" }, "message": "feat(rme): uplift RSI_SYSREG_READ/WRITE tests to alp13\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Ia06872776d06655e0c0ceb6a48fca0e5aefac0b8\n" }, { "commit": "c609e4b7a08c3e32b10e0bac1e14201520ed99dc", "tree": "3c1470e09f20fbbdf3f4df56420d04347f25d315", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Aug 20 22:00:22 2025 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Sep 09 14:03:20 2025 -0500" }, "message": "test: FFA_ABORT ABI not supported at Nwd interface\n\nFFA_ABORT is supported only at secure FF-A interfaces. It is not\nexposed to NWd callers.\n\nThis patch enhances an existing test to ensure FFA_ABORT ABIs are\nnot supported when invoked in normal world.\n\nChange-Id: I2bfd2abd8db182aad4d9491b210b384e79059291\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "74041faa3dab7c6dcd39471ed1eccf6ad69e4d97", "tree": "2e0877611e7d66da32b4011414d4287094b10410", "parents": [ "3751ef338f509672387fcf1022d22836f9365352" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Sep 01 18:09:11 2025 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Sep 09 18:15:44 2025 +0100" }, "message": "fix: the FF-A version compatibility check\n\nDrop the assert to check the version returned by SPM.\nInstead, only expect it is compatible.\nArguments for the function \"ffa_versions_are_compatible\"\nwere mistakenly swapped.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I8b94c52c0d6ca3e88967975a7d394e3e4fe273a3\n" }, { "commit": "3751ef338f509672387fcf1022d22836f9365352", "tree": "b67a241873b24ad0f1e1745ec1eddf35165bb916", "parents": [ "9324a5fce9c601405bccd35dbcc373d4f8887915" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Sep 01 18:08:33 2025 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Sep 09 18:15:30 2025 +0100" }, "message": "chore: drop unused FF-A version macros\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Icf4cd3b7b00cb26b96deb1868c63d800e444b39d\n" }, { "commit": "9324a5fce9c601405bccd35dbcc373d4f8887915", "tree": "fd6bbfdd5ad66d10bbb9ed2b996c557c52610b19", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Aug 28 12:11:45 2025 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Sep 09 18:14:58 2025 +0100" }, "message": "test(ff-a): bump FF-A version to v1.3\n\nFollowing Hafnium FF-A version bump, increase the\nexpected version in the tests to FF-A v1.3.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I82ce437834d3d711059b0a74b15bcf4757c547a5\n" }, { "commit": "794b0ac8cdb01aa8c5ad630d4592b3743f6782cd", "tree": "9d4bda7de5f2c1640670949c0aa8fb382bc31fee", "parents": [ "aa48358ef9270417897780230bdedb635cc4af56" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Jun 20 13:13:29 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:37:05 2025 +0100" }, "message": "refactor(gic): unify SGI exception data\n\nThe information we pass to exception handlers for SGIs, PPIs, and SPIs\ndoes not differer materially. Unify the handling to use the same types.\n\nSince SGIs are normal IRQs, we can put the last remaining function in\nirq.h to simplify a bit.\n\nChange-Id: I1cf6f8a2a832797a9ce54eeb025a94120f115cf6\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "aa48358ef9270417897780230bdedb635cc4af56", "tree": "e5b990082edda1abc4e2f50903865f1c899f6516", "parents": [ "5f2468444daafa55f72a976c856d7f941a83ca51" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Jun 20 09:07:44 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:37:05 2025 +0100" }, "message": "fix(gic): don\u0027t access a GIC register if it\u0027s not supported\n\nOn non-gicv3 systems, this register will not be present. However, the\ncheck for gicv3 wil be after, resulting in an error.\n\nChange-Id: I6077289eb848bd3194660f975baeca5141b14e1f\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "5f2468444daafa55f72a976c856d7f941a83ca51", "tree": "89d59590ff79f1bb8ab1b7924c47611cb1fbd245", "parents": [ "44de1232dca506a997adef7eae08b2570892262b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 16 11:42:30 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:37:04 2025 +0100" }, "message": "refactor(gic): add a is_feat_gic_supported() standard helper\n\nFEAT_GIC is a CPU feature like any other, add an arch_features.h helper\nfor it.\n\nChange-Id: I762b6333907f5f3dd3352544c1f2fb211a794b3e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "44de1232dca506a997adef7eae08b2570892262b", "tree": "b84d79c1da2802ddb131ce33953e36918140e0f2", "parents": [ "a4b3334f21fb994e96549bfc968fa0086c3f9d77" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jul 31 09:43:33 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:36:24 2025 +0100" }, "message": "refactor(gic): make the GIC driver generic\n\nEvery currently supported tftf has some variety of GIC that can work\nwith the main GIC driver. So there\u0027s no need to have each platform\nspecify that as part of their build.\n\nChange-Id: Ic771aad82e8f423042bcf3bf1d3b70cba6236666\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "a4b3334f21fb994e96549bfc968fa0086c3f9d77", "tree": "f4871f7a364074a59e8496102f3f8d56bfd29500", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jun 19 16:24:29 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:36:24 2025 +0100" }, "message": "refactor(gic): prepare for a new GIC revision\n\nThe top level interrupt functions that common code calls are generic\nenough to become tftf\u0027s interrupt API, so rename the file to better\nreflect this. Conversely, gic_common.c is quite specific to GICv2 and\nGICv3 so also rename it to reflect this.\n\nChange-Id: I7becd74fae526a3bc5a9ef9501f0db75b1b086fb\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "fe0c1e428ff3891c1506debf0b41ce7d9b4da87e", "tree": "fe1152797d856e342047d5039dfd43b19efb3e52", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Saivardhan Thatikonda", "email": "saivardhan.thatikonda@amd.com", "time": "Thu Sep 04 10:05:31 2025 +0000" }, "committer": { "name": "Saivardhan Thatikonda", "email": "saivardhan.thatikonda@amd.com", "time": "Sat Sep 06 01:51:42 2025 +0530" }, "message": "fix(versal-net): update test skip list\n\nOn the Versal-Net platform, only a single non-secure private SDEI\nevent is exposed. The test tries to bind every non-secure PPI,\nwhich isn’t supported and could disrupt non-secure drivers that\nalready own those interrupts.\nEnabling SDEI private events for all non-secure PPIs would conflict\nwith existing non-secure components and doesn’t match the platform’s\ndesign or intended usage. Skipping this test is therefore appropriate\nto prevent unintended side effects.\n\nChange-Id: I261b1390aa91e521ac350489fd767a866092bf6c\nSigned-off-by: Saivardhan Thatikonda \u003csaivardhan.thatikonda@amd.com\u003e\n" }, { "commit": "63ea05bd16fceb7048ee625cae12394a3be5f15b", "tree": "7e3d3afdc53a005d65d27093751447c011eb61d3", "parents": [ "0861d8310fe65168754d544a63c3fe2ef2f87211", "9b1afa7fdeaa7a57900c3aa606626a9c9bf9e405" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Sep 02 18:27:21 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 02 18:27:21 2025 +0000" }, "message": "Merge \"feat(mpam): test FEAT_MPAM_PE_BW_CTRL register access\"" }, { "commit": "0861d8310fe65168754d544a63c3fe2ef2f87211", "tree": "c2ddf1e56f45c0e04d2e675da8c8fbd4a4be95db", "parents": [ "38ce1c141611704cc4750f48264c9e5e45a2843e", "456cf6efad5133c8591a4aaade4d27c4ea1ef0f8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Sep 01 09:56:45 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 01 09:56:45 2025 +0000" }, "message": "Merge \"fix(arm): increase reserved DRAM1 mem for NS images\"" } ], "next": "9b1afa7fdeaa7a57900c3aa606626a9c9bf9e405" }