)]}'
{
  "log": [
    {
      "commit": "c1136a849fc21470313e4e852a22ae4b9db50440",
      "tree": "b6b5e8854589497f4e2d2c159f0bd2e590dcd8c5",
      "parents": [
        "d179ddcc64cac3b319b301cfe6c1bc32c1ea0eaf"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Apr 12 15:24:44 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed May 24 13:40:42 2023 +0100"
      },
      "message": "tftf(rme): intermittently switch to Realm while doing NS SVE ops\n\nInterleave NS SVE operations with Realm SVE operations and check whether\nSVE vectors are not affected.\n\nThis test also configures SVE op array and SVE vector length with random\nvalue in NS and Realm for test each iteration.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7a9ba4bd0d298f187baa3048ec622eb97ec3d99f\n"
    },
    {
      "commit": "0bbdc2dff449036aa65e4c53cd351d01484e0d23",
      "tree": "60f35abe7f72ade6409b3ffcd46262502a9b6885",
      "parents": [
        "ed7cdc8b28137ab15d9f263825674d156b3c2b30"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Apr 05 15:30:18 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Thu May 18 16:08:39 2023 +0100"
      },
      "message": "feat(rme): add SVE Realm tests\n\nVerifies Realm with SVE support. Below tests are added\n- Check whether RMI features reports proper SVE VL\n- Create SVE Realm and check rdvl result\n- Create SVE Realm with invalid VL and check if it fails\n- Create SVE Realm and test ID registers\n- Create non SVE Realm and test ID registers\n- Create SVE Realm and probe all supported VLs\n- Check RMM preserves NS ZCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I98a20f34ce72c7c1a353ed13678870168fa27c48\n"
    },
    {
      "commit": "369955abac0a083f57bfb787eeda82a511eb8fc0",
      "tree": "54a35fd1b033a708569c91f2dfb1e1516d690cec",
      "parents": [
        "38133fa69bfefab6e3d1d7461b42c806d36ae33b"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Apr 19 18:05:56 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri May 05 13:56:12 2023 +0100"
      },
      "message": "test(tftf): test FPU state registers context is preserved in RL/SE/NS\n\nTest that FPU/SIMD state are preserved during a randomly context switch\nbetween secure/non-secure/realm(R-EL1)worlds.\nFPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers,\nthe test runs for 1000 iterations with random combination of:\nSECURE_FILL_FPU, SECURE_READ_FPU, REALM_FILL_FPU, REALM_READ_FPU,\nNONSECURE_FILL_FPU, NONSECURE_READ_FPU commands,to test all possible\nsituations of synchronous context switch between worlds, while the\ncontent of those registers is being used.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I6da5fd334777000111924bb1239b77123a3dcea6\n"
    },
    {
      "commit": "2f30f1030f186760b20cd06b59832e332b2bdd0a",
      "tree": "e06899ba1be405650b4a15603429900dac67ccc2",
      "parents": [
        "2eb601b98a245df8a31e670a7dc322c2e8f153cf"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Mon Mar 13 19:37:46 2023 +0000"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Fri Mar 31 11:41:56 2023 +0200"
      },
      "message": "feat(rme): add PMU Realm tests\n\nThis patch adds Realm PMU payload tests with\nPMU interrupt handling.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2\n"
    },
    {
      "commit": "002e569021f2e219456d02dfe239218eba5c7cfa",
      "tree": "4c2ea2d7cce38d168ce5e03849498161d537f1c2",
      "parents": [
        "0fcfd47a5936180b754819ee928e8d5af173c5d2"
      ],
      "author": {
        "name": "nabkah01",
        "email": "nabil.kahlouche@arm.com",
        "time": "Mon Oct 10 12:36:46 2022 +0100"
      },
      "committer": {
        "name": "nabkah01",
        "email": "nabil.kahlouche@arm.com",
        "time": "Tue Nov 08 16:34:01 2022 +0000"
      },
      "message": "feat: tftf realm extension\n\nThis patch adds Realm payload management capabilities to TFTF\nto act as a NS Host, it includes creation and destruction of a Realm,\nmapping of protected data and creation of all needed RTT levels,\nsharing of NS memory buffer from Host to Realm by mapping of\nunprotected IPA, create REC and auxiliary granules, exit Realm\nusing RSI_HOST_CALL ABI.\n\nOlder realm_payload name is used now for only R-EL1 test cases,\nRMI and SPM test cases have been moved to new file tests-rmi-spm.\n\nNew TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk,\nas an offset from where R-EL1 payload memory resources start.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7\n"
    }
  ]
}