)]}' { "log": [ { "commit": "b419b9bc520ee87a1001daa8069ebc967663bb91", "tree": "44544d8b7e5c74c8c49aa0983240f5efb7c69184", "parents": [ "37232f0b3f977edb2b22b9cac276bdeef9aa696d" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 15 12:17:54 2026 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 15 12:36:13 2026 +0100" }, "message": "fix(pauth): restore inlining test instructions\n\nAfter the change [1] pauth instructions are no longer invoked in\nsequence, introducing bl/ret instructions in between test helpers\ninvocations. This pattern breaks Realm payload pauth test.\n\nRestore the inline asm function making sure the top level test helper\nis constituted of the well defined pauth instructions sequence.\n\n[1] https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/33144\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ic062aad8f4c85daf7741094eb9b5ef6769ee8dc6\n" }, { "commit": "37232f0b3f977edb2b22b9cac276bdeef9aa696d", "tree": "5f06c995cf12f702d0b537abca12e8d42f078f35", "parents": [ "705624475f6016053f301335deba10ed6ac0ea2d", "9159f55d156d279753be934d205a2f03648f784d" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jan 14 15:39:36 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 14 15:39:36 2026 +0000" }, "message": "Merge changes from topic \"gcc_9_build_fixes\"\n\n* changes:\n fix(pauth): allow compiling with older toolchains\n fix(ls64): drop ARMv8.7 compiler requirement\n fix(wfxt): allow build without ARMv8.7 capable compiler\n feat(helpers): introduce renamed and unprefixed sysreg wrapper\n feat(ls64): improve test\n" }, { "commit": "9159f55d156d279753be934d205a2f03648f784d", "tree": "5f06c995cf12f702d0b537abca12e8d42f078f35", "parents": [ "466428c259737a30842ab0453d3ef389186726f3" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Nov 04 16:09:07 2024 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Jan 13 13:18:04 2026 +0000" }, "message": "fix(pauth): allow compiling with older toolchains\n\nAt the moment compiling the PAUTH test with an older toolchain results\nin it complaining about the unsupported PAUTH instructions:\n\nError: selected processor does not support `paciasp\u0027\n\nThis has been relaxed in later binutils releases, as those instructions\nexecute as NOP on older CPUs, so are safe to deploy everywhere.\n\nSince those instructions are actually in the HINT space, provide wrapper\nfunctions in assembly, and instantiate them using their \"hint #x\"\nencodings, to make them compatible with any toolchain.\n\nThis allows compiling TFTF with the Ubuntu 20.04 provided toolchain.\n\nChange-Id: I2fa15a5e7cef334777fd89d05aa534c63e1ddab9\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "466428c259737a30842ab0453d3ef389186726f3", "tree": "69893f73215dd2e3d37c3b3abcae34d315409d5b", "parents": [ "19b3e3485c3d954e1f8008d433ef7a01362aa208" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Oct 30 17:48:15 2024 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Jan 13 13:17:45 2026 +0000" }, "message": "fix(ls64): drop ARMv8.7 compiler requirement\n\nThe LD64B and ST64B instructions are part of the ARMv8.7 architecture\nextension, and as such are unknown to older toolchains. The LS64 test is\nforcing the assembler to use ARMv8.7 extensions when compiling the LS64\ntests, which requires a recent toolchain - which the binutils shipping\nwith Ubuntu 20.04 are not.\n\nAdd a macro definition for the ls64b and st64b instructions, and use\nthat to generation the opcode at build time.\nThis allows us to drop the ARMv8.7 capable toolchain requirement for\nthis file.\n\nThe generared object is identical before and after this patch.\n\nChange-Id: Ibbf3f9bde26bbfc4d510e7df6f39860208eabf36\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "19b3e3485c3d954e1f8008d433ef7a01362aa208", "tree": "a0edf565f2741fef4a275e82a623bd1ac78f038f", "parents": [ "d829897c5cdd03835f65385ea1c4ce0e8c5ed558" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Oct 30 17:42:23 2024 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Jan 13 13:10:37 2026 +0000" }, "message": "fix(wfxt): allow build without ARMv8.7 capable compiler\n\nThe WFIT and WFET instructions are part of the ARMv8.7 architecture\nextension, and as such are unknown to older toolchains. The WFXT test is\nforcing the assembler to use ARMv8.7 extensions when processing the\ntest_wfxt.c file, which requires a recent toolchain - which the binutils\nshipping with Ubuntu 20.04 are not.\n\nHowever we just need the assembler to pass those inline assembly\ninstructions on, and we don\u0027t need the toolchain to use any v8.7\nfeatures otherwise. And since we properly check the availability of\nthe WFxT feature before, it is safe to be hardcoded in the binary.\n\nFortunately the WFxT instructions use a system register encoding, so we\ncan use the generic sysreg naming scheme (Sx_*_C*_C*_*) to encode WFxT\nwithout the toolchain needing to know about the new instructions.\n\nUse the newly introduced macro to instantiate sysreg access functions\nwithout a prefix to wrap the WFET and WFIT instructions. Then drop the\nARMv8.7 extension requirement from the .c file.\n\nThis allows TFTF to be compiled on an Ubuntu 20.04 system.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nChange-Id: If91cd88438c9dde5a4e2bb23f52a191a40be193b\n" }, { "commit": "d829897c5cdd03835f65385ea1c4ce0e8c5ed558", "tree": "0b922795a4c98dd3a16741ac474cdfc0e4d4642e", "parents": [ "ea09918488803953d3f947447eb0191de79b0e85" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Oct 30 17:42:23 2024 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Jan 13 13:01:51 2026 +0000" }, "message": "feat(helpers): introduce renamed and unprefixed sysreg wrapper\n\nSome new instructions are actually accesses to system registers\n(typically write-only), although their name or description will not\ngive this away.\nExamples are WFIT/WFET (wait-for-interrupt/exception-with-timeout).\n\nProvide a macro that allows to instantiate such function, but without\nthe mandatory \"write_\" prefix that the existing wrappers add.\n\nThis allows to define and use those functions even when the toolchain\ndoes not know (yet) about those new instructions.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nChange-Id: I78fcc02c594e21998c8695198f811aa76b372cd0\n" }, { "commit": "ea09918488803953d3f947447eb0191de79b0e85", "tree": "67496ceb808e7abb2da445a1b629f11aafad3416", "parents": [ "705624475f6016053f301335deba10ed6ac0ea2d" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Nov 04 13:42:11 2024 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Jan 13 12:59:34 2026 +0000" }, "message": "feat(ls64): improve test\n\nImprove the test coverage a bit, and use more complex bit patterns for\nthe write-read-back test. This helps to spot corruptions in the values.\nAlso LS64_ARRAYSIZE does not need to be hardcoded and in a header file,\nsince it\u0027s only used privately by the LS64 test code. Explain how the\nvalue of \"8\" comes about while at it.\n\nChange-Id: I889e614a4158c5fa5d3b9f5b056d8d10f2681755\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "705624475f6016053f301335deba10ed6ac0ea2d", "tree": "f31e8df30290bfdb8d7a7484dc4cc789966df43d", "parents": [ "92b772bfd865b7472a7640980daba8952d889e45", "c754ff703b8e4d72035354a2febc6d1c4b2e6f5c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 08 15:40:01 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 08 15:40:01 2026 +0000" }, "message": "Merge \"refactor: Change undef injection test to FEAT_GCS\"" }, { "commit": "c754ff703b8e4d72035354a2febc6d1c4b2e6f5c", "tree": "f31e8df30290bfdb8d7a7484dc4cc789966df43d", "parents": [ "92b772bfd865b7472a7640980daba8952d889e45" ], "author": { "name": "Balint Dobszay", "email": "balint.dobszay@arm.com", "time": "Thu Dec 18 12:39:58 2025 +0100" }, "committer": { "name": "Balint Dobszay", "email": "balint.dobszay@arm.com", "time": "Thu Jan 08 13:03:44 2026 +0100" }, "message": "refactor: Change undef injection test to FEAT_GCS\n\nCurrently the undef injection test relies on ENABLE_FEAT_FGT\u003d0 to enable\ntrapping of the HFGITR_EL2 register and test the injection mechanism.\nHowever, this cannot be used to test RF-A since it always assumes a\nnewer architecture version where FEAT_FGT is present and never trapped.\nThis commit refactors the test to rely on FEAT_GCS and try reading the\nGCSCR_EL2 register instead, which can be trapped both in TF-A and RF-A.\n\nChange-Id: I3c53cc36f49d6c6b2ce10be4041904aa35f46042\nSigned-off-by: Balint Dobszay \u003cbalint.dobszay@arm.com\u003e\n" }, { "commit": "92b772bfd865b7472a7640980daba8952d889e45", "tree": "2eafaf880f7c2c244f368bc4ec08cdef3b4b3a50", "parents": [ "293b28884816e28ecc04a8041a1a1204a5936825", "aa22af5f38ddf435e9de7a0a37a4a7d9275a502b" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jan 07 11:38:59 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 07 11:38:59 2026 +0000" }, "message": "Merge changes from topic \"bk/feat_cleanup\"\n\n* changes:\n fix(cpufeat): use \u003e\u003d instead of \u003d\u003d for csv2_2\n fix(cpufeat): use helpers for RNDR instead of inline assembly\n" }, { "commit": "293b28884816e28ecc04a8041a1a1204a5936825", "tree": "f0bafcf849797c05ca35052dfa3fa55dc1de785d", "parents": [ "2606d1cabe8c06e6c14745a172035f9a78aad83e", "8948dc98c4cd3d079e67aba36d7551575d625575" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Jan 06 15:36:41 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 06 15:36:41 2026 +0000" }, "message": "Merge \"fix(errata_abi): update EM_HIGHER_EL_MITIGATION to avoid failure\"" }, { "commit": "2606d1cabe8c06e6c14745a172035f9a78aad83e", "tree": "d2435282c340ef360cb77a82ff1277f1b1585e57", "parents": [ "c84feced6a93a55aab18c19d83bdac0c57166be3", "f71ccda5dcb6e1dab7a088a3e35715491484e926" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Dec 19 10:06:39 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 19 10:06:39 2025 +0000" }, "message": "Merge \"fix(Xilinx): remove logging from timer interrupt handler\"" }, { "commit": "c84feced6a93a55aab18c19d83bdac0c57166be3", "tree": "66313494b7f6cd2885ee9498351457cd7f408208", "parents": [ "6c7eb1c7589bae7b34fd7eb6f1e957dbf2cca6e2", "1bf7a81590ac18b91fd7f989a274c1a11fb953a9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 18 10:08:15 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Dec 18 10:08:15 2025 +0000" }, "message": "Merge \"plat: corstone1000: Add Cortex-A320 support\"" }, { "commit": "6c7eb1c7589bae7b34fd7eb6f1e957dbf2cca6e2", "tree": "3e9cd0157a5b7a59afcbd1ba5759697cd21dd906", "parents": [ "fc1d85e4ff5e04508375366e5e751112685196b4", "ec9d07ca7dabc133a11ce60ef1cfb38e367e3f0c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Dec 16 21:20:39 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Dec 16 21:20:39 2025 +0000" }, "message": "Merge \"feat(SMCCC): handle SMCCC_WA3 returning 0 on Neoverse V2\"" }, { "commit": "ec9d07ca7dabc133a11ce60ef1cfb38e367e3f0c", "tree": "3e9cd0157a5b7a59afcbd1ba5759697cd21dd906", "parents": [ "fc1d85e4ff5e04508375366e5e751112685196b4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Dec 16 17:29:42 2025 +0000" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Dec 16 13:33:48 2025 -0600" }, "message": "feat(SMCCC): handle SMCCC_WA3 returning 0 on Neoverse V2\n\nUpdate the SMCCC_WORKAROUND_3 tests to expect a return value of 0\ninstead of 1 for Neoverse V2 and handle this case gracefully.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I270457db40427e4db783f9d92d68ae336c991118\n" }, { "commit": "aa22af5f38ddf435e9de7a0a37a4a7d9275a502b", "tree": "7628103aec71f652d78956a4ceb656f1d64e1c4c", "parents": [ "601ba4b117a48be0dd1f80c49fa4deca74b9fb6f" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Dec 12 10:27:37 2025 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Dec 15 11:04:15 2025 +0000" }, "message": "fix(cpufeat): use \u003e\u003d instead of \u003d\u003d for csv2_2\n\nCSV2_2 has been superseded by CSV2_3 so the ID register won\u0027t match even\nthough the feature is implemented. Fix that to align with the ID\nregister forward compatibility scheme.\n\nChange-Id: I263a629e03d4e0074c959ac20b8f40c80109bbe7\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "601ba4b117a48be0dd1f80c49fa4deca74b9fb6f", "tree": "e8ac8ae4100d421f4c7a5f2a8c339c29df7f818e", "parents": [ "fc1d85e4ff5e04508375366e5e751112685196b4" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Dec 09 16:44:11 2025 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Dec 15 11:04:15 2025 +0000" }, "message": "fix(cpufeat): use helpers for RNDR instead of inline assembly\n\nThis gives backwards compatibility when FEAT_RNG isn\u0027t\nunderstood/enabled.\n\nChange-Id: Ic39eda6432cd27bae8a722e2a17da8ac35ffbae4\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "fc1d85e4ff5e04508375366e5e751112685196b4", "tree": "d1aee989a728cddce3b015a49ac45857466fb0de", "parents": [ "d3d2ca95fb3a87187f80cde40d3d4c22db166c63", "b71024c8d46b20de74df7f32e541acefbbc5740a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Dec 15 10:36:33 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Dec 15 10:36:33 2025 +0000" }, "message": "Merge changes I08d937ba,I485eed95,I637352ed,I2fd525f4,I78c02c1b\n\n* changes:\n feat(da): update RMI_VDEV_UNMAP to not expect vdev\n fix(da): add VCA caching\n fix: make dev map/unmap testcase comply with alp17\n refactor: create pdev/vdev helper module\n feat(realm): update DA related ABIs to spec alp17\n" }, { "commit": "b71024c8d46b20de74df7f32e541acefbbc5740a", "tree": "d1aee989a728cddce3b015a49ac45857466fb0de", "parents": [ "9db1b5f060e4adb8749e6fe5ddaee2ab272725d7" ], "author": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Fri Dec 05 17:47:58 2025 +0100" }, "committer": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Mon Dec 15 10:57:43 2025 +0100" }, "message": "feat(da): update RMI_VDEV_UNMAP to not expect vdev\n\nThis change is necessary to be able to run with linux kernel host.\n\nChange-Id: I08d937ba81f47888e857c621e73ee2c1c1f656ba\nSigned-off-by: Mate Toth-Pal \u003cmate.toth-pal@arm.com\u003e\n" }, { "commit": "9db1b5f060e4adb8749e6fe5ddaee2ab272725d7", "tree": "9001e55f5e4d210f6b51cc1c0762215de722a642", "parents": [ "830c21e5a77e13621a098d5376bc5ca733988b84" ], "author": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Fri Nov 28 13:05:17 2025 +0100" }, "committer": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Mon Dec 15 10:57:43 2025 +0100" }, "message": "fix(da): add VCA caching\n\nChange-Id: I485eed95af9063f83dc65ff44f01660b5989aa6c\nSigned-off-by: Mate Toth-Pal \u003cmate.toth-pal@arm.com\u003e\n" }, { "commit": "830c21e5a77e13621a098d5376bc5ca733988b84", "tree": "67c1e55f379a2da6936586d6ab248a7a0e11ea2d", "parents": [ "d1b0fb5990ef1862ae4e9b6129edf8a9d581279e" ], "author": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Fri Nov 28 14:50:57 2025 +0100" }, "committer": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Mon Dec 15 10:57:43 2025 +0100" }, "message": "fix: make dev map/unmap testcase comply with alp17\n\nThe updated vdev_[un]map command requires a VDEV parameter.\n\nChange-Id: I637352edb6ce2154144a8b354dc00abb60239d01\nSigned-off-by: Mate Toth-Pal \u003cmate.toth-pal@arm.com\u003e\n" }, { "commit": "d1b0fb5990ef1862ae4e9b6129edf8a9d581279e", "tree": "fce5ed4af379afb1ac3b843abf6a5b8d4c3c8951", "parents": [ "d600193ca2fd0c35dab3d663456b22f840f959b9" ], "author": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Fri Dec 05 14:41:39 2025 +0100" }, "committer": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Mon Dec 15 10:57:30 2025 +0100" }, "message": "refactor: create pdev/vdev helper module\n\nMove the DA related helper functions to a new module, to allow other\ntestcases to execute basic DA flows\n\nChange-Id: I2fd525f47a5629f94da4b3ea7b4da493a3fbf868\nSigned-off-by: Mate Toth-Pal \u003cmate.toth-pal@arm.com\u003e\n" }, { "commit": "d600193ca2fd0c35dab3d663456b22f840f959b9", "tree": "863fb973d3d154f436dcb9bb456ef77110966a5f", "parents": [ "d3d2ca95fb3a87187f80cde40d3d4c22db166c63" ], "author": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Fri Nov 28 12:48:47 2025 +0100" }, "committer": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Mon Dec 15 10:57:08 2025 +0100" }, "message": "feat(realm): update DA related ABIs to spec alp17\n\nChange-Id: I78c02c1bbffdf313043023959742f1c04d5ecd8e\nSigned-off-by: Mate Toth-Pal \u003cmate.toth-pal@arm.com\u003e\n" }, { "commit": "f71ccda5dcb6e1dab7a088a3e35715491484e926", "tree": "92bc3839c61c487009ea5aa9d43d41c45383535f", "parents": [ "d3d2ca95fb3a87187f80cde40d3d4c22db166c63" ], "author": { "name": "Sai Varun Venkatapuram", "email": "saivarun.venkatapuram@amd.com", "time": "Mon Nov 24 14:03:25 2025 +0530" }, "committer": { "name": "saivarun.venkatapuram@amd.com", "email": "saivarun.venkatapuram@amd.com", "time": "Mon Dec 15 06:34:12 2025 +0000" }, "message": "fix(Xilinx): remove logging from timer interrupt handler\n\nThe timer interrupt handler was calling INFO/ERROR logging functions\nfrom ISR context. These logging functions attempt to acquire the printf\nspinlock while holding timer_lock. This issue manifests during the\n\"Resume preempted STD SMC after PSCI SYSTEM SUSPEND\" test, where the\ntimer framework handler invokes the platform-specific handler.\n\nRemoved all logging calls from handler_timer() and simplified it to only\nperform essential interrupt handling: disable timer interrupts and read\nthe ISR register to clear the interrupt status. This follows the same\npattern used in the timer framework itself, where logging from ISR\ncontext is avoided.\n\nChange-Id: I7d1d6fa4806679c76f9b71d1a251a51406abfedd\nSigned-off-by: Sai Varun Venkatapuram \u003csaivarun.venkatapuram@amd.com\u003e\n" }, { "commit": "8948dc98c4cd3d079e67aba36d7551575d625575", "tree": "7c2ec75b9cd61b1abe2bded82d2a31f649c2d7e1", "parents": [ "d3d2ca95fb3a87187f80cde40d3d4c22db166c63" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 25 07:31:27 2025 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Dec 12 08:48:03 2025 +0000" }, "message": "fix(errata_abi): update EM_HIGHER_EL_MITIGATION to avoid failure\n\n The EM-ABI test for Versal Net was failing on Cortex-A78 AE erratum\n2376748. TF-A reports EM_HIGHER_EL_MITIGATION (ret0 \u003d\u003d 3) for this\n errata, but tftf logic only passed NOT_AFFECTED outside\nthe revision range and for higher el mitigation as failure.\n\nUpdated errata id 2376748 rxpx_high to 0x02.\n\nEM-ABI test for ZynqMP was failing on Cortex-A53 erratum 835769\nand 843419. TF-A reports EM_NOT_AFFECTED for both the errata id\u0027s\nwhile rxpx is inside the range resulting in tftf marking tests as\nfailure.\n\nUpdated errata ids 835769 and 843419 rxpx_high to 0x03.\n\nChange-Id: I5191a8683fafe69170d7c49d724c1c6a32d88f59\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "d3d2ca95fb3a87187f80cde40d3d4c22db166c63", "tree": "bfdf945b50d6732d3f68643a9b8d9541ecdc44b3", "parents": [ "361414e3604478057b5165c70cfe7274f0c28040", "d4cb8c05379a5c872327ac77b1b8af18602d26fb" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Dec 10 14:12:39 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 10 14:12:39 2025 +0000" }, "message": "Merge \"fix(fvp): make the FEAT_LS64 test easier to run\"" }, { "commit": "d4cb8c05379a5c872327ac77b1b8af18602d26fb", "tree": "bfdf945b50d6732d3f68643a9b8d9541ecdc44b3", "parents": [ "361414e3604478057b5165c70cfe7274f0c28040" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Dec 08 16:51:00 2025 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Dec 09 11:01:18 2025 +0000" }, "message": "fix(fvp): make the FEAT_LS64 test easier to run\n\nThe fvp doesn\u0027t have any regular memory that supports FEAT_LS64\ninstructions. Instead it has this weird FIFO device that is the only\nthing that can be targeted with an LS64 instruction. Depending on the\nbp.ls64_testing_fifo.op_type argument, this device will either return\nthe result or return it NOTed. Quite annoyingly, the default is to\nreturn with NOTing.\n\nSo check both the original value and its bitwise negative before failing\nthe test. This will allow the test to run regardless of the value of\nbp.ls64_testing_fifo.op_type.\n\nChange-Id: Ifd26f2a735e96ce4953e3d1cb9306c642750eca2\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "1bf7a81590ac18b91fd7f989a274c1a11fb953a9", "tree": "74087fbb6aa3756e09a680d074648b74d8f6ad7e", "parents": [ "361414e3604478057b5165c70cfe7274f0c28040" ], "author": { "name": "Michael Safwat", "email": "michael.safwat@arm.com", "time": "Tue Aug 26 11:20:01 2025 +0000" }, "committer": { "name": "Michael Safwat", "email": "michael.safwat@arm.com", "time": "Wed Dec 03 16:07:52 2025 +0000" }, "message": "plat: corstone1000: Add Cortex-A320 support\n\nSwitch platform to GICv3 (GIC-600) for Corstone-1000 with Cortex-A320\ndepending on CORSTONE1000_CORTEX_A320:\n - Define GICD and GICR bases.\n - Update the platform sources to include the GIC-V3 files.\n\nMove the NVM offset to prevent overlap with the TFTF firmware,\nwhich starts at 0x80000000 (TFTF_BASE).\n\nIntroduce a new skip file tests_to_skip_cortex_a320 to be used when building\nTF-A-Tests with CORSTONE1000_CORTEX_A320\u003d1. This ensures that tests which\nare not supported or cause traps on Corstone-1000 with Cortex-A320 are\nconsistently skipped during execution.\n\nSkipped entries:\n CPU extensions/AMUv1 suspend/resume\n CPU extensions/Use trace buffer control Registers\n\nChange-Id: I0745f12b84b3a7cd7577f8eaec0a1e8d5cb65875\nSigned-off-by: Michael Safwat \u003cmichael.safwat@arm.com\u003e\nSigned-off-by: Harsimran Singh Tungal \u003charsimransingh.tungal@arm.com\u003e\n" }, { "commit": "361414e3604478057b5165c70cfe7274f0c28040", "tree": "e0820fbc3cdf50fa9e7308d3c04e17ed75efe28a", "parents": [ "3b3d800133081b48482b1205a32671b82bc2b640", "b5ca6dafcf0a9866e311557613b705215f7ef202" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Nov 27 15:15:26 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 27 15:15:26 2025 +0000" }, "message": "Merge \"fix(pauth): add an isb after restoring pauth registers so they take effect\"" }, { "commit": "b5ca6dafcf0a9866e311557613b705215f7ef202", "tree": "e0820fbc3cdf50fa9e7308d3c04e17ed75efe28a", "parents": [ "3b3d800133081b48482b1205a32671b82bc2b640" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Nov 27 10:27:19 2025 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Nov 27 10:27:19 2025 +0000" }, "message": "fix(pauth): add an isb after restoring pauth registers so they take effect\n\nWithout the isb the write to the APIA key may not take effect until some\nlater point. When context is restored and execution returns to the\npre-suspend path the key must be the same otherwise the authentication\nwill fail.\n\nChange-Id: Iada89dd17eb0f3ed85bbc64087a27be6ab0b242a\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "3b3d800133081b48482b1205a32671b82bc2b640", "tree": "c78fc318385711b3195d40079670bb2e8951ffe4", "parents": [ "d2afaf190c7bc0e82f0c928d7b554df1fdf16e1b", "0c62f73cc4786ac489c0fc1b5fd8ad2744a8d232" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Nov 24 14:21:16 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 24 14:21:16 2025 +0000" }, "message": "Merge \"docs(release): changelog for v2.14 release\"" }, { "commit": "d2afaf190c7bc0e82f0c928d7b554df1fdf16e1b", "tree": "9e5d8120764591fc172212f4b84a59354879bebc", "parents": [ "96139e5482164db421c076982b3408fd430ce1c4", "6ae7ee4b404057d71d68df972ccdef25cbdcfe79" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Nov 20 15:40:04 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 20 15:40:04 2025 +0000" }, "message": "Merge \"fix(docs): correct `--no-ff` -\u003e `--ff-only`\"" }, { "commit": "6ae7ee4b404057d71d68df972ccdef25cbdcfe79", "tree": "9e5d8120764591fc172212f4b84a59354879bebc", "parents": [ "96139e5482164db421c076982b3408fd430ce1c4" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Nov 20 11:45:50 2025 +0000" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Nov 20 11:45:52 2025 +0000" }, "message": "fix(docs): correct `--no-ff` -\u003e `--ff-only`\n\nThe `--no-ff` flag always creates a merge commit; that\u0027s the opposite of\nwhat we meant when this documentation was updated. Use `--ff-only` to\nrequire fast-forwards pulls only.\n\nChange-Id: Ia49ddccbfc998e403e900e9fa86f55129fe521b3\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "96139e5482164db421c076982b3408fd430ce1c4", "tree": "7ecc4db4ca0ac58f82ee882eb4b95870087ea0c4", "parents": [ "7a54ce374b9c42e0ba6804ab41f3f73a363f31bd", "762954962f0d7fc1470ecb39ac2ba407e6810ce0" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Nov 19 16:59:57 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 19 16:59:57 2025 +0000" }, "message": "Merge changes from topic \"hm/release\"\n\n* changes:\n chore: bump libeventlog to latest version\n fix(docs): set language to \"en\" in sphinx config\n chore(docs): reconcile submodule dep info\n" }, { "commit": "0c62f73cc4786ac489c0fc1b5fd8ad2744a8d232", "tree": "f2649c142e9ef1b0fbb8cedc6e2a6559613a38ac", "parents": [ "762954962f0d7fc1470ecb39ac2ba407e6810ce0" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Nov 14 09:27:51 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Nov 19 14:40:58 2025 +0000" }, "message": "docs(release): changelog for v2.14 release\n\nChange-Id: Ib35085f4f0e6271d955a437e45df946596e95808\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "762954962f0d7fc1470ecb39ac2ba407e6810ce0", "tree": "7ecc4db4ca0ac58f82ee882eb4b95870087ea0c4", "parents": [ "aaf80b91325ca111dde7acbca48b7aca9f4e923e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Nov 19 13:45:08 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Nov 19 14:40:58 2025 +0000" }, "message": "chore: bump libeventlog to latest version\n\nPulls in a fix to the version specified in the CMake file.\n\nChange-Id: Ic81119a20fa2c8bc59cc7cf2ba623171a5cc4edd\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "aaf80b91325ca111dde7acbca48b7aca9f4e923e", "tree": "df0ee47680a051b0afefe39b033de2bec1a14894", "parents": [ "5ef5d1c2654477b22eb10879c091d2a0e50b3540" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Nov 17 16:52:53 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Nov 19 14:40:58 2025 +0000" }, "message": "fix(docs): set language to \"en\" in sphinx config\n\nSphinx complains about the lack of a language in the configuration. Our\ndocumentation is in English, so it makes sense to have that as an\nexplicit setting the config - TF-A already does this.\n\nChange-Id: Iacadc870116e189080febbd986eead7dfd9a964d\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "5ef5d1c2654477b22eb10879c091d2a0e50b3540", "tree": "3356080f00414ab4f826ac9955f04f95b6e44fa6", "parents": [ "7a54ce374b9c42e0ba6804ab41f3f73a363f31bd" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Nov 17 11:34:31 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Nov 19 14:40:58 2025 +0000" }, "message": "chore(docs): reconcile submodule dep info\n\nRemove explicit submodule version info and refer instead to the Git\nsubmodules file. Also add some information for users about how to keep\nthe repo in sync.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: Iad89dc5f726bb64c65e91a505ac51cc73a905933\n" }, { "commit": "7a54ce374b9c42e0ba6804ab41f3f73a363f31bd", "tree": "cf0a7f6ee8706ad987a8447572d0a06e3b312b6d", "parents": [ "98aec2a7a1e31374075495f74623854a6fb100a4", "b82b947960452cf1ab45588f2c747805ebf128d1" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Nov 19 09:14:50 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 19 09:14:50 2025 +0000" }, "message": "Merge \"chore: move mbedtls into contrib\"" }, { "commit": "b82b947960452cf1ab45588f2c747805ebf128d1", "tree": "cf0a7f6ee8706ad987a8447572d0a06e3b312b6d", "parents": [ "98aec2a7a1e31374075495f74623854a6fb100a4" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Nov 17 12:11:26 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Nov 19 09:14:30 2025 +0000" }, "message": "chore: move mbedtls into contrib\n\nAlign with other submodules so they all live in the same subdirectory.\n\nChange-Id: I784d69f4473fa06fea7e0c1ec0d53abf2c8ca12f\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "98aec2a7a1e31374075495f74623854a6fb100a4", "tree": "428ea2102f6b3b4ad45bcf8dca6afe29edfc312d", "parents": [ "03c7b1302606b7588738051960a94778c64eb838", "11cae9599179c152a680c5b9ec862269a8bedffb" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Nov 14 08:53:56 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 14 08:53:56 2025 +0000" }, "message": "Merge \"fix(gic): fix gic_v2 spi irq handling\"" }, { "commit": "11cae9599179c152a680c5b9ec862269a8bedffb", "tree": "428ea2102f6b3b4ad45bcf8dca6afe29edfc312d", "parents": [ "03c7b1302606b7588738051960a94778c64eb838" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Nov 13 16:18:22 2025 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Nov 13 16:20:31 2025 -0600" }, "message": "fix(gic): fix gic_v2 spi irq handling\n\nWith commit@055adff8d7e5431174672c7aac0bc530c4e7a778\ncheck for is_plat_spi was removed in `tftf_irq_enable` this is\ncorrectly handled from re-routing but not the case in gic_v2 handling.\n\nChange-Id: Id22f2dcc5d9de3950bc210139869ff284c636719\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "03c7b1302606b7588738051960a94778c64eb838", "tree": "9a874d0eafa72b5fdd70e757c08e2b5fbd19c530", "parents": [ "c48cf81af362d9b2d96e0ab4d00b56f4ec6648bf", "7f7ffe503bdb05a9135e5685689931914fdbcbc9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Nov 10 15:52:59 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 10 15:52:59 2025 +0000" }, "message": "Merge \"feat(idte3): add support to detect and test FEAT_IDTE3\"" }, { "commit": "7f7ffe503bdb05a9135e5685689931914fdbcbc9", "tree": "9a874d0eafa72b5fdd70e757c08e2b5fbd19c530", "parents": [ "c48cf81af362d9b2d96e0ab4d00b56f4ec6648bf" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Mon Nov 03 15:50:11 2025 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Sun Nov 09 12:22:52 2025 -0600" }, "message": "feat(idte3): add support to detect and test FEAT_IDTE3\n\nAdd new defines for ID_AA64MMFR2_EL1.IDS and SCR_EL3.TID3/TID5\nto support FEAT_IDTE3 detection. A helper function is added to\ncheck for this feature, and the SMCCC feature availability test\nis updated to verify IDTE3 presence.\n\nChange-Id: Ib9471a838381439214a61feeed96796e406a9cb7\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "c48cf81af362d9b2d96e0ab4d00b56f4ec6648bf", "tree": "37efdc09d3903cb0a54227ff24d529e5b14c6989", "parents": [ "9ad97fa64ff00dcf03d81e8e60a9848257e6bd24", "3bef40952bbb4a006a952948c2d71f5711133fbb" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Nov 07 18:12:40 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 07 18:12:40 2025 +0000" }, "message": "Merge changes from topic \"mb/lfa-rmm-test\"\n\n* changes:\n test(realm): perform LFA of RMM with Realm Payload\n feat(lfa): add multi-CPU test for LFA of RMM\n feat(lfa): add LFA SMCs tests using a single CPU\n" }, { "commit": "9ad97fa64ff00dcf03d81e8e60a9848257e6bd24", "tree": "a722f9f0fb5aaa48e685ddafccac89ab40fb4ce2", "parents": [ "80b143f91f178b4b3e62015aba2a9b510f0af20c", "cb38be8da24189798aad6b02ff95c7c30cbc2fce" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Nov 07 17:40:17 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 07 17:40:17 2025 +0000" }, "message": "Merge \"test(SMCCC): update SMCCC_ARCH_FEATURE_AVAILABILITY test\"" }, { "commit": "cb38be8da24189798aad6b02ff95c7c30cbc2fce", "tree": "a722f9f0fb5aaa48e685ddafccac89ab40fb4ce2", "parents": [ "80b143f91f178b4b3e62015aba2a9b510f0af20c" ], "author": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Thu Nov 06 12:06:46 2025 -0600" }, "committer": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Fri Nov 07 11:09:12 2025 -0600" }, "message": "test(SMCCC): update SMCCC_ARCH_FEATURE_AVAILABILITY test\n\nUpdate the SMCCC_ARCH_FEATURE_AVAILABILITY test\nto include FEAT_MEC support.\n\nSince MDCR_EL3.EnPM2 bit is set unconditionally, even when\nFEAT_PMUv3p9 is not present, modify the check to be always\npresent.\n\nSigned-off-by: Sona Mathew \u003cSonaRebecca.Mathew@arm.com\u003e\nChange-Id: Ifd727c15fe03afce5fcb2c04ee1d19b7b06a3608\n" }, { "commit": "3bef40952bbb4a006a952948c2d71f5711133fbb", "tree": "9a64b37522e048e095d81c421ccb1f5e6352f599", "parents": [ "fd0680e77da168991bc78fe9b316c1a15bf66a74" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jan 28 10:51:05 2025 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Nov 07 11:26:13 2025 +0000" }, "message": "test(realm): perform LFA of RMM with Realm Payload\n\nAdd a test to execute the Realm payload with the existing RMM,\nthen perform LFA of RMM, and finally execute the Realm payload\nagain to ensure it runs with the newly activated RMM.\n\nChange-Id: Ifbba462506c6b1c0c86aba1ac22a19cd414f54d9\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "fd0680e77da168991bc78fe9b316c1a15bf66a74", "tree": "90b1a2fc8f8bb5a34e9440f358f922e44b4879c2", "parents": [ "0be9d87528948d1e3c659f674c93ee40bccaeb7b" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Nov 06 20:46:22 2025 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Nov 07 11:25:27 2025 +0000" }, "message": "feat(lfa): add multi-CPU test for LFA of RMM\n\nAdd LFA testing on multiple CPUs. Executed full LFA\ntest for RMM live activation.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I22f9ec7185adddc91b8f5c5ebae9128f31ef0e2a\n" }, { "commit": "0be9d87528948d1e3c659f674c93ee40bccaeb7b", "tree": "5193b6ee09b54984a420de1465438c9ff0c2274d", "parents": [ "80b143f91f178b4b3e62015aba2a9b510f0af20c" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Aug 16 09:13:28 2024 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Nov 07 11:23:24 2025 +0000" }, "message": "feat(lfa): add LFA SMCs tests using a single CPU\n\nAdd a LFA tests for single CPU without the Activate SMC.\nAlso, include a negative test case where the firmware\nis unavailable for activation during the Prime phase,\nresulting in a failure.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I9fff281f77de87580f5b3c1fecd69fbf0f5d1f2d\n" }, { "commit": "80b143f91f178b4b3e62015aba2a9b510f0af20c", "tree": "01c334accfb4b579553d628632229284b74594a9", "parents": [ "062073104f71dde3054755add4b76519b7526811", "0860f29e52eaf265cf824c1bd5104ca8197c4d54" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Nov 05 13:51:09 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 05 13:51:09 2025 +0000" }, "message": "Merge \"feat(smccc): add FEAT_EBEP to FEATURE_AVAILABILITY\"" }, { "commit": "0860f29e52eaf265cf824c1bd5104ca8197c4d54", "tree": "01c334accfb4b579553d628632229284b74594a9", "parents": [ "062073104f71dde3054755add4b76519b7526811" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Nov 04 10:14:31 2025 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Nov 04 13:21:06 2025 +0000" }, "message": "feat(smccc): add FEAT_EBEP to FEATURE_AVAILABILITY\n\nChange-Id: Ia545d5c226d3504cd821c704e765542b7d2b838c\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "062073104f71dde3054755add4b76519b7526811", "tree": "cd369dc6cc274616abe1e0f9560470a6c66066aa", "parents": [ "355710eb888e89fb739c5492639ddbdc7c0e9897", "66e1ec89263e3454eb5a7210cad96df11ba75abb" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Nov 04 09:56:29 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 04 09:56:29 2025 +0000" }, "message": "Merge changes from topic \"bk/gicv5_full\"\n\n* changes:\n feat(realm): set the PMU IRQ number depending on GIC version\n feat(fvp): set the timer IRQ number depending on GIC version\n refactor(gic): defer IRQ handler management to the GIC driver\n refactor(gic): make the concept of SGI generic\n feat(gicv5): add a GICv5 driver\n feat(gicv5): add GICv5 instructions and register accessors\n" }, { "commit": "66e1ec89263e3454eb5a7210cad96df11ba75abb", "tree": "cd369dc6cc274616abe1e0f9560470a6c66066aa", "parents": [ "9134748e4a1faabd97cb29fa71069cd656107a4a" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 16:09:52 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 15:17:24 2025 +0000" }, "message": "feat(realm): set the PMU IRQ number depending on GIC version\n\nDespite the PPI number being the same, the INTID is different - it needs\nto be labelled as PPI on GICv5. Add a helper to switch this.\n\nChange-Id: I600ab121135b0826f8405202de222943392c36ec\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "9134748e4a1faabd97cb29fa71069cd656107a4a", "tree": "4d56558da5148277f1dd71831263000367062549", "parents": [ "055adff8d7e5431174672c7aac0bc530c4e7a778" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:53:57 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "feat(fvp): set the timer IRQ number depending on GIC version\n\nChange-Id: I8039ee2104effdf052141e52059d45675ca09127\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "055adff8d7e5431174672c7aac0bc530c4e7a778", "tree": "2968cec4c85ea200c4838a268ccd13dba9a5c7ad", "parents": [ "6d144db95cd1ee317bf66efade0fd5d4e0909c3c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:34:12 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "refactor(gic): defer IRQ handler management to the GIC driver\n\nInterrupt groups are not generic between GIC versions. SGIs and eSPIs\ndisappear, while SPIs and LPIs subtly change function. So abstract all\nof this away and hide it behind each individual GIC driver.\n\nChange-Id: Iaa55014b2940969508b290736c43134688e8c422\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "6d144db95cd1ee317bf66efade0fd5d4e0909c3c", "tree": "0b57d1214fe208e82a5b56ba03b06cec0074700f", "parents": [ "e5629bd4c6ab6088e21e7f4e2f4a27495945e21a" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:04:53 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "refactor(gic): make the concept of SGI generic\n\nSoftware generated interrupts (SGIs) are a GICv2/3/4 concept. However,\nthey are deeply embedded in how TFTF handles wake ups. This patch\npromotes the SGI to an abstract concept that can be performed\nindependently of the interrupt controller, largely the same as it is\nused today. To do that the interrupt interface for an SGI is separated\nfrom the general IRQ and each SGI is assigned a linear index from 0\nonwards. Translating from SGI to IRQ is done via a hook in arm_gic.c\nthat will be multiplexed to the appropriate driver. For GIC \u003c\u003d v3 this\nis a thin wrapper around the identity mapping as SGIs map to INTIDs from\n0 through 15. For GICv5 the mapping is different and an SGI is an LPI\nand calculated as recommended by chapter 2.5 in the spec.\n\nAdditionally, the definitions of SGI numbers are made generic as no\nplatform has utilised the difference.\n\nChange-Id: I7e6a5fbe655098c5e235b98f6dda8a14619a5904\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "e5629bd4c6ab6088e21e7f4e2f4a27495945e21a", "tree": "4034af170e7cd7109f9e4fdf2ba91d8438f2f495", "parents": [ "b731b11b6ad6db96ff34fc2a430cbeef56ed14e5" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 16 11:45:34 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "feat(gicv5): add a GICv5 driver\n\nChange-Id: I10e125c3866e50ed5adde2e4944245f47e50f2e6\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "b731b11b6ad6db96ff34fc2a430cbeef56ed14e5", "tree": "7d4c7a173bb10d0338ad1a38f38592c8db8ca9e5", "parents": [ "355710eb888e89fb739c5492639ddbdc7c0e9897" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jun 26 12:25:35 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "feat(gicv5): add GICv5 instructions and register accessors\n\nChange-Id: I1960b6f0a3bf00ae31c0baadd6202e5d3c894600\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "355710eb888e89fb739c5492639ddbdc7c0e9897", "tree": "1e3ffddb7a8bc8e05494121fcba4ad4435255db1", "parents": [ "49e1706dd57ffc22494a3a47e05e5a28e984675d", "fe1c9b82b5ecc91778eada953135051a180b5237" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Nov 03 11:45:37 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 03 11:45:37 2025 +0000" }, "message": "Merge \"feat(planes): test SIMD access from plane N\"" }, { "commit": "49e1706dd57ffc22494a3a47e05e5a28e984675d", "tree": "12edd4aed8d7989463e1c0226f1aaa91dd195504", "parents": [ "bedd612ed9bc80d60dda50bddeb3823eb62bde21", "6a1ffac35e88673635a124c2a100696d51b8bea9" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Oct 31 15:02:53 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 31 15:02:53 2025 +0000" }, "message": "Merge \"fix(debugv8p9): fix access to mdselr_el1\"" }, { "commit": "6a1ffac35e88673635a124c2a100696d51b8bea9", "tree": "12edd4aed8d7989463e1c0226f1aaa91dd195504", "parents": [ "bedd612ed9bc80d60dda50bddeb3823eb62bde21" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Oct 29 15:32:26 2025 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Oct 30 20:14:36 2025 -0500" }, "message": "fix(debugv8p9): fix access to mdselr_el1\n\nWhen 16 or fewer breakpoints are implemented, MDSELR_EL1 is\nimplemented as RAZ/WI, it is IMPLEMENTATION DEFINED whether\nthe trap controls have any effect on accesses to MDSELR_EL1.\n\nRef: https://developer.arm.com/documentation/111107/2025-09/AArch64-Registers/MDSELR-EL1--Breakpoint-and-Watchpoint-Selection-Register?lang\u003den\n\nChange-Id: I40215ca074e01d5e5dfb184c6aba656fc9077018\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "fe1c9b82b5ecc91778eada953135051a180b5237", "tree": "5c9df9ece7049e83dd728aa62d96de6c7a2122b2", "parents": [ "bedd612ed9bc80d60dda50bddeb3823eb62bde21" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Oct 02 18:07:49 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Oct 30 13:02:11 2025 +0000" }, "message": "feat(planes): test SIMD access from plane N\n\nAdd tests to exercise access to SIMD functinality from Plane N.\nThe tests alternate execution of \u0027rdvl\u0027 instruction from Plane 0 and\nPlane N in different sequences and combinations of TRAP_SIMD values.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I55b9bf55b43b72419e8244f228c505a58c2a819c\n" }, { "commit": "bedd612ed9bc80d60dda50bddeb3823eb62bde21", "tree": "0279fe90658bd378acdfaa5f34d67ce9ce1e7c2b", "parents": [ "bf96263e9162322d57a512fc0e744f08ec86da1e", "5955a6208de318a67dc41a3900e868c7d0378c4d" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Wed Oct 29 16:21:42 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 29 16:21:42 2025 +0000" }, "message": "Merge \"docs: fix Sphinx build errors in maintainers and platform docs\"" }, { "commit": "bf96263e9162322d57a512fc0e744f08ec86da1e", "tree": "4b27b1a61763ef28567a156fd2f551ef73aee0c0", "parents": [ "8530c4e871eb6544c78d1871b843715ff518e7ea", "7919d6dee09f135ed7178cab22df405d7aa530ad" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Oct 28 11:15:17 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 28 11:15:17 2025 +0000" }, "message": "Merge \"docs: update toolchain requirements to 14.3.Rel1\"" }, { "commit": "8530c4e871eb6544c78d1871b843715ff518e7ea", "tree": "93314ef0e22cfa4bcff22c07b59918eca21c487e", "parents": [ "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e", "b32ccfe7950e0dfd33aa89b465274a2b38a0950f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Oct 27 11:06:13 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 27 11:06:13 2025 +0000" }, "message": "Merge \"test(sdei): SDEI event signaling state (registered, enabled, unmasked)\"" }, { "commit": "5955a6208de318a67dc41a3900e868c7d0378c4d", "tree": "c7e948e75b457aa2497b0f045bebde921653b79e", "parents": [ "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Oct 24 13:44:27 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Oct 24 14:27:46 2025 -0500" }, "message": "docs: fix Sphinx build errors in maintainers and platform docs\n\nDefine substitutions for |M|, |G| and |F| in maintainers.rst\nand add missing GitHub link targets to resolve Sphinx “undefined\nsubstitution” and “unknown target name” errors.\n\nAlso fixed indentation , code-block directive and\nthe underline length errors.\n\nChange-Id: I8a25a2c9a063ce04ef8e538e82d96c26ae82361c\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "b32ccfe7950e0dfd33aa89b465274a2b38a0950f", "tree": "93314ef0e22cfa4bcff22c07b59918eca21c487e", "parents": [ "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Thu Feb 27 23:48:45 2025 +0100" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Oct 24 14:26:27 2025 -0500" }, "message": "test(sdei): SDEI event signaling state (registered, enabled, unmasked)\n\nThis patch adds a test to check whether only a registered, enabled\nand unmasked SDEI event can be signaled successfully.\n\nIn other conditions the event signaling process should fail early.\n\nChange-Id: I3ce76ed060bc32648cea43dcce65b707d97c3a78\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "7919d6dee09f135ed7178cab22df405d7aa530ad", "tree": "f2098de161848b1ee8951448fd86aa7c2c008cbd", "parents": [ "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Oct 02 15:06:51 2025 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Oct 24 09:26:13 2025 +0100" }, "message": "docs: update toolchain requirements to 14.3.Rel1\n\nTF-A tests have been validated with toolchain version 14.3.Rel1.\nUpdate documentation to reflect this as the current supported version.\n\nChange-Id: I3d88f2eec209c60e16b133392c2ed72b4b4acc4a\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "ec5c5cc80cddc74594fe7088f446d217bb3c5e7e", "tree": "b5f90cc65be3aa63bebaaeda7bb4c5919dc55e48", "parents": [ "f543e954e2887cf5927b05ae19759c35710c4e4d", "fa0259bf3db29c31d853ea1c0b1824e28719162f" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Oct 23 09:58:33 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 23 09:58:33 2025 +0000" }, "message": "Merge \"feat(mbedtls): update mbedtls 3.6.5\"" }, { "commit": "fa0259bf3db29c31d853ea1c0b1824e28719162f", "tree": "b5f90cc65be3aa63bebaaeda7bb4c5919dc55e48", "parents": [ "f543e954e2887cf5927b05ae19759c35710c4e4d" ], "author": { "name": "Slava Andrianov", "email": "slava.andrianov@arm.com", "time": "Thu Oct 16 14:32:48 2025 -0500" }, "committer": { "name": "Slava Andrianov", "email": "slava.andrianov@arm.com", "time": "Tue Oct 21 16:32:48 2025 -0500" }, "message": "feat(mbedtls): update mbedtls 3.6.5\n\nChange-Id: Iad177d211b86b3b92f7f3c8c3738f63132895441\nSigned-off-by: Slava Andrianov \u003cslava.andrianov@arm.com\u003e\n" }, { "commit": "f543e954e2887cf5927b05ae19759c35710c4e4d", "tree": "d002b09e7453e10e2ea444ce942c5b98d44f10a7", "parents": [ "4c04f4a824aa3fa2b58b399ebdfc7a5d4248b17b", "466f182aefcd2523f7a12b6315e23507b13c97a6" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Oct 16 15:30:18 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 16 15:30:18 2025 +0000" }, "message": "Merge changes from topic \"amd_pm_tests\"\n\n* changes:\n feat(amd): add test for get reset status EEMI API\n feat(amd): add test for force powerdown EEMI API\n feat(amd): add test for query data EEMI API\n feat(amd): add test for self suspend EEMI API\n feat(amd): add test for pll EEMI APIs\n feat(amd): add test for system shutdown EEMI API\n feat(amd): add test for operating characteristics EEMI API\n feat(amd): add test for TF-A register sgi API\n feat(amd): add test for TF-A feature check API\n feat(amd): add test for trustzone version API\n feat(amd): add test for init finalize EEMI API\n feat(amd): add test for pin EEMI APIs\n feat(amd): add test for clock EEMI APIs\n feat(amd): add test for node EEMI APIs\n feat(amd): add test for IOCTL EEMI API\n feat(amd): add test for register notifier EEMI API\n feat(amd): add platform specific test cases\n" }, { "commit": "4c04f4a824aa3fa2b58b399ebdfc7a5d4248b17b", "tree": "a14e26c5df9b2f417ce758ce619602896747fabd", "parents": [ "a75b61043527655ffdca008a8d47fbb4cc17431b", "f02375764dad0e5f1531fbdb2a17370497b27858" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Tue Oct 14 16:29:22 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 14 16:29:22 2025 +0000" }, "message": "Merge changes I5a64f51b,I89a45bec\n\n* changes:\n feat(smccc): availability test: add FEAT_AIE and FEAT_PFAR checks\n fix(spe): turn assert into warning for newer SPE versions\n" }, { "commit": "a75b61043527655ffdca008a8d47fbb4cc17431b", "tree": "32db39cc1beed611b52f1c7aa44b3ca0a9e993ea", "parents": [ "ed52bf5682c652e9d82a5a2e6869774bb300ed08", "adc86ecbe0aff82859a5f2f215d8199b77409413" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Oct 14 12:11:52 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 14 12:11:52 2025 +0000" }, "message": "Merge \"fix(versal2): correct SLCR base for timer interrupt\"" }, { "commit": "f02375764dad0e5f1531fbdb2a17370497b27858", "tree": "48babcccbde99dc320ebe8d051ea344cc6af9723", "parents": [ "0fe74ee1f2b40f416d5e5945441f1dada67c6ec0" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Oct 07 15:08:17 2025 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Oct 13 15:18:59 2025 +0100" }, "message": "feat(smccc): availability test: add FEAT_AIE and FEAT_PFAR checks\n\nARMv8.8 introduced FEAT_PFAR and FEAT_AIE, which each have a trap bit\nin SCR_EL3.\n\nAdd the respective ID register fields and check for those two features\nin the SMCCC feature availability test, to verify that EL3 has enabled\nthe right bits in the SCR_EL3 availability value.\n\nFix some whitespace damage in the MEC field definitions on the way.\n\nChange-Id: I5a64f51ba6bcc04c271ddf1e7456ed584da6a1af\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "0fe74ee1f2b40f416d5e5945441f1dada67c6ec0", "tree": "a5b9d53613499f7160058eee0a911cf599a3f6d5", "parents": [ "ed52bf5682c652e9d82a5a2e6869774bb300ed08" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Oct 09 18:15:35 2025 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Oct 13 15:18:43 2025 +0100" }, "message": "fix(spe): turn assert into warning for newer SPE versions\n\nFEAT_SPE gets some updates in the architecture from time to time,\nincreasing the value in the ID_AA64DFR0_EL1.PMSVer field. The Arm ARM\npromises that higher numbers only add features, so any tests for a lower\nversion should always be valid, even if the hardware supports more\nfeatures.\n\nTurn the assert into a warning, so we still log that the test might need\nto be upgraded, but don\u0027t fail the test anymore.\n\nChange-Id: I89a45bec9b22dae15f754a22f310fc6ea8def714\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "ed52bf5682c652e9d82a5a2e6869774bb300ed08", "tree": "4a4cb1c859ce181d3a0dbb9ca6975d042d851a68", "parents": [ "a297106fffd8ceea66065ca17a25bb641ce2028b", "6db21fa1e8ef4df32d743b178d86489c8da3db4a" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Oct 09 17:14:48 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 09 17:14:48 2025 +0000" }, "message": "Merge \"fix(smccc): make feat discovery testcase to use SMC64\"" }, { "commit": "a297106fffd8ceea66065ca17a25bb641ce2028b", "tree": "39a89d1b3ea5b81eefe52296188d8fff72e348aa", "parents": [ "c72fd11ff7cd96fbce3f1052b72ccda02134eca4", "b2ca2dc3806ef8cebd55c568c8873d300763d641" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Oct 09 10:07:37 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 09 10:07:37 2025 +0000" }, "message": "Merge \"fix(ff-a): no NS attribute in hypervisor retrieve request\"" }, { "commit": "c72fd11ff7cd96fbce3f1052b72ccda02134eca4", "tree": "f94be6511eceb4eb72c82769ce47ddaaa4027ef6", "parents": [ "595833773c4de78f4e2d53217f704b453625ab5a", "3bb031c9f8ed31fbdbfe6241f7f46e29f2a1c2a3" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Oct 08 21:51:29 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 08 21:51:29 2025 +0000" }, "message": "Merge \"fix(fuzzing): resolve script issue\"" }, { "commit": "6db21fa1e8ef4df32d743b178d86489c8da3db4a", "tree": "5c60256ba83d3f812e34fdee37a61357e8fdef69", "parents": [ "595833773c4de78f4e2d53217f704b453625ab5a" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Sep 19 10:17:06 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Oct 08 14:38:54 2025 -0500" }, "message": "fix(smccc): make feat discovery testcase to use SMC64\n\nCommit a0fa44b48 fixed SMCCC_ARCH_FEAT_AVAILABILITY to use aarch64\nvalue, this patch updates tftf to reflect the change.\n\nChange-Id: I29fa8c5dca21a350dad4895822c87357c1e71a88\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "b2ca2dc3806ef8cebd55c568c8873d300763d641", "tree": "192aac3add05bf9e116b48761d72d335a750e9f4", "parents": [ "595833773c4de78f4e2d53217f704b453625ab5a" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 08 12:26:06 2025 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 08 15:57:23 2025 +0100" }, "message": "fix(ff-a): no NS attribute in hypervisor retrieve request\n\nWhen validating the return of the hypervisor retrieve request, tftf\nwas expecting the NS attribute. Which is not meaningful in the context\nof the NWd.\n\nChange-Id: Icee86f458b14b67716ceea208f56e68dd85fc047\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "adc86ecbe0aff82859a5f2f215d8199b77409413", "tree": "aa900b3570f13f346bb6117335a882d79e98f666", "parents": [ "595833773c4de78f4e2d53217f704b453625ab5a" ], "author": { "name": "Saivardhan Thatikonda", "email": "saivardhan.thatikonda@amd.com", "time": "Wed Sep 24 09:09:42 2025 +0000" }, "committer": { "name": "Saivardhan Thatikonda", "email": "saivardhan.thatikonda@amd.com", "time": "Mon Oct 06 06:28:45 2025 +0000" }, "message": "fix(versal2): correct SLCR base for timer interrupt\n\nTSP suspend/resume tests were failing because the timer interrupt did\nnot occur after registration, due to an incorrect SLCR (System Level\nControl Registers) base address mapping.\nUpdated the SLCR base address to align with the AMD Versal Gen 2\nregister mapping and configured the TTC (Triple Timer Counter) base\nto TTC0.\n\nChange-Id: I64e3bbed20e440a8fd6f26295ee72ef421392360\nSigned-off-by: Saivardhan Thatikonda \u003csaivardhan.thatikonda@amd.com\u003e\n" }, { "commit": "595833773c4de78f4e2d53217f704b453625ab5a", "tree": "b1046eeb5ecebb324455284ad9466f2a18c712df", "parents": [ "a26539f5a882d35ece2a238c28e02f6e29a7fe1e", "24b2cf7d07ba4cb55ac8a3d66eac6c42ffe3087d" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Oct 02 15:07:42 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 02 15:07:42 2025 +0000" }, "message": "Merge \"refactor(ffa-notification): deprecate per-vCPU notification test coverage\"" }, { "commit": "a26539f5a882d35ece2a238c28e02f6e29a7fe1e", "tree": "f630867caf5b73c8693ca9503b4c4549bc77f796", "parents": [ "84529f26a1c5b6729856a9f27ddba1ebdea1cd80", "cce10bd1c0ec3ac1573da7715da8abe94808fc54" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Sep 29 09:05:12 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 29 09:05:12 2025 +0000" }, "message": "Merge \"fix: incorrect expectation for FFA_ABORT interface in ffa_features\"" }, { "commit": "84529f26a1c5b6729856a9f27ddba1ebdea1cd80", "tree": "7e9b0f4b3da745f79e108e0c947de96ce504ad9f", "parents": [ "dcf9d6f994ef8b803fe6ea270a8c06634c97f8fc", "caca5cc7406eea453bcd93df1639ba2407ae80ef" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Sep 26 15:05:58 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 26 15:05:58 2025 +0000" }, "message": "Merge \"feat(mbedtls): update mbedtls to version 3.6.4\"" }, { "commit": "caca5cc7406eea453bcd93df1639ba2407ae80ef", "tree": "7e9b0f4b3da745f79e108e0c947de96ce504ad9f", "parents": [ "dcf9d6f994ef8b803fe6ea270a8c06634c97f8fc" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Jul 10 14:28:24 2025 -0500" }, "committer": { "name": "Slava Andrianov", "email": "slava.andrianov@arm.com", "time": "Fri Sep 26 09:27:48 2025 -0500" }, "message": "feat(mbedtls): update mbedtls to version 3.6.4\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I3ed56c27d7c67f5386d9c9a69b45b90a4a5f4b60\n" }, { "commit": "466f182aefcd2523f7a12b6315e23507b13c97a6", "tree": "8f43c4f3a54acad84b94c3b63ae4970b11f22cda", "parents": [ "ceec9a5f8ea70599d0190b2519764067708b7b9a" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Aug 29 01:14:01 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for get reset status EEMI API\n\nAdd a test for the get reset status EEMI API within the TF-A test\nframework. The test validates the functionality of the API to read the\ndevice reset state.\n\nChange-Id: I3f35e27eb25fc7d6bbb2b71b7c3e46db775420c8\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "ceec9a5f8ea70599d0190b2519764067708b7b9a", "tree": "cb4725f55c2623f6e6b52fc7f470c7d4336122c7", "parents": [ "0a30387ca351f1603f3be15fa134ba60cda5ec84" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Thu Aug 28 22:08:46 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for force powerdown EEMI API\n\nAdd tests for the EEMI APIs that handle force power down and request\nwakeup within the TF-A test framework. The force power down API is\nused to terminate an unresponsive subsystem and automatically release\nits resources. The request wakeup API is used to power up a CPU node\nwithin the same PU or to power up another PU.\n\nChange-Id: I4fa6da87a3044c52834ab34621141cce5e136948\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "0a30387ca351f1603f3be15fa134ba60cda5ec84", "tree": "c4ffb9c066f389ebe5a589ad1168fc4a0c3ae89c", "parents": [ "2623513dbbbaee21ac309fb9f14eba748806fd47" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Wed Aug 27 04:15:25 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for query data EEMI API\n\nAdd a test for the query_data EEMI API within the TF-A test framework.\nThe test validates the functionality of the API for querying platform\nresource information.\n\nNote: This initial test focuses on validating the API interface and\ndoes not cover all query IDs\n\nChange-Id: I8488d08c3682613fcfc796acee6e76e384bbc39e\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "2623513dbbbaee21ac309fb9f14eba748806fd47", "tree": "ea9ae57b314a55cbf31e4cc68bbfea6b72168d47", "parents": [ "7fad289c38edda310b73a1072b4ffab2460385de" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Tue Aug 26 00:23:47 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for self suspend EEMI API\n\nAdd tests for setting wakeup source and self-suspend EEMI APIs.\nThe purpose of these tests is to validate the setting up of wake up\nsource and for a cpu to declare that it is about to suspend itself.\n\nChange-Id: I93374924703e03663b0d038a2aa79298e1cdb6f6\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "7fad289c38edda310b73a1072b4ffab2460385de", "tree": "57fd7d079cd6684679cf6ddc3663dbaee3760025", "parents": [ "952291944c14a2837610a3f2ba4b167bbdf64b90" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 23:51:41 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:42 2025 -0700" }, "message": "feat(amd): add test for pll EEMI APIs\n\nAdd test for pll EEMI APIs within the TF-A test\nframework. The purpose of this test is to validate\nfunctionality and reliability of various pll operations\n\nTest cover the following EEMI APIs:\n- xpm_pll_set_parameter\n- xpm_pll_get_parameter\n- xpm_pll_get_mode\n- xpm_pll_set_mode\n\nChange-Id: I1a2c88edc247dd4783ed52bc7e731b1d18b139e9\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "952291944c14a2837610a3f2ba4b167bbdf64b90", "tree": "1a17c36d70a12d92b64ff01e7b9ac4c4d58558b5", "parents": [ "0559174098d9d200f7aeafab5ada401a71b9d292" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 23:29:29 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:41 2025 -0700" }, "message": "feat(amd): add test for system shutdown EEMI API\n\nAdd test for xpm_system_shutdown EEMI API within the TF-A test\nframework. The purpose of this test is for a subsystem to\nshutdown self or restart self, Ps or system.\n\nNote: Only the subsystem restart scenario is executed in this test.\nPerforming a system shutdown would prevent the execution of\nany subsequent tests.\n\nChange-Id: Iaf8a7cad96ad6b6137187214c902434f90a78802\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "0559174098d9d200f7aeafab5ada401a71b9d292", "tree": "ddd8987d30526a2c8801f1f253930d5a575ddc5c", "parents": [ "db5542aaeb6c7c4f04346a4f51aec205a3595261" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 22:56:05 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:41 2025 -0700" }, "message": "feat(amd): add test for operating characteristics EEMI API\n\nAdd test for the get_op_characteristics API within the TF-A test\nframework. The purpose of this test is to request the power\nmanagement controller to return information about an operating\ncharacteristic of a component.\n\nChange-Id: I3b8346a82742c1b59dacc724c29235e4dbd6e753\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "db5542aaeb6c7c4f04346a4f51aec205a3595261", "tree": "3d0330d61d98ec5748703cd68338676b05260792", "parents": [ "6b1f473108203a65977d503c5a743e3bb1ebc988" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 22:24:47 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:41 2025 -0700" }, "message": "feat(amd): add test for TF-A register sgi API\n\nAdds a test to verify the tf_a_register_sgi() API, which registers\nthe IPI interrupt with the system.\n\nChange-Id: I3be28dc6c4ddec274cb64c8148fe0b61a1ab7b34\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "6b1f473108203a65977d503c5a743e3bb1ebc988", "tree": "7387741b6c9d23c4843450f5b05c23174936d820", "parents": [ "4cb875e37ac1a0423d3e772dbe266f9415e249bf" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 22:12:44 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:41 2025 -0700" }, "message": "feat(amd): add test for TF-A feature check API\n\nAdd test for the tf_a_feature_check API within the TF-A test\nframework. The purpose of this test is retrieve the supported\nAPI Version.\n\nChange-Id: I3d03661aec29814132d2635e7187442fb52af067\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "4cb875e37ac1a0423d3e772dbe266f9415e249bf", "tree": "c934b5b295eec8d21ab33b46591e76584ba949b4", "parents": [ "5c80b54add25bfa575c64b20f63a225c65dc90cd" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 21:51:55 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for trustzone version API\n\nAdds a test to verify the get_trustzone_version() API, which retrieves\nthe current TrustZone version from the firmware.\n\nChange-Id: I92876df6ccf970b5474eb86f48f97af9168704bb\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "5c80b54add25bfa575c64b20f63a225c65dc90cd", "tree": "7356fae8000f1953f504377e4d6606cc5b35ee6f", "parents": [ "453f76f08a6ed1a176d669ef5805531e1318c51e" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 21:31:17 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for init finalize EEMI API\n\nAdds a test to verify the init_finalize EEMI API, which notifies the\npower management controller that power management initialization is\ncomplete.\n\nChange-Id: I84a36b3cd0cadb0c462fdad2d1fd18b1821dedbd\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "453f76f08a6ed1a176d669ef5805531e1318c51e", "tree": "a3ac828b95b98efd1420ad2e8abea01dc2c2b32c", "parents": [ "d514d2bbc464cf128cb7487f6a4df0c8d341db55" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 06:50:50 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for pin EEMI APIs\n\nAdd test for the pin-related EEMI APIs within the TF-A test\nframework. The purpose of these tests is to validate the\nfunctionality and reliability of various pin operations.\n\nTest cover the following EEMI APIs:\n- xpm_pinctrl_request\n- xpm_pinctrl_release\n- xpm_pinctrl_set_function\n- xpm_pinctrl_get_function\n- xpm_pinctrl_set_parameter\n- xpm_pinctrl_get_parameter\n\nNote: This initial test does not cover all the pin ids, as the\npurpose of the test is to validate the pin EEMI APIs interface.\n\nChange-Id: I50142ee110e5cb7427ffaeae7f413aa0e6662006\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "d514d2bbc464cf128cb7487f6a4df0c8d341db55", "tree": "da6b66fc10f0505c0acf4f127f3d6dff9237e6ba", "parents": [ "9743f7d31c0d86290c711f0d439e5b333881cad3" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 06:25:32 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for clock EEMI APIs\n\nAdd test for the clock-related EEMI APIs within the TF-A test\nframework. The purpose of these tests is to validate the\nfunctionality and reliability of various clock operations.\n\nTest cover the following EEMI APIs:\n- xpm_clock_get_status\n- xpm_clock_enable\n- xpm_clock_disable\n- xpm_clock_set_parent\n- xpm_clock_get_parent\n- xpm_clock_set_divider\n- xpm_clock_get_divider\n\nNote: This initial test does not cover all the clock ids, as the\npurpose of the test is to validate the clock EEMI APIs interface.\nThe HW design must have QSPI nad GEM clocks enabled to pass this\ntest, otherwise the test will fail.\n\nChange-Id: Ie0d7dc844d4e58d1000a9fd6d669528103b097c7\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" }, { "commit": "9743f7d31c0d86290c711f0d439e5b333881cad3", "tree": "50c4bf05d441e646cdc351bb8f9696c1d732394f", "parents": [ "7faf8caa04992a21ce0691c1fb41f4586462aa93" ], "author": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Mon Aug 25 05:39:36 2025 -0700" }, "committer": { "name": "Madhav Bhatt", "email": "madhav.bhatt@amd.com", "time": "Fri Sep 26 02:55:40 2025 -0700" }, "message": "feat(amd): add test for node EEMI APIs\n\nAdd test for the node-related EEMI APIs within the TF-A test\nframework. The purpose of these tests is to validate the\nfunctionality and reliability of various node operations.\n\nTest cover the following EEMI API functionalities:\n- Retrieving node status\n- Setting node requirements\n- Setting maximum latency\n- Releasing an already released node\n- Requesting an already requested node\n\nNote: This initial test does not cover all the node ids, as the\npurpose of the test is to validate the node EEMI APIs interface.\nThe HW design must include USB and RTC device nodes in order to pass\nthis test, otherwise the test will fail.\n\nChange-Id: I1883abb20ae7e602530e504f3c39b20d02f57004\nSigned-off-by: Madhav Bhatt \u003cmadhav.bhatt@amd.com\u003e\n" } ], "next": "7faf8caa04992a21ce0691c1fb41f4586462aa93" }