)]}' { "log": [ { "commit": "6a010a32ac092ff392c34b80179b21e8036731f4", "tree": "dd6f31da6a94933db431d633e815002c92bbe08c", "parents": [ "2338ffcc695072c9ba1883b40473b1bb358a967f", "31f6f653bbc0eb6f2df84eb1fdb4574170bfba16" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Sep 15 12:07:44 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 15 12:07:44 2025 +0000" }, "message": "Merge changes from topic \"rmm-planes\"\n\n* changes:\n fix(rme): RMM is not taking PSTATE into account on PN entry/exit\n feat(rme): update tests to alp14\n feat(rme): uplift RSI_SYSREG_READ/WRITE tests to alp13\n" }, { "commit": "31f6f653bbc0eb6f2df84eb1fdb4574170bfba16", "tree": "0f58b61fa0d5a182ce062c876d70f8f385051b97", "parents": [ "049b469008f0901d9aa75444f10f1c5bc195cc78" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Aug 05 18:20:55 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Sep 12 17:58:28 2025 +0100" }, "message": "fix(rme): RMM is not taking PSTATE into account on PN entry/exit\n\nPlane 0 is notified, through RsiPlaneExit.pstate field of RMM PSTATE\nupon plane N exit. Also, plane 0 needs to provide RMM PSTATE value upon\ncalling RsiPlaneEnter through RsiPlaneEnter.pstate value.\n\nThis patch implements that behavior on the existing tests for planes\nas it was not implemented before.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I45af6c5863af2d2b7cc92005e16b80b895639f07\n" }, { "commit": "049b469008f0901d9aa75444f10f1c5bc195cc78", "tree": "e564191843668b2c2f96f9fb71b31885884af317", "parents": [ "4a9ffd52277103082ea78d7873e5f5732ed6fdcc" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Jun 02 20:01:02 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Wed Sep 10 13:19:20 2025 +0100" }, "message": "feat(rme): update tests to alp14\n\nRMI_RTT_AUX_{MAP, UNMAP}_UNPROTECTED have been modified on alp14.\nThis patch updates the RME tests to align with the new spec.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Icefb26de4fb66b1199a19d99496fa800f6abc2bc\n" }, { "commit": "4a9ffd52277103082ea78d7873e5f5732ed6fdcc", "tree": "7465ab700d8557cd0027ccbfce37a9637ed1bcf8", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu May 22 14:45:48 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Wed Sep 10 13:18:57 2025 +0100" }, "message": "feat(rme): uplift RSI_SYSREG_READ/WRITE tests to alp13\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Ia06872776d06655e0c0ceb6a48fca0e5aefac0b8\n" }, { "commit": "794b0ac8cdb01aa8c5ad630d4592b3743f6782cd", "tree": "9d4bda7de5f2c1640670949c0aa8fb382bc31fee", "parents": [ "aa48358ef9270417897780230bdedb635cc4af56" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Jun 20 13:13:29 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:37:05 2025 +0100" }, "message": "refactor(gic): unify SGI exception data\n\nThe information we pass to exception handlers for SGIs, PPIs, and SPIs\ndoes not differer materially. Unify the handling to use the same types.\n\nSince SGIs are normal IRQs, we can put the last remaining function in\nirq.h to simplify a bit.\n\nChange-Id: I1cf6f8a2a832797a9ce54eeb025a94120f115cf6\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "5f2468444daafa55f72a976c856d7f941a83ca51", "tree": "89d59590ff79f1bb8ab1b7924c47611cb1fbd245", "parents": [ "44de1232dca506a997adef7eae08b2570892262b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 16 11:42:30 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:37:04 2025 +0100" }, "message": "refactor(gic): add a is_feat_gic_supported() standard helper\n\nFEAT_GIC is a CPU feature like any other, add an arch_features.h helper\nfor it.\n\nChange-Id: I762b6333907f5f3dd3352544c1f2fb211a794b3e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "9b1afa7fdeaa7a57900c3aa606626a9c9bf9e405", "tree": "b63bf8e845ab5ff2bc70f711e4ef19b012ccca01", "parents": [ "e0b75ac177b9b3e7d703948387f429a665615c23" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 15 10:58:13 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 29 11:24:36 2025 -0500" }, "message": "feat(mpam): test FEAT_MPAM_PE_BW_CTRL register access\n\nThis patch introduces FEAT_MPAM_PE_BW_CTRL testing to cpu feats.\nWe check the presence of registers MPAMBW2_EL2, MPAMBW1_EL1\nand MPAMBWIDR_EL1 to verify FEAT_MPAM_PE_BW_CTRL\nis supported.\n\nChange-Id: I5f89402e8aa0ce3320f3e120f4c0c9dbed6f8c5f\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "dc23fcdec28d9c315c741710aba76c2145b73e91", "tree": "e54af256a0e4ef90b75f627ac6fe2217d6c1bb0b", "parents": [ "1bc61da619b0b375459ae221bd13bb25dcbf0bc2" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Sat Apr 05 14:26:13 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Aug 11 16:22:35 2025 +0000" }, "message": "feat(realm): assign MECID when creating realms\n\nThis change allows TFTF to assign a MECID to every realm that is\ncreated by passing an extra parameter to the Realm creation helpers.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I89bf08011eb005d949a195b406b073955f23f5ad\n" }, { "commit": "73005a60253c98274a4a1104af0bf75ccca4d205", "tree": "4b377917909b3aeada9b6a23598112b2b63fd145", "parents": [ "b0833d26dacc0fef45e4d695f9e7028a8d20825e" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 10:37:15 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Jul 09 09:08:51 2025 +0000" }, "message": "refactor(lib/pcie): rename macro CHECK_DA_SUPPORT_IN_RMI\n\nRename macro CHECK_DA_SUPPORT_IN_RMI to SKIP_DA_TEST_IF_PREREQS_NOT_MET\nand move it to host_da_helper.h\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ie955e1dcb2edefa0f41edfc36b4b2587cb465a29\n" }, { "commit": "b0833d26dacc0fef45e4d695f9e7028a8d20825e", "tree": "f0902ea53de0d53d4ff4fb3464ea78910ee0ef61", "parents": [ "bbb1305abc89d5b88a4cefe374e05052f27d165c" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jun 26 11:05:51 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:39 2025 +0100" }, "message": "feat(lib/pcie): init pcie device capabilities\n\nAdd additional fields in pcie_dev structure that will be later\nused by DA testcases.\n\nFind and initialize devices extended capabilities.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I32042393dc023d8ac948aa9f4ea921de22ec0b98\n" }, { "commit": "bbb1305abc89d5b88a4cefe374e05052f27d165c", "tree": "914c12b61f6f91da1982b906aa3dd180b911583c", "parents": [ "503b89a6b2d6ecd039401bd7f6f08f0d3cbb69a6" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 24 14:00:06 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:39 2025 +0100" }, "message": "feat(lib/pcie): add dvsec helpers\n\nAdd DVSEC RME DA support and helpers based on RME System\nArchitecture [1].\n\n[1] https://developer.arm.com/documentation/den0129/latest\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I29c2dc3c94fa295c9948f63f57f88e2763326291\n" }, { "commit": "503b89a6b2d6ecd039401bd7f6f08f0d3cbb69a6", "tree": "bf4b3f02eabecec15b63e2c5247eb6085b7c5ce8", "parents": [ "20c2d74e687556c462b49eb1f8a5e3afc21698cb" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jun 19 10:34:11 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:36 2025 +0100" }, "message": "fix(lib/pcie): import pcie enumeration helpers from rmm-acs\n\nImport PCIe enumeration helpers from rmm-acs[1] at tag v1.0_REL0_12.24.\n\nThis patch adds the missing device enumeration logic added as part of\nthe initial commit.\n\nThis change is verified with FVP default PCI topology. The helper\npcie_init() might need some enhancements for other platforms with\ndifferent PCI topology.\n\n[1] https://github.com/ARM-software/cca-rmm-acs\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I46724c458fe0071272fc7bca73d51e27181bb1b4\n" }, { "commit": "51f0333e24e6c4aff44ace871c6042b507476b5e", "tree": "4e7a4c0d34ab7cb3c0039bbd3b59431f646c531c", "parents": [ "cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jun 27 13:47:23 2025 +0000" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jun 27 13:57:23 2025 +0000" }, "message": "revert: replace in-tree Event Log Lib w/ submodule\n\nThis reverts commit cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849.\n\nReason for revert: Causing CI failures\n\nChange-Id: Iad32fb9ba1d32044ef647f01e3091e9b0ee0d9e2\n" }, { "commit": "cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849", "tree": "8be9469773b3f15614ee27ae9539cc29f8692c3c", "parents": [ "68ecce15bcd5db2449700d122f4e8f32cce91ae9" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu May 22 11:08:46 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 24 15:58:15 2025 +0000" }, "message": "refactor: replace in-tree Event Log Lib w/ submodule\n\nThe Event Log Library has been relocated to a separate repository and is\nnow integrated as a submodule, eliminating the need for in-tree files\nand reducing maintenance efforts for TFTF.\n\nChange-Id: I29694f8b3b08bb1d57dd685f6e42dc9f69d241bb\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "68ecce15bcd5db2449700d122f4e8f32cce91ae9", "tree": "4e7a4c0d34ab7cb3c0039bbd3b59431f646c531c", "parents": [ "550d5104ffe85f2f6994ef04a7172627cd76770e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon May 12 12:38:24 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 24 15:58:13 2025 +0000" }, "message": "feat(libtl): integrate Transfer List Library as submodule\n\nReplaces in-tree transfer_list implementation with LibTL submodule.\nRemoves legacy source and headers, updates includes and makefiles\nto use the standalone library. Adds architecture-specific inttypes\nheaders for compatibility.\n\nChange-Id: Iff8272a6417983b9fb8e7f6bde6db44c2a6020f5\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "1b16dc85e01ac96b02a384a307925005a471b2e2", "tree": "56be81714e31b82397012a6203f28a17bbb203d4", "parents": [ "718fd7902c015a64b49b12dcb6005d1aa50fd72e" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Jan 14 11:40:18 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jun 12 23:30:01 2025 +0100" }, "message": "feat(rme): add dev mem map/unmap tests\n\n- Add tests for RMI_DEV_MEM_MAP and\nRMI_DEV_MEM_UNMAP commands as per RMM Specification 1.1-alp12.\n- Add RNDR and RNDRRS registers\u0027 definitions.\n- Redefine RNDR and RNDRRS read functions as:\nDEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)\nDEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS)\n\nChange-Id: Ieecc41dd6d3011bb63101bc38d527a8f57e0ef4a\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "718fd7902c015a64b49b12dcb6005d1aa50fd72e", "tree": "6be817fbd9b1073bdd876b527e31e06e45b8a782", "parents": [ "5032d7bc760128a07ace8c9d4d91f7c3e9011cda" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Nov 08 14:55:20 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jun 12 22:45:11 2025 +0100" }, "message": "feat(rme): add dev granules tests\n\nAdd tests for RMI_GRANULE_DELEGATE and\nRMI_GRANULE_UNDELEGATE commands using\ndevice granules.\nAdd plat_get_dev_region() function to\nretrieve platform PCIe memory region info.\n\nChange-Id: Ie59361dd28e11db348c30b033c156de044aa0ffc\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "5ab09e8174e1ec17d6b1c35483f268e0775a5b67", "tree": "3be81b31149a1c413293061bd39d41c94d2416e6", "parents": [ "060efe97ff6c31b7dbec96af9fde0b169db4183d", "089c9ad705c1f393d95dd911c76a6772af45d1fd" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "message": "Merge changes from topic \"hm/handoff-mb\"\n\n* changes:\n feat(handoff): add event log test\n feat(measured-boot): add measured boot drivers\n" }, { "commit": "089c9ad705c1f393d95dd911c76a6772af45d1fd", "tree": "1842ee9a2fabfe773b56c98a76bb7e831b26b5a0", "parents": [ "b674809e4d937d44f85ef53aa2bdbb9f74b569b2" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:54 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:37 2025 +0000" }, "message": "feat(handoff): add event log test\n\nAdds a new TFTF test to validate presence and correctness of the TPM\nevent log in the transfer list received from EL3. Uses event_log_dump to\nparse and output log data.\n\nChange-Id: I0b1f782429e4bfe3d1760fce52d40a9836dc27a2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "b674809e4d937d44f85ef53aa2bdbb9f74b569b2", "tree": "3192a0624448d4503cb3679f0d939cb7c169ac22", "parents": [ "19620adc7cbcae26cc432a28a9c3b0944957cf13" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:03 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:25 2025 +0000" }, "message": "feat(measured-boot): add measured boot drivers\n\nIntroduces core measured boot support, including TPM event log handling,\nhashing infrastructure, and event formatting per TCG spec. The driver is\nimported from the existing implementation in TF-A.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: Ib2e6a88c86f110f9a6907c3e6dbb0dc736486de9\n" }, { "commit": "060efe97ff6c31b7dbec96af9fde0b169db4183d", "tree": "bc0e18f218d5facba2ae30222dad21bc7f5f3bbd", "parents": [ "336f1c20beba190b912a83756ca91626b2860c14", "2230a5955d328b4a018e72163482690892f5ff59" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Apr 25 16:18:55 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 25 16:18:55 2025 +0200" }, "message": "Merge changes from topic \"fix_pmuv3p9_test\"\n\n* changes:\n feat(ras): add RAS system registers access test\n fix(smccc): availability test: add two features and fix TRNDR\n" }, { "commit": "43ad50d798007af9d607898597d30bf215d3aa05", "tree": "1d0620e5b07b525e656d82ea22e7aefedba7f6a7", "parents": [ "8993e8ec7c66a849dad48f7b57e866cc40de3191" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Mar 28 17:37:04 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Mar 28 17:47:36 2025 +0000" }, "message": "feat(rme): update FEAT_MPAM tests on Realms\n\nCurrently, to test that accessing a FEAT_MPAM register from a Realm\ncauses an undefined abort injected back to the Realm, we only test\nby accessing a single register.\n\nThis patches updates the test by trying to access all MPAM registers\nfrom the Realm to validate that an undefined abort is taken to the\nRealm for all the registers.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I16c88d467eb2a49342694536a1c7b6358416dc34\n" }, { "commit": "37e3f3e1d237b6e8289fbc0a090b2b4dd2d4b9ec", "tree": "43448a6e0d637e635d482b1abf2144f0d7dda046", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Mar 07 17:25:24 2025 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 15:04:03 2025 +0000" }, "message": "fix(smccc): availability test: add two features and fix TRNDR\n\nThe SMCCC_ARCH_FEATURE_AVAILABILITY test was not up-to-date and was\nmissing two features: FEAT_TWED and FEAT_PMUV3P9. Connect the SCR_EL3\nand MDCR_EL3 bits to their corresponding ID register fields, so that\nthey can be tested.\n\nAt the same time the FEAT_RNG_TRAP test was slightly off: the SMCCC spec\nsays it should report accessibility of the RNDR and RNDRRS registers, so\nwe should look at FEAT_RNG, not FEAT_RNG_TRAP when checking the TRNDR\nbit.\n\nThis fixes the tf-a-tests run on an FVP with ARMv9.4 enabled, which was\nreporting the following issues before:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\u003e Executing \u0027SMCCC_ARCH_FEATURE_AVAILABILITY test\u0027\n TEST COMPLETE Failed\nis_feat_rng_trap_present says feature is supported but SCR_TRNDR_BIT was\n\tnot set!\nSCR_EL3 still has values set: 0x20000000. Test needs to be updated\nMDCR_EL3 still has values set: 0x80. Test needs to be updated\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nChange-Id: I73a0d240b2cd1a16e1c64d3d66ee30e658c9c946\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "tree": "a0ec5b6bff32d2fa1294f33af597c0d54558306e", "parents": [ "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "c8f5a2ee90f2b376da910f08170af4c4dc7396ae" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "message": "Merge \"test: test the save restore logic for brbcr_el1\"" }, { "commit": "c8f5a2ee90f2b376da910f08170af4c4dc7396ae", "tree": "625509a3d6d8838e0c31c9e89fbf23ed9361d15f", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Tue Feb 04 15:22:01 2025 -0600" }, "committer": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Mar 06 16:55:05 2025 -0600" }, "message": "test: test the save restore logic for brbcr_el1\n\nThis patch tests the save/restore logic by enabling\nbranch recording at NS-EL2. Additionally this\npatch also tests the trap logic when FEAT_FGT is enabled\nand a Realm tries to access any FEAT_BRBE related registers.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I176ea6feaf01d42cfd6231dc65a9470da8d1e37c\n" }, { "commit": "90506fbda56864b578980bc2d433f2ba38207e61", "tree": "b77200b91f6f52038c3754cc14fc2896d407f149", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120", "b3d451c3bb4b3b6c6a03aaaa8e1a785c5a4ca0a5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Mar 06 21:39:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 06 21:39:06 2025 +0100" }, "message": "Merge \"fix: add xpaci instruction to exception report\"" }, { "commit": "992c62b427ad7fc425ec3c02e6c2f5e98e94d120", "tree": "1267fde5c9244b900105a5d2d073c4d938ef7e0d", "parents": [ "3e496b408634030405c5fa5fbcb8b8babcebfb30", "eb2dd23469c8a5f3624b60ce21fab8299785fe4e" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 05 20:46:05 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 05 20:46:05 2025 +0100" }, "message": "Merge changes from topic \"kc/stmm\"\n\n* changes:\n refactor: move StMM to cactus tertiary\n feat(hob): add boot-time prints for cactus-stmm HOB list\n refactor(cactus): map boot information regions\n feat(hob): add HOB definitions to TFTF\n feat(spm): add STMM cactus partition\n" }, { "commit": "b3d451c3bb4b3b6c6a03aaaa8e1a785c5a4ca0a5", "tree": "4f962c5a8e86e12e0bdd0526bbb59dda55efe9b7", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Feb 13 14:24:06 2025 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Mar 04 10:37:16 2025 -0600" }, "message": "fix: add xpaci instruction to exception report\n\nWhen reporting an exception with ENABLE_PAUTH\u003d\u003d1 calling xpaci\nbefore printing the ELR value will remove the PAC and make the\npointer readable.\n\nChange-Id: I45339dbb3396f403768ea3ee780d0c5010da44c4\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "716c8cc0951fb6a3e212d4bd9b79ea0b6f9bdf9b", "tree": "858cebc6186fb65cc28fc02883dec4a112534603", "parents": [ "42dd088203e40911c67106d46cfccde58d55e1b5" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Feb 25 18:22:45 2025 +0000" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Feb 26 11:33:37 2025 +0000" }, "message": "fix(lib/pcie): bdf macro\n\nThe existing PCIE_CREATE_BDF macro is a non standard way of deriving bdf\nvalue. This fix assigns 3 bits for function number, 5 bits for device\nnumber and 8 bits for bus. This bdf value is used as TDISP function id\nwhile passing it to DSM. Using a wrong bdf value results the TDISP\ncommand to fail.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I31301be4dfc9bd2409da73e54715f73079a921cb\n" }, { "commit": "8808a945590fbc4138c0961717da75ddc383ede0", "tree": "992e6e95734b14bddb4dddc924c19122fccc6f69", "parents": [ "8ac4dd8ce81ba17121c62b4d39925ae6b62d7998" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Jan 07 15:45:39 2025 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 23:05:15 2025 -0600" }, "message": "feat(hob): add boot-time prints for cactus-stmm HOB list\n\nAt boot time, print HOB headers and contents.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ic634f045cacdbc8e318836eba85982a93f55fc0f\n" }, { "commit": "bde3eab2e68bc0059b5ccfc83a13759287eb9cf4", "tree": "90acb838f69c8c620e7790409df205077a8fe65b", "parents": [ "e8a17a905ca1c20acb1b9248ac725ab847bddc42" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Dec 09 14:04:43 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 13:51:36 2025 -0600" }, "message": "feat(hob): add HOB definitions to TFTF\n\nAdd necessary HOB structure definitions and HOB library to TFTF.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I1a81cd99df52436a077a71030244ca642122497a\n" }, { "commit": "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "tree": "010803c4d3fb8186d23cfd2f54f923c8271b45cd", "parents": [ "23ec8506918aff276b21b9543831d4825855906d", "82cd82e9868b1f381a5c8d84195657e1583cfca1" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "message": "Merge \"feat(rme): add tests for FEAT_MPAM on Realms\"" }, { "commit": "82cd82e9868b1f381a5c8d84195657e1583cfca1", "tree": "c7be244d493e784e55df370f501d8c3ba9275523", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jan 17 17:37:42 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Feb 04 15:01:14 2025 +0000" }, "message": "feat(rme): add tests for FEAT_MPAM on Realms\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6e138cbf121793bdaaa3a44824c0dbff74daced1\n" }, { "commit": "c398c8f7248e9aec29bbc41c94e41005d539863c", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jan 16 14:35:48 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Feb 04 11:38:28 2025 +0000" }, "message": "fix(realm): fix realm PMU tests\n\n- FEATURE_PMU_NUM_CTRS field in feature_flag was used\nto pass number of PMU event counters in realm creation.\nThe width of this field was set to 4, which was not\nenough to pass numbers \u003e 15 and was causing PMU tests\nfailures in FVP configuration with more than 15 event\ncounters implemented.\n- This patch removes all FEATURE_XXX macros for setting\nfeature_flag and replaces them with the corresponding\nRMI_FEATURE_REGISTER_0_XXX to match feature register 0.\n- In host_set_pmu_state() function was setting PMSELR_EL0\nto incorrect value 0 instead of 31 to select PMU cycle\ncounter for configurations with no event counters implemented.\n- Test host_realm_pmuv3_mul_rec() was running incorrectly\nwith number of event counters set to 0 or 31.\n- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0\ncan be constrained unpredictable depending on the\nvalue of PMSELR_EL0.SEL and number of accessible event\ncounters. See corresponding TF-RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573\nThis patch fixes host_set_pmu_state() and\nhost_check_pmu_state() functions to avoid unpredictable access\nto these registers.\nThis patch makes Realm PMU tests pass for all possible FVP\nconfigurations clusterN.pmu-num_counters\u003d[0...31].\n\nChange-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "414346805fa6589643780f6f9ce181facf2e1271", "tree": "69b825442caff18f8b25d6eee80140c80832d176", "parents": [ "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Dec 05 14:57:48 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 14:53:41 2025 +0000" }, "message": "test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n\ntest for RSI_PLANE_REG_READ/WRITE command\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I92e0aeef48c9b2abe26e5d3b2ea62669a22d4f8b\n" }, { "commit": "a0736c3dbf83f3c00ca98c83534070be259fb822", "tree": "4ab625c28b93f9fe02b4072720ab05a342175b26", "parents": [ "69cae79515b85f13a3ee957474231e51e879c4d8" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 09:34:35 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:12 2025 +0000" }, "message": "test(realm): handle permission fault for planes\n\nAdd support for handling permission fault in planes.\nSet s2ap in RTTs.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I590fc5a1c43357b117fa5cb76e8c699c4c7eebad\n" }, { "commit": "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "tree": "05125c5f936c21bd2d9cc5915bf9544333182bd9", "parents": [ "079c37c7aaf219182d7061427e22c65aaa416b37", "ff2f1150099940a2767381df1701c9007eec8e68" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "message": "Merge changes from topic \"qemu_tests\"\n\n* changes:\n fix(test): compile error in test_irq_spurious_gicv2.c\n feat(timer): support PPI timer interrupts\n" }, { "commit": "3e9115dc182c6240f9289912b6f528853b510e10", "tree": "bb75b4c42e4b096554dacad9bc3b399284f04097", "parents": [ "4686bbfe1f0122f07aa65f2d9c11fca81557ec54", "5abab7674959cb2fa3211e5199ac3115e72e86dc" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jan 13 14:18:16 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 13 14:18:16 2025 +0100" }, "message": "Merge changes I62946a18,Ida808b9d,Ic71af8d0,I505a4a05\n\n* changes:\n test(realm): add support for RSI Planes ABI\n test(realm): add AUX RTT support for planes\n test(realm): allocate memory for multiple planes\n test(realm): add initial support for planes\n" }, { "commit": "5abab7674959cb2fa3211e5199ac3115e72e86dc", "tree": "86f2a0e558571dc8e5f616e31d1564f8fbf11d5a", "parents": [ "8f5dae9067e545618830abda9fc5f143c58e7c9f" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 04:57:53 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 10 16:39:05 2025 +0000" }, "message": "test(realm): add support for RSI Planes ABI\n\nAdd Planes RSI support.\nAdd helpers to setup initialize and enter planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I62946a185c47fe77a04f42751d0b0a467d41ceee\n" }, { "commit": "b24cc1347491fd4ac89212970eba80f3fae5438f", "tree": "02bf7741ffc9dad822742b79fc90caa9839b9a7f", "parents": [ "7b7ca22f1b54632558663f5816d103105ce3aaec" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 28 10:35:35 2024 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "fix(brbe): report BRBE support with later revisions\n\nThere is BRBEv1p1 now, but the accessor reports the BRBE is not\nsupported altogether when that is present. The result is that the test\nis skipped. Fix the condition to return support with newer revisions\ntoo.\n\nChange-Id: Iab51b4016934d4b9eef125a6c4010ea419c99b81\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "7b7ca22f1b54632558663f5816d103105ce3aaec", "tree": "e3a9111c51ba449327eeeecbb638f03b5dab3cc6", "parents": [ "566f07da79dc559c405e79327be47740b7a66686" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 13:33:18 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "test(SMCCC): test SMCCC_ARCH_FEATURE_AVAILABILITY\n\nThis test calls the function with each valid argument and checks that\nevery bit is set if its relevant feature is present in the system. It\nalso fails the test if any set bit in the return value has not been\nchecked. This should serve as a reminder to update this test for every\nnew feature that is implemented.\n\nOnly feature that tfa supports are tested with the expectation that new\nones will be added in the future.\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I801326a49810bb76bfc3b9d06780d416dcc32a40\n" }, { "commit": "4e282424143dbd73cd0248d470d03cccb9005f42", "tree": "b5da9ecc48fe84d374c9e04de6a0d3e2c7f8aa0d", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 14:34:13 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:16 2025 +0000" }, "message": "feat: add register definitions needed for SMCCC_ARCH_FEATURE_AVAILABILITY\n\nAlso slightly optimised some redundant feature functions\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I6dcc11060a2f3697a8aa41443e9cfc665b2b7c74\n" }, { "commit": "d1a7f4d2bd6b4867a71366b58b00759724ef99d1", "tree": "7439900358c0026fe7c781e725e6ba0b1c3fd37b", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Tue Nov 26 12:50:47 2024 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 19 14:51:47 2024 +0000" }, "message": "feat: add tests to check SCTLR2, THE and D128 sysregs\n\nThis patch adds test cases for verifying that the system registers of\nFEAT_SCTLR2, FEAT_THE and FEAT_D128 (FEAT_SYSREG128) are working\ncorrectly by performing a series of reads and writes to the registers.\n\nChange-Id: I5c102daa358a7ec5d1801395bc875e9850e83939\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "dc18ace1a36a4f684f1e4c7ef193a34c563d75c1", "tree": "49bb31a7dc6df8d5b09217a4e38f5e493ffa87d8", "parents": [ "a07460f4520b05d6f01624a857e6b6c0a6a41235", "1ab21e5e0f05680e5a30093fe6a7eff99fdcb150" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 12 22:42:25 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Dec 12 22:42:25 2024 +0100" }, "message": "Merge \"feat(fpmr): test FPMR register access\"" }, { "commit": "5929bfe75a40577efa77cf23a2fc4057ced92e7e", "tree": "054341aebc883a57faab006f4d700d596c323203", "parents": [ "67a3ffba147f4a5d996fa5e307fd59389925434e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:28:00 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 18:10:28 2024 +0000" }, "message": "refactor(realm): define PCIe helpers\n\nThis patch refactors the existing PCIe and DOE\nhelpers to define generic helpers to make them\nreusable across more tests.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I56a9f5c59715c7916f3f737ed6d3af94b0e3679f\n" }, { "commit": "2c2810f79e57e78d77899084b5439cbdd1aaa464", "tree": "5d5644927acc2f4a212ba18558c7ed57f3d1e07c", "parents": [ "ea43ac0daef913576cf214454cf81482d8cf109a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 15 17:11:24 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 05:21:39 2024 +0200" }, "message": "fix(realm): make PCIe tests default for testing\n\nThis patch moves the PCIe DOE test to the default realm world\ntestsuite.\n\nAlso fixes some build issues and hardens the PCIe functions.\n\nNote that FVP_Base_RevC model needs to have the following\noptions enabled for the PCIe tests to work :\n\n -C pci.pcie_rc.ahci0.endpoint.doe_supported\u003d1\n -C pci.pcie_rc.ahci0.endpoint.ide_supported\u003d1\n\n\nChange-Id: Icfd6b68799b0bacb44299c6a3cf99a3c425f833d\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "1ab21e5e0f05680e5a30093fe6a7eff99fdcb150", "tree": "17c76bf9488a15d760977c0631fd35ef733554a1", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Nov 12 10:52:08 2024 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Nov 19 15:16:35 2024 -0600" }, "message": "feat(fpmr): test FPMR register access\n\nChange-Id: I326690564d01596fb4f4b449f4f314699ccfe3c4\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "c79338af9a3e9cb24b90afd79491c85b7ef11d72", "tree": "bcf79e2a50a9e49bdfbae09e71fd4176c717bc7d", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Oct 28 18:48:25 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Tue Nov 19 09:06:55 2024 -0600" }, "message": "feat(smc): support SMC calls with no ret vals in x8\n\nThe current implementation of the SMC library assumes that x8\ncontains the address of an smc_ret_values structure. Although\nthis can be convenient, it prevents from using registers x8-x17\nas arguments, since it assumes there is an address in x8.\n\nThis patch implements an alternative API for SMC calls, allowing\nthe use of registers x1-x17 as input arguments and the use of\nregisters x0-x17 as output arguments without assuming a pointer\nin x8.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I0016116b8d2ee4ef5aac9473f31e38434cda4943\n" }, { "commit": "16059ac52d8f221c921e0766bc2b714ee52e06ed", "tree": "13ad5ef729e1eda7fc70c89969dd774319806f25", "parents": [ "b2b581650c4af293b734a45430ba49bccd96d60d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 11:15:22 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 13:19:55 2024 +0200" }, "message": "fix: add sysreg define for ID_AA64MMFR3_EL1\n\nThe patch 7c78f7b4a removed the definition for ID_AA64MMFR3_EL1 sysreg.\nThis define is needed for older GCC (like GCC 11) to compile TFTF\nsuccessfully. This patch restores the define.\n\nChange-Id: I18f8e00830c8e72807b6f1613e9d9864f12669ba\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "46d0228e2a1a17c57be8f5011f183ea28e6ba518", "tree": "ce322be37116651bf3ab1d681632c176f8105233", "parents": [ "7c78f7b4a74e58512ff6998f7a5438520e58c343" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Nov 18 16:58:37 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Nov 19 11:22:08 2024 +0100" }, "message": "fix(serror): use custom argument for incrementing elr_elx\n\nAdd a custom argument to increment the elr_elx after handling SError.\nIn some cases, to prevent re-triggering the instruction, ELR needs\nto be incremented by 4. In other cases, it may not be necessary.\n\nThis argument is passed to the handler, which then decides whether\nto increment elr_elx by setting the passed argument accordingly after\nhandling the SError.\n\nChange-Id: I404f3c5e24f894502a8d00c73649be0b2dd540fa\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "7c78f7b4a74e58512ff6998f7a5438520e58c343", "tree": "ea7bd3a6363d1bf5686e5cfbd2a92cabec7a3df6", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Oct 25 11:44:32 2024 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Nov 19 10:10:16 2024 +0000" }, "message": "feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n\nWhen FEAT_DoubleFault2 is supported, TF-RMM must take into\naccount bit SCTLR2_EL1.EASE in order to decide whether to inject\na SEA into the sync exception vector or into the serror one.\n\nThe test on this patch verifies that TF-RMM injects the SEA\nto the right vector depending on SCTLR2.EASE bit.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c976fecb04d123e3efb96c5973b1466e241097f\n" }, { "commit": "5a44078f017c581c9def5cfd697f0579fc6ff89c", "tree": "4d63ddf377e00735bcbb1d5fdacc1885f8401377", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Tue Jun 25 12:36:20 2024 +0200" }, "committer": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Fri Nov 15 09:06:21 2024 +0100" }, "message": "feat(timer): support PPI timer interrupts\n\nAdd support for timers that use a PPI as timer interrupt. A new\nfunction, tftf_initialise_timer_secondary_core(), is added to initialize\nthe PPI on the secondary CPUs from tftf_warm_boot_main().\n\nChange-Id: Ia343ce10b0b51e72b9e520b1fab0ea7ba0a43f2c\nSigned-off-by: Jens Wiklander \u003cjens.wiklander@linaro.org\u003e\n" }, { "commit": "e42561dbcd9d66d4de22d1b2bf48e124872b815c", "tree": "eab01079c905b0f119a826ca02ecb8e65a642647", "parents": [ "73d5bbd188aa33ad7ef4c28acbddaf2d8b9433a7" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Nov 11 11:22:03 2024 +0100" }, "committer": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Nov 11 13:00:46 2024 +0100" }, "message": "fix: update definitions for sysregs on older toolchains\n\nThe patch 0db4a3cd added new sysreg access which older toolchains\ndo not support. This fix opts to use the renaming variant of the\nnecessary preprocessor macros for the registers used as part of\nthat patch, so that TFTF can compile with older toolchains.\n\nChange-Id: I1d4cdfc3f67a085af35a3b51477eda79e9e93db7\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "4b67210c4ae32e723fc5805f3b7e8c48fb8ec962", "tree": "b5d66c48a39a422a902364d694a41521c35de431", "parents": [ "0db4a3cdde090a94721a8a598cbbbf857f7cf47f" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Sep 23 13:06:15 2024 +0200" }, "committer": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Fri Nov 08 17:48:28 2024 +0100" }, "message": "feat(cm): add test to validate EL2 regs during context switch\n\nVerify that EL2 system registers are preserved when switching\nfrom Normal world to Secure world and vice versa. Do this by\nmodifying the live EL2 register state and dumping it to memory,\nthen performing an FF-A Cactus call and checking whether the\nstate matches the previously saved context.\n\nChange-Id: I0537b4d671c72c0a2fd29ac7e218bf69e1c66001\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "0db4a3cdde090a94721a8a598cbbbf857f7cf47f", "tree": "30581ed1d668fe4be2075f5ce034dedc1e3ee5e3", "parents": [ "86e5e5d500a839920edcf71783f31b7e4fc20c42" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Sep 23 12:52:15 2024 +0200" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 16:52:44 2024 +0000" }, "message": "feat(cm): add el2-ctx registers helper macros\n\nThis patch adds the necessary definitions for the registers\nand helpers that are used in the EL2 context switch test.\n\nChange-Id: Ie846f9341d600ae8fb7a46a9655a8f8ee62d84b0\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "86e5e5d500a839920edcf71783f31b7e4fc20c42", "tree": "c9b96514811730ade3be4cd5449254025502fb07", "parents": [ "af49307617a6861c13008371a1e5397b278bb4c7" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Aug 05 19:52:29 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 16:52:38 2024 +0000" }, "message": "feat(cm): add tests to validate EL1 regs during context switch\n\n* This patch adds a test to verify the integrity of the el1_context\n registers across world-switch.\n\n* It aims at testing the save and restore functionality provided\n by the EL3 context management library.\n\n* It validates the EL1 ctx register entries after interaction with\n TSP (S-EL1) software.\n\nChange-Id: Id435d9d7699231d66e9e7acdbb3459ec439d2aef\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "af49307617a6861c13008371a1e5397b278bb4c7", "tree": "8f8243c121303783723ef96c2994bb7a388c5947", "parents": [ "8e65838b7baaf9a0c57582aa7deee11d78012931" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Aug 12 17:26:10 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 11:29:43 2024 +0000" }, "message": "feat(cm): add el1-ctx register helper macros\n\nAdding EL1 context registers related helper macros\nnecessary to test EL1 context entries.\n\nChange-Id: Ifb0149ad78f951958990290b496e7c1b92c072ea\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "72b7ce11edd6042d5a3fe75bba83fb5e7f58ee08", "tree": "6fba961e72767d7a0c58b914acc24723190802a3", "parents": [ "a62262f047c9c48c65021f4e23be7b709e8c2811" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Nov 04 13:44:39 2024 +0000" }, "committer": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Wed Nov 06 21:46:35 2024 +0100" }, "message": "feat(ls64): add LS64_ACCDATA test\n\nFEAT_LS64_ACCDATA introduces the system register ACCDATA_EL1, its value\nreplacing the first four bytes of the data provided to an ST64BV0\ninstruction. As this system register would need context switching\nbetween non-secure and secure worlds, there is an SCR_EL3 bit to allow\ntrapping accesses from lower ELs into EL3.\n\nIntroduce a check to verify that accesses to this system register do not\ntrap into EL3, if the CPUID registers advertise this feature.\nBits[63:32] of ACCDATA_EL1 are described as RES0, so mask those bits\nwhen comparing the read-back values with the written one.\n\nChange-Id: Ia32bcf7187356c701470a1757708b3d554e88629\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "f2f1e27c93581b6a9770b8b70780bcd80b961b24", "tree": "e3f021e5f5f1af491df4544fc00fc1e433d9e6f8", "parents": [ "37a5034e1c96dffd897e7231d406fccb3131aa8d" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Sep 03 11:49:51 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Oct 24 11:19:43 2024 +0100" }, "message": "feat(tcr2): add asymmetric feature testing for FEAT_TCR2\n\nChange-Id: I07b27ff58ccf471ccc43643141e2dfe70083fd13\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "9601dc5343d4aee267a5adcebeb2495f395acc4d", "tree": "ba51882deb7e44d3b0832904d0ef0ca61b8c871b", "parents": [ "70de3ff58e06f66819e98a25a9167c6751f87330" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Wed Aug 28 17:27:18 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "feat: skip asymmetric tests when features not present\n\nThis patch skips asymmetric tests, when features are not present\nand will split them into separate tests.\n\nThe problem with the previous test structure was that you can\u0027t\ndistinguish between a trap to EL2 and an undef injection. This meant\nthat on some platforms, the tests would pass even without the\nasymmetric support patches. In these cases, it would be better if the\ntest was skipped, since there\u0027s no situation where it fails.\n\nFor example, if FEAT_SPE wasn\u0027t present on any cores, and the\nasymmetric support patches weren\u0027t applied, then the test would pass.\nThis is because the register accesses would trap to EL2.\n\nThis patch skips the test on every core that doesn\u0027t have the feature\nimplemented. It also splits the test into separate test functions.\nThis allows us to display a separate test result for each asymmetric\ntest. It also allows us to skip the whole test if the feature isn\u0027t\npresent on any cores, since in these cases the test would always pass.\n\nThe structure of the test is similar to\ntftf/tests/runtime_services/standard_service/psci/api_tests/cpu_suspend/test_suspend.c.\nThe run_asymmetric_test function takes a function as an argument, and\nruns it on all CPUs.\n\nThe whole test should only be skipped if the test was skipped on all\nCPUs. The test on each CPU can\u0027t return TEST_RESULT_SKIPPED, because\nthe whole test is skipped if any of the CPUs return\nTEST_RESULT_SKIPPED. Instead, to skip a test, the test returns\nTEST_RESULT_SUCCESS, then sets a flag in the test_skipped array. This\narray is checked at the end by the run_asymmetric_test function.\n\nChange-Id: I802431714de3eb8b059e8fc56f7e19fc94e3e8fb\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "5467cb50ac44eb4d3248c0cf70eaf1fd6a034c8b", "tree": "1e35ba50c44808b5b946e98fd32aa02c4723b7b3", "parents": [ "19cfac8b0cbbc1dfffc58f28a4cacb925eb4c8c9" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Oct 02 18:21:43 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 07:14:34 2024 +0200" }, "message": "fix(realm): cater for removal of SH from rtte\n\nThe RMM v1.0 REL specification removes the SH field from host_controlled\nparameters. Fix up TFTF for this change.\n\nChange-Id: Id032d4555da4b200bb9a355085b8a7f0709884fb\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "9f2de630d5d2472e8ec7348507e343738934940d", "tree": "4905c2ec19086fbdecde033abd1f2f766d98f692", "parents": [ "36ed009a073c64a422c769b46eede6538fa42667" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 11:48:22 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 13 18:20:18 2024 +0200" }, "message": "feat(doe): add PCIe DOE tests\n\nThis patch adds PCIe DOE tests for\n- DOE discovery protocol\n- SPDM get version\nTo build this test suite use \u0027TEST\u003dpcie-doe\u0027\noption.\n\nThe spdm.h is imported from https://github.com/DMTF/libspdm\nproject.\n\nChange-Id: I8db1048d01b4f8061d8a4ddccc198159ed61e6b7\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "9f0dc01f4d4f6f1800e86c4c6f1e8377e119a713", "tree": "119dc2ce7fa5fe4807fc535ea0dfc1275af2fedb", "parents": [ "31a6f6499c5e558a9ef13ff53922f031d18a48b9" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:22:06 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:22:06 2024 +0100" }, "message": "feat(pcie): add PCIe DOE library\n\nThis patch adds PCIe DOE library source files.\n\nChange-Id: Ic2ab11afa0438d74c53cb157a63caada7457d77e\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "e4f2eaa6f626646cfa3e439086966ac114540cbc", "tree": "ebb5c60c417e4393c160b78f1c31b780a3c48d2f", "parents": [ "eeac9d97edaf45041b7325f9aade1ad7bfeb6828" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Mon Aug 12 17:59:54 2024 +0100" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 12:07:48 2024 -0500" }, "message": "feat: introduce asymmetric feature testing for feat_spe\n\nChange-Id: Ide9bda1b5f1cabc63241f42b93a672d8e04b8119\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "8191621885dfc65789a19ef0eb590b8639ed87d1", "tree": "8fbbf09517a4e7de5976e8912a594be10cfb1f04", "parents": [ "0145ec3459750f35a6546b3f015906356b7dc6cd" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Aug 15 15:08:23 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 09:07:55 2024 -0500" }, "message": "feat: test if errata 2938996 and 2726228 workaround is applied\n\nThis patch confirms if access to trbe el1 register generates an undef\ninjection in affected cores. If a core is affected by errata 2938996/\n2726228 and it generates an undef injection on access to trbe el1 register then\nthe test passes. If it is an unaffected core then the test passes , but\nwhen undef injection doesn\u0027t happen in affected core, the test fails.\n\nChange-Id: I515a9aa4613c6d99ee73e579206089ebf89ffae8\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "6043eaf8e2aad4727f6e3f7199e88b59787d3ad4", "tree": "0bef58a1a1ac541c6d73fe59773d8f9701f87f93", "parents": [ "277925bbfc6bd1caf47f573dd17569b9a30d7844" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Mar 08 14:14:12 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:22:31 2024 +0200" }, "message": "feat(spm): probe SVL for SME related tests\n\nFor world switch SPM tests checking the SME context, probe the possible\nSVL values in streaming SVE and run tests with each possible SVL.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I5157fc896168f7ea2df131a86acdb1d1f1bb795e\n" }, { "commit": "2661ba526090e7217d8a334f6f7280c56296f37b", "tree": "116bda475946441b4c19c87ed211a85e0d8dd32a", "parents": [ "d0704f69f4824d6100faabd19522e0205c926e92" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Feb 19 18:50:53 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:21:27 2024 +0200" }, "message": "test(spm): check processor feature regs\n\nFor cactus secure partitions, check ID registers report:\n-FPU/Adv. SIMD supported.\n-SVE/SME not supported.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Iba3508d57a8bcb1f554adddef97c4c83f4118a03\n" }, { "commit": "d0704f69f4824d6100faabd19522e0205c926e92", "tree": "cbc56389b7c54fe0021fcfab729b9f5c48f9c5d2", "parents": [ "65442a9ca6fd1062f0eb34c4ac9f62f781dcf352", "c3cf2daed819a9d01feba31832544309c9da8d70" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Jul 29 18:54:59 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 29 18:54:59 2024 +0200" }, "message": "Merge \"feat(amu): test AMU counter restriction (RAZ)\"" }, { "commit": "65442a9ca6fd1062f0eb34c4ac9f62f781dcf352", "tree": "7c4a6528edfddbbcfa4513549244e6e759b16e19", "parents": [ "3d88db7691467351726d05b20d629b94c1fb1b59", "b47ccd0519d2b26fb89bd3434113a17b97e9cc05" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 24 20:04:49 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 24 20:04:49 2024 +0200" }, "message": "Merge \"test(handoff): fix register convention value on test_firmware_handoff()\"" }, { "commit": "3d88db7691467351726d05b20d629b94c1fb1b59", "tree": "10f847b91327aae17ae91a2d6a5342b0a1575e03", "parents": [ "b1ab5854ad384dd1e3abbe760a6b35d6cae9a0bc", "94963d4e739f3fb1accefddd4105cf9140989889" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 24 17:26:44 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 24 17:26:44 2024 +0200" }, "message": "Merge \"feat(fgt): add support for FEAT_FGT2 testing\"" }, { "commit": "cd6c94b20e7450e27254856a82008ca0595d84d1", "tree": "6a8146d2ef87f4c5a0f72f84b850e1577c57a4a4", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Feb 15 17:19:05 2022 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jul 23 14:06:14 2024 +0100" }, "message": "feat(ls64): add a test for 64byte loads/stores instructions\n\nThis patch adds a test to verify the 64 byte load and store\ninstructions introduced by FEAT_LS64.\nThe test primarily executes instructions:\n1. LD64B\n2. ST64B\nand ensures that the NS-EL2 has no dependency on EL3 while\nrunning them.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I7a4ca0ee4a2c18bf0de030c72e35eb218bc6364c\n" }, { "commit": "94963d4e739f3fb1accefddd4105cf9140989889", "tree": "904e5a3428384fae10f4cae54fd91589fc47da8c", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jun 13 17:19:56 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Mon Jul 22 16:21:01 2024 -0500" }, "message": "feat(fgt): add support for FEAT_FGT2 testing\n\nThis patch adds testcase that validates FEAT_FGT2 support\nby reading Fine-grained trap registers that are part of FEAT_FGT2.\nThese registers are only present when FEAT_FGT2 is implemented\n\nChange-Id: Ifc1106d12dbe03b956310d364600368d3f035491\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "b47ccd0519d2b26fb89bd3434113a17b97e9cc05", "tree": "81c6baf940af8d9cb028aad04265d872b3cd48ae", "parents": [ "994e6956079c58766cefac29aaa0f97af10cd73c" ], "author": { "name": "Levi Yun", "email": "yeoreum.yun@arm.com", "time": "Wed Jul 10 16:18:47 2024 +0100" }, "committer": { "name": "Levi Yun", "email": "yeoreum.yun@arm.com", "time": "Mon Jul 22 12:03:28 2024 +0100" }, "message": "test(handoff): fix register convention value on test_firmware_handoff()\n\nAccording to recently firmware handsoff spec [1]\u0027s \"Register usage at handoff\nboundary\", Transfer List\u0027s signature value was changed from 0x40_b10b\n(3 bytes) to 4a0f_b10b (4 bytes).\n\nAs updating of TL\u0027s signature, register value of x1/r1 should be:\n\nIn aarch32\u0027s r1 value should be\n R1[23:0]: set to the TL signature (4a0f_b10b -\u003e masked range value: 0f_b10b)\n R1[31:24]: version of the register convention \u003d\u003d 1\nand\nIn aarch64\u0027s x1 value should be\n X1[31:0]: set to the TL signature (4a0f_b10b)\n X1[39:32]: version of the register convention \u003d\u003d 1\n X1[63:40]: MBZ\n(See the [2] and [3]).\n\nTherefore, it requires to separate mask and shift value for register\nconvention version field when sets each r1/x1.\n\nCurrently, TRNASFER_LIST test runs only in aarch64.\nSo, change the assert value in test_firmware_handoff() as\naarch64\u0027s x1 value when transfer list deliver.\n\nLink: https://github.com/FirmwareHandoff/firmware_handoff [1]\nLink: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]\nLink: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]\n\nChange-Id: Ibc86963cc5abda3aae4cb8fe34533be250e3dd95\nSigned-off-by: Levi Yun \u003cyeoreum.yun@arm.com\u003e\n" }, { "commit": "2f2c959871723c303a833778271cd923910deaca", "tree": "a3b777765c3959ea183de411cbe73d18e45578b1", "parents": [ "b5103df4af352c9409fb0756579788d6c0732b87" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jun 06 16:34:28 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Jun 28 14:55:27 2024 -0500" }, "message": "feat(debugv8p9): test if EL3 has properly enabled FEAT_Debugv8p9\n\nWhen FEAT_Debugv8p9 is not enabled, access to MDSELR_EL1\ntraps to EL3. Access to FEAT_DEBUGV8P9 control registers\nmust be explicitly enabled in EL3,\n\nThis testcase uses this behavior to test if\nFEAT_Debugv8p9 is enabled or not.\n\nChange-Id: I2f9a0158e9f38eaffac2e27c40d44d3c520d508d\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "7efea19cd6c832ea8a595ef5dc057cca721ca237", "tree": "5f387e91703069d63085e874b0c7727b15d2be80", "parents": [ "6d833ef005af59119dbbc9794a3bbfc191eb4f60" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Sep 19 16:07:09 2023 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Jun 13 13:17:35 2024 +0100" }, "message": "feat(rmi): add support for FEAT_LPA2 to the Realm Extension tests\n\nThis patch adds support to the current Realm Extension tests to\nenable and use 52 bit address size with 4KB granularity when\nFEAT_LPA2 is present.\n\nIn addition, this patch also introduces changes to support passing the\nstarting RTT level and the FEAT_LPA2 enable flag during realm creation\nso they can be used later to implement tests for FEAT_LPA2 on RMI.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I0a930735a44772e5e76d6608c969759f27129917\n" }, { "commit": "c3cf2daed819a9d01feba31832544309c9da8d70", "tree": "d47120e316a97ea94409e1a61594ec6da1f5a71b", "parents": [ "caff038b3f0b261b1fcc14f7918a80fa515202c1" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Apr 01 13:57:19 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri May 10 13:40:04 2024 -0500" }, "message": "feat(amu): test AMU counter restriction (RAZ)\n\nWhen using AMU counters, there is risk of exposing information to\nlower exception levels. In order to prevent this, counters are\nrestricted, so they are read as zero (RAZ) at a lower EL. This\ntest verifies that counters are read as zero after forcing counting\nthrough instructions that trigger MPMM \"gear shifting\" (e.g.: by\nexecuting SVE instructions).\n\nNote: This test applies to TC2 only, as it is the only platform that\n supports MPMM currently.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ic32ba19fa489cf479947d4467ddb84e6abd1b454\n" }, { "commit": "21a30ed1ae35a8b32d23e96cdc143702a27bda90", "tree": "bd1d61a86ff59e96c33a98a036e542f43ce185df", "parents": [ "a8deec5c0b51719b1f268e4f106c3a095a387074" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Sat Jan 13 23:07:43 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Feb 14 12:51:31 2024 +0100" }, "message": "test(realm): test realm pauth state is preserved\n\nModify Pauth lib to work for multiple CPU\nTest if Realm pauth state is preserved for all RECs\non context switch to RMM/NS.\n\nChange-Id: Ibb393b415bab27066289b560be49e02d0c8f58ba\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "b027f5706308502152b5aade0ad509ba27370c42", "tree": "3a05dab054068d29e8b242f8f82daa4a864468e9", "parents": [ "fd35f0a4d6125bb1fa69a671a6d2d42628229609" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Jan 02 22:00:29 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Feb 08 12:14:31 2024 +0100" }, "message": "test(realm): add testcase for Synchronous external aborts\n\nAdd testcase to cause instruction or data abort in Realm by\naccessing addr with\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dEMPTY\n* HIPAS\u003dASSIGNED and RIPAS\u003dEMPTY\n* Unprotected IPA\n* Host injected SEA after Data abort\n\nChange-Id: I6be546c042b4983670fb7c27fca74649c68787be\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "e68494eb130e2c8021ca4af626a9cb1df8d67dbd", "tree": "894c262fc0aa78dcbe3b28cc6b731df068a404b6", "parents": [ "daa6c795847b78692f522fd96f783a6d419aaec2" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Nov 06 11:04:57 2023 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 06 10:45:44 2024 +0100" }, "message": "test(realm): add testcase for REC exit due to Data/Instr abort\n\nAdd testcase to cause instruction or data abort in Realm by\naccessing addr with\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dDESTROYED\n* HIPAS\u003dASSIGNED and RIPAS\u003dDESTROYED\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dRAM\nVerify rec exit due to abort\n\nChange-Id: Ic04c0ddaf1b18ec0cfd71c28753c4ed7298302da\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "0945e23153c06ed196756ac094c81ab8627d9a95", "tree": "7bc1e57bb77a4cf09cf18b75974e18e60711da53", "parents": [ "8f6b131f44bf5355d07b274f6a43490f968590b2", "16de81046dbffdfc19ca4a30524f170860eac178" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jan 31 08:48:35 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 31 08:48:35 2024 +0100" }, "message": "Merge \"test(fvp): Test trusted key certificate corruption\"" }, { "commit": "16de81046dbffdfc19ca4a30524f170860eac178", "tree": "d70655f6090cd2e8befdae3a8270682f19f551ba", "parents": [ "84ad6157a4e83834fa925b80534ca5414c368586" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Fri Aug 18 08:50:30 2023 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Mon Jan 29 13:10:08 2024 -0600" }, "message": "test(fvp): Test trusted key certificate corruption\n\nThis also includes a test framework for use with corrupting the\nroot of trust private key certificate in the boot FIP, found\nusing its UUID.\n\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\nChange-Id: I988c517637edcf6fdcaf271628eb650781c276f8\n" }, { "commit": "13887ac63d4186a851ae2a916c112cb6229c6e63", "tree": "e49867e623b38a26d977d84b2a21b1f382f523cf", "parents": [ "ea94738603d09be1399337f0976f89f951c35e6a" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jan 04 15:22:52 2024 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Jan 16 12:43:23 2024 -0600" }, "message": "feat(mpam): add MPAM system registers access test\n\nAdded a test which reads MPAM system registers to ensure that\nEL3 is giving permission to Non-secure EL2 to access these registers.\n\nChange-Id: Ie701a19c9682df6d6aeaec086954e275afff1843\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "e15bc803ed76eee496f95cba2df45aa292500090", "tree": "684b021e9625392ed31f006b559c1f103be4503c", "parents": [ "f0da2001c7779ca7bc23dce4bab9bd314cdcb0e6" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Dec 18 15:21:13 2023 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Dec 18 16:17:14 2023 +0000" }, "message": "feat(handoff): update register signature\n\nThe existing register signature was changed from 0x6ed0ff to account for\n0xff being a value that is regularly found in memory [1].\n\n[1] https://github.com/sjg20/firmware_handoff/commit/f70c184905607f6b1d074a5de9aa407a5d92344b\n\nChange-Id: Ib217f1b68df9e534fc61604c88eea4560ecb9dc2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "417edcad3eb332eca5d7ed70de51cac489a2dca4", "tree": "520dcd978d3d12003560fd56a66e1c0117521514", "parents": [ "bbf08c50aca569e517a52d2216c42e7244769a5e" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Sep 05 17:44:24 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Nov 30 16:27:24 2023 +0000" }, "message": "feat(smc): add SMCCCv1.3 sve hint bit support in tftf framework\n\nTFTF smc library uses SVE field in trap register to represent SVE\nhint flag.\n\nTestcase has to explicitly set this bit using the helper routine\ntftf_smc_set_sve_hint(). When set to true, denotes absence of SVE\nspecific live state on the CPU that implements SVE. Once set to true,\nSVE will be disabled in trap register and any SMC made using tftf_smc()\nwill set FUNCID_SVE_HINT in the SMC function ID.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I13055fe4102cc4e35af1d7091e88327a21778835\n" }, { "commit": "1768e59c3a6ac8d727ac012719b4b09947c8400d", "tree": "cc6ad04618bb60fb861bf3e7e4da2538c1a5cf42", "parents": [ "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue May 23 13:28:38 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:54 2023 +0000" }, "message": "feat(rme): add tests to check NS SME ID registers and configurations\n\nThese tests checks the functionality of RMM for NS SME support.\n- Create Realm and test ID registers specific to SME\n- Check if Realm gets undefined abort when it accesses SME\n- Check whether RMM preserves NS SMCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ia8ffd0188297a74c095dbadfb389add50c548e10\n" }, { "commit": "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581", "tree": "3e0552b2dae1f333abe34bddd7a4ea63c40f985f", "parents": [ "47b702c49a622e895d70104d78a20bb979dae229" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 06 16:31:19 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "feat(sme): add sme helper routines and add streaming sve support\n\nThis patch adds a few helper routines to set the Streaming SVE vector\nlength (SVL) in the SMCR_EL2 register, to enable/disable FEAT_SME_FA64\nand to get CPU\u0027s Streaming SVE mode status.\n\nThis patch also makes SVE compare routines compatible for both normal\nSVE and streaming SVE mode.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7294bb17a85de395a321e99241704066662c90e8\n" }, { "commit": "47b702c49a622e895d70104d78a20bb979dae229", "tree": "0d8eb64935c78a960998a4163c996f418c0fd96b", "parents": [ "92f1868013792ac13497d1045078b7e8a12d4f02" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 06 13:31:46 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "fix(sme): use rdsvl instead of rdvl\n\nUse rdsvl instruction to get Streaming SVE vector length instead of rdvl\ninstruction. When the CPU is in Streaming SVE mode both rdvl and rdsvl\ninstruction returns the same value but that is not true when the CPU is\nin Normal SVE mode. So it\u0027s preferred to use rdsvl to get SVL.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ieb6226f4fc275ee8a81eb359af465c26e307bc75\n" }, { "commit": "92f1868013792ac13497d1045078b7e8a12d4f02", "tree": "c94edb176be497ef790dfeaf98bb7b1e49cef824", "parents": [ "3dc2d746aa4bc44174a9981fa082c1473d0006a4" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Sat Sep 02 01:41:28 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "fix(sme): enable SME/SME2 during arch init\n\nThis change enables SME/SME2 for nonsecure use at EL2 for TFTF cases\nduring arch_setup. This removes dependency on testcases to explicitly\ncall sme_enable or sme2_enable to access SME or SME2 functionality.\n\nThis change also adds CPTR_EL2 register in suspend context. CPTR_EL2\nregister is saved/restored in CPU suspend entry/exit path.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2c99fd49c48c1a9ff2110747714db858a78d3a32\n" }, { "commit": "ab2fe6b01abef3c4b17ffb2c6ee4759f6801e095", "tree": "8285b1a38265e0fa5dd691874d8bf0cdd58aa93f", "parents": [ "406e19135f9fe88bb7794c60012759ca3fb3bdc8", "6e011646ae828f789fc8643e0e6a0c225130cd0c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 27 15:46:09 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 27 15:46:09 2023 +0200" }, "message": "Merge \"feat(handoff): add basic firmware handoff tests\"" }, { "commit": "6e011646ae828f789fc8643e0e6a0c225130cd0c", "tree": "d82ffdaee70f155372aac8519e8244d37f510a6f", "parents": [ "cdf525212326f8b453f22122dddc9d8bf0725981" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Sep 22 17:17:35 2023 +0100" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Oct 27 11:00:34 2023 +0100" }, "message": "feat(handoff): add basic firmware handoff tests\n\nAdd tests to sanity check information shared between BL31 and NS world\nusing the firmware handoff framework.\n\nChange-Id: I9d00292db7732157d0815e6159438c0db08551ad\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "fa05bd9ea226541e860789443b8f68f8d8846390", "tree": "e63b0399f570e205112b27f7fd92b3d26cbb1a74", "parents": [ "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 14:36:53 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 15:07:14 2023 +0100" }, "message": "feat(sve): add helper routines to read, write, compare SVE registers\n\nAdd helper routines to read, write, write_rand and compare SVE\nZ, P, FFR registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to configure SVE vector length and\nhas to pass memory to read/write SVE registers.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I3fa064c76a498ee2348d92cba2544a6e50331e15\n" }, { "commit": "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045", "tree": "68f9b32383bb80a3542368ebe9ffc15e4bba1c43", "parents": [ "035899729133080ffff3ed691ba65664c34f75ca" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 13:27:36 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:24:42 2023 +0100" }, "message": "feat(fpu): add helper routines to read, write, compare FPU registers\n\nAdd helper routines to read, write, write_rand and compare FPU state\nand FPU control/status registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to pass memory to read/write FPU\nregisters.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I10ae5487c9f58e46434c1bd5b42fd458ec755045\n" }, { "commit": "035899729133080ffff3ed691ba65664c34f75ca", "tree": "02a0b07c127329297d5c28e0683352357c8c0d8a", "parents": [ "73949a20b61def813b3265c2a6a330656bd001af" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 11:04:51 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:15:59 2023 +0100" }, "message": "fix(sve): represent sve Z0-31 registers as array of bytes\n\nCurrently each Z register is type defined as sve_vector_t but the helper\nroutine to write or read Z registers works based on current vector\nlength.\n\nIf test case defines \u0027sve_vector_t zregs[32]\u0027 and reads all Z registers\nusing sve_read_vector_regs() then zregs[n] might not corresponds to Zn\nregister unless the vector length is set to max value.\n\nThis patch also renames sve_vector_length_get() to sve_rdvl_1()\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I42955f8009bdd7f40d74c5a8d21d7c16ce6d761e\n" }, { "commit": "b69eae0e22dde3487cc0edcf0c8d2e092f54cf13", "tree": "19a9dc33bef7c68b8de1efe361bbd1f7b30434ef", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 10:27:58 2023 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Sep 08 12:24:42 2023 +0200" }, "message": "feat(rmm): modify rmi_realm_params structure\n\nThis patch modifies rmi_realm_params structure\naccording to definition of RmiRealmParams in\nRMM Specification 1.0-eac1.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I63c3097290004de90cd2222b24419aef517d9b49\n" }, { "commit": "507ed939b32d26244412af3f6253a7adcc22420c", "tree": "e47b85a68d09cea2d4b9d29998c2893141ece874", "parents": [ "c94fb400ec40a8550a89cd484bd1137dca029336" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Jul 10 16:09:31 2023 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Thu Aug 24 11:08:53 2023 -0500" }, "message": "refactor(fgt): modify FEAT_FGT test to check for init values\n\nThe original test checked only if FEAT_FGT was enabled. This new version\nof the test also checks whether the values of registers HFG*_EL2 are the\nvalues used during initialization.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I17673b813da7f14ef03349eead2c0a47cf3a8b26\n" }, { "commit": "c94fb400ec40a8550a89cd484bd1137dca029336", "tree": "863c7398f9252136f958d03c3b6d6ce5fc781ec1", "parents": [ "c68ba0dec2989735fa24a8ed4efcf9cd76af2b05" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri Jul 21 17:19:42 2023 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Thu Aug 24 11:05:53 2023 -0500" }, "message": "feat(cpufeat): add feat detection helpers\n\nThis patch adds multiple feature detection helpers, useful for\ntests that need to check for the presence of those features.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ie6d39b9e9c8d28d0a4cd9d02350e2bedd016e45e\n" }, { "commit": "9d0cfe88aedc34f1b61a51ff18013743c56e2fbc", "tree": "b5b65d1a477d3d46aacfb69bd3dff348a2136ce4", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Apr 17 10:57:26 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Jul 25 17:00:33 2023 +0100" }, "message": "test(tftf): test PAuth in Realm\n\n- Enable PAuth in Realm RL1 by default.\n- Check if PAuth keys are accessible in Realm RL1.\n- Check if Realm PAuth keys are preserved across RMM entry/exit.\n- Check if NS PAuth keys are preserved across RMM entry/exit.\n- Generate PAuth fault by cloberring LR.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I85d8e03ec604c96117555e7aa866453cb2745cfe\n" }, { "commit": "d648077f8284ada21b03871ce06bf568a2333bbd", "tree": "b2307d260395753bd714732500f51cd1f307f1ff", "parents": [ "baed8dd3577633768837048cb71351fb135d59ee" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Feb 27 13:23:06 2023 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 13 13:58:31 2023 +0200" }, "message": "feat: introduce SError exception handler\n\nIntroduce SError exception handler along with support to register a\ncustom handler. The default behaviour is same as before if no handler\nis registered.\nThis patch will allow tests to do a graceful exit after handling an\nSError.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Idbe37d3690e3a8e08fa3b0dff496d18d3022a8fc\n" }, { "commit": "2a32ff7161ef8711f9e7420c499a246e3d055f42", "tree": "041037f8c7b3126163c8988fd8041712da8447ff", "parents": [ "ec59c59afc953c306a4b83e919a787694ee6a88f" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu May 25 17:51:48 2023 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Jun 06 11:00:21 2023 +0100" }, "message": "feat(xlat): add support for 52 bit PA size with 4KB granularity\n\nThis patch adds support to the xlat library to for 52Bits of\nPA size with 4KB granularity (FEAT_LPA2). The patch only reports\nthe right granularity when it supports FEAT_LPA2 and it does\nnot enable the feature.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Iee0cab8e1f8844a6af135771d8f940ec7e1dce84\n" }, { "commit": "5270d01e968b1b0a8b853a9263e767a467e541b9", "tree": "ac67959df7b5d536b4c662ed1f0a0e2f19970980", "parents": [ "c1136a849fc21470313e4e852a22ae4b9db50440" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 19 14:53:42 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed May 24 13:40:42 2023 +0100" }, "message": "tftf(rme): check if RMM doesn\u0027t leak Realm contents in SVE registers\n\nThis test verifies that the Realm contents in SVE registers are not\nseen by NS world once the Realm returns back to the host. This test\nperforms the below steps:\n\n1. Set NS world SVE VQ to max and write a known pattern.\n2. Set NS world ZCR_EL2 with VQ as 0 (128 bits).\n3. Create Realm with max SVE VQ\n4. Call Realm to fill in Z registers\n5. Once Realm returns, NS sets ZCR_EL2 with max VQ and reads the\n Z registers.\n6. The upper bits of Z registers must be either 0 or the old values\n filled by NS world at step 1.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I8205190d1ce9c37b99d35cf5b15df21ca9b838c3\n" } ], "next": "c1136a849fc21470313e4e852a22ae4b9db50440" }