)]}' { "log": [ { "commit": "718fd7902c015a64b49b12dcb6005d1aa50fd72e", "tree": "6be817fbd9b1073bdd876b527e31e06e45b8a782", "parents": [ "5032d7bc760128a07ace8c9d4d91f7c3e9011cda" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Nov 08 14:55:20 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jun 12 22:45:11 2025 +0100" }, "message": "feat(rme): add dev granules tests\n\nAdd tests for RMI_GRANULE_DELEGATE and\nRMI_GRANULE_UNDELEGATE commands using\ndevice granules.\nAdd plat_get_dev_region() function to\nretrieve platform PCIe memory region info.\n\nChange-Id: Ie59361dd28e11db348c30b033c156de044aa0ffc\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "d72394d0965829a319701247ac8522c365f9e55d", "tree": "506d71bf4de98babd4f0a3ee9ac8d2528814d2f8", "parents": [ "7692564d4e05affc177c245884ca160fca57a3ef" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Wed Apr 23 10:51:15 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Mon Apr 28 08:20:26 2025 +0000" }, "message": "fix(versal2): update test skip list\n\nSkipping tests related to invalid entry addresses and system suspend\nwith cores suspended. This will continue until the implementation in\nTF-A is completed to properly handle invalid entry addresses and\nresolve system suspend failures.\nAdditionally, skipping tests for FFA Group0 in the normal world since\nFFA support is not available.\n\nChange-Id: Icc62f563ffb0321f7cdc2e7399a3c3b6c908d778\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "7692564d4e05affc177c245884ca160fca57a3ef", "tree": "4efc4526184a55be45988545ff43e6dc0ba70865", "parents": [ "060efe97ff6c31b7dbec96af9fde0b169db4183d" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Wed Apr 23 10:37:01 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Mon Apr 28 08:20:22 2025 +0000" }, "message": "fix(versal2): update tftf and uart base address\n\nUpdate TFTF base address as per new DDR address map along\nwith default console base address set to Uart1.\n\nChange-Id: I4dddee2e01984a4fcef1d86ad9a92aff3baaa961\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "2373cbb8ace3d400d2bd0f336507219ae926ae36", "tree": "63bc19ed2f7bca762ae165804feba211391d3697", "parents": [ "aeb5c5ccb10a569c258d2b3e24841da4d234d3df" ], "author": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Tue Apr 01 15:18:18 2025 +0530" }, "committer": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Mon Apr 21 12:16:51 2025 +0530" }, "message": "fix(versal-net): check ttc irq status\n\nContinuous interrupts are observed after cancel timer operation\nas proper cleanup is not done in cancel timer routine.\nProvide proper cleanup in cancel timer routine by reading the\nttc interrupt status register for cause of interrupt and disabling\nthe ttc counter by setting bit 0 in ttc counter control register.\nValue of per-cpu hypervisor timer interrupt id is set to 26 in\naccordance with arm documentation and reference for same is present in\narm juno and nvidia settings.\n\nChange-Id: I4f19314deaec9fa05b6fcbe04d0192e3c2a1a772\nSigned-off-by: Amit Nagal \u003camit.nagal@amd.com\u003e\n" }, { "commit": "b319e455fb8cdaf24d5623cb0617dd496839bb95", "tree": "6d08225409590233f1757d2c32d08220df9300a3", "parents": [ "5179144894ba1c30dfa6befc90eaac8b93839840" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Apr 15 11:36:56 2025 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Apr 16 09:53:05 2025 +0100" }, "message": "feat(neoverse_rd): deprecate and remove NRD1 platform includes\n\nAs NRD1 platforms have been removed, remove common includes for\nNRD1 platforms.\n\nChange-Id: I0805fc135837b2257b51d9a21dd678178b5df8e2\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "5179144894ba1c30dfa6befc90eaac8b93839840", "tree": "aeacb613100d73dd07d647398ca0cb6d520af6ff", "parents": [ "dc4235a917f6e7b4981a5de027e05f2bc8875d4d" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Apr 15 11:34:50 2025 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Apr 16 09:52:57 2025 +0100" }, "message": "feat(neoverse_rd): deprecate and remove RD-V1 platform variants\n\ndeprecate and remove support for RD-V1 and RD-V1-MC platform variants.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I59003ae3a6b3ea0f603f3282c31efc37d312e1fd\n" }, { "commit": "dc4235a917f6e7b4981a5de027e05f2bc8875d4d", "tree": "2c99e6ab6fe0d92af43331cb79ec58b36355fbfb", "parents": [ "d685f8cfd3cf66a64e2afa0f36a217f7f1a461e0" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Apr 15 11:34:22 2025 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Apr 16 09:52:48 2025 +0100" }, "message": "feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants\n\ndeprecate and remove support for RD-N1-Edge and RD-N1-Edgex2 platform\nvariants.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I2b00f3550c8ef0f4d80236d856d644762881eba3\n" }, { "commit": "d685f8cfd3cf66a64e2afa0f36a217f7f1a461e0", "tree": "e91b03d14edc19304132d85ded19ea1aad2087df", "parents": [ "d06a6f50017d79d67be8c8742ad578963a089024" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Apr 15 11:30:08 2025 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Apr 16 09:52:38 2025 +0100" }, "message": "feat(neoverse_rd): deprecate and remove SGI-575 platform\n\ndeprecate and remove support for SGI-575 platform.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: Ia86236155c3185991841ebd05851ac0bfb84ada2\n" }, { "commit": "42dd088203e40911c67106d46cfccde58d55e1b5", "tree": "48f1d07ae117eadadd1c0496cc0a8ad895abff3b", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd", "c779d0d0ac9faf894963675dcccb6110e3f0229a" ], "author": { "name": "Sandrine Afsa", "email": "sandrine.afsa@arm.com", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "message": "Merge changes from topic \"xlnx_fix_custom_inval_entry\"\n\n* changes:\n fix(versal): platform definition of invalid entry\n feat(tftf): new interface to get an invalid entrypoint address\n" }, { "commit": "c779d0d0ac9faf894963675dcccb6110e3f0229a", "tree": "66a0d99df1847e1ac663da0a378e4d92f3ba63bd", "parents": [ "1e4f7a064f08205a0a37922e660b238be04a8137" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:43:37 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:47 2025 +0000" }, "message": "fix(versal): platform definition of invalid entry\n\nAdd platform specific function to return custom entry address.\n\nChange-Id: I58785a8b7c197e4dae3ac9a29f8d23c29d5cb5e3\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "1e4f7a064f08205a0a37922e660b238be04a8137", "tree": "ccf0e6f9e63ee23a7b249eed564ceedafcee9035", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:40:56 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:16 2025 +0000" }, "message": "feat(tftf): new interface to get an invalid entrypoint address\n\nTFTF test for invalid entry address in cpu hotplug, validates\nfor default entry address 0x0 which doesn\u0027t account for platforms\nfor which 0x0 is a valid address. Added function to retrieve invalid\nentry address for default scenario and platform implementation to\nretrieve specific custom invalid entry address.\n\nChange-Id: I9f109acc8d0443dabd3088cb31852900e8e07853\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "af8934c8574fd64bef6ac4b0201c2144b78c8fd7", "tree": "33c29f9b95a29b2b879fc8055d994787b5e79fce", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Fri Jul 26 14:51:14 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Jan 31 16:48:58 2025 +0000" }, "message": "test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\n\n* This patch adds a test that suspends to affinity level 2 with another\n CPU running in a different power domain.\n\n* Previously with the bug identified and resolved in commit (01959a1),\n the function \"psci_is_last_cpu_to_idle_at_pwrlvl\" checked only one\n power domain when suspending to level2. This meant that if there was\n a cpu running outside the power domain of the calling CPU, the suspend\n request would be allowed. But in this case, the request should be\n denied. This test case validates this behaviour and ensures the\n request is denied.\n\n* This patch also adds the following global variables to parameterise\n and reuse the existing functions for the new test.\n * test_should_suspend - an boolean array that allows you to leave\n some CPUs running.\n * test_should_deny - a boolean to specify if the suspend request\n should be denied.\n * cpu_finished - an array of events so that the running CPUs know\n when to terminate.\n\n* Additionally this patch also adds a function to get a CPU that is\n in a different cluster to the lead CPU.\n\nRefer to TF-A commit (01959a1) for more information on the bug.\n\nChange-Id: Ib163aa8d5347baeaa47d1ae6f59599f1c68c11a8\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "d49873af4a07659bbf8fd9c07119a7d85f9cda89", "tree": "2b8e1f0c9e74cee68e382a53c12f085e6e76c2e6", "parents": [ "58a254ae181886efcf6e691789a67d5c145eecf4" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Thu Jul 25 13:45:13 2024 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Thu Nov 28 11:31:04 2024 +0000" }, "message": "feat(neoverse_rd): add TFTF support for RD-V3 platform\n\nAdd platform files to enable TFTF on RD-V3 platform.\n\nChange-Id: Icd6f512a01b1582e3251c8c0b242dc0999da0d15\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "2c2810f79e57e78d77899084b5439cbdd1aaa464", "tree": "5d5644927acc2f4a212ba18558c7ed57f3d1e07c", "parents": [ "ea43ac0daef913576cf214454cf81482d8cf109a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 15 17:11:24 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 05:21:39 2024 +0200" }, "message": "fix(realm): make PCIe tests default for testing\n\nThis patch moves the PCIe DOE test to the default realm world\ntestsuite.\n\nAlso fixes some build issues and hardens the PCIe functions.\n\nNote that FVP_Base_RevC model needs to have the following\noptions enabled for the PCIe tests to work :\n\n -C pci.pcie_rc.ahci0.endpoint.doe_supported\u003d1\n -C pci.pcie_rc.ahci0.endpoint.ide_supported\u003d1\n\n\nChange-Id: Icfd6b68799b0bacb44299c6a3cf99a3c425f833d\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "b607317afc8c6ad5f37ac8873dfa8777c50b96aa", "tree": "ade1fb648af0b10a6080c9a8035962b7ef0176f3", "parents": [ "6abf05e7077e19281443e773012bc81e8e659786", "784c6d220ea2b62b20e58eb814ba379349ce1665" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Nov 19 15:50:14 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 19 15:50:14 2024 +0100" }, "message": "Merge changes from topic \"xlnx_plat_skip_query_pmf\"\n\n* changes:\n fix(zynqmp): update test skip list\n fix(versal-net): update test skip list\n fix(versal): update test skip list\n" }, { "commit": "784c6d220ea2b62b20e58eb814ba379349ce1665", "tree": "56b6ce66cb9fd60b5d96f0680fc479e40f61e9c2", "parents": [ "746b32be41f26c3cb29031bb01ab0c3efd3d890b" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Nov 15 09:32:52 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Mon Nov 18 08:23:36 2024 +0000" }, "message": "fix(zynqmp): update test skip list\n\nTest cases \"Query Vendor-Specific Service\" and \"Probe PMF version\"\nare failing since PMF is not supported on AMD platform.\nTest cases will be skipped till non-availability of PMF support.\n\nChange-Id: I82c85838b2b10ccf2d044925b7b713a0edf5556a\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "f675feb04d6583e80770a1cda48989a3f27e61fa", "tree": "94a32197863ac3dc2d6a050eb4321887fdf41ceb", "parents": [ "27f833a0817002e1ea9b88e11ba173357588afcc" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Wed Nov 13 11:37:30 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Thu Nov 14 09:09:57 2024 +0000" }, "message": "fix(versal2): move timer clk offset definition to platform header\n\nFor Versal2 platform TTC_CLK_SEL_OFFSET is defined in common timers source\nwhich is creating build conflict for other platform.\n\nMoving the definition for TTC_CLK_SEL_OFFSET to versal2 platform header.\n\nChange-Id: I1e2db4c591520be12e568d84da290b17d72bf897\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "746b32be41f26c3cb29031bb01ab0c3efd3d890b", "tree": "e94b5d241de2e796ae6a540c814ea9eb00072194", "parents": [ "ac24bb830b3b6da926c71aec40150688fd3c338d" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 05 06:18:51 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 12 03:23:10 2024 +0000" }, "message": "fix(versal-net): update test skip list\n\nTest cases \"Query Vendor-Specific Service\" and \"Probe PMF version\"\nare failing since PMF is not supported on AMD platform.\nTest cases will be skipped till non-availability of PMF support.\n\nChange-Id: I40fd7defea853d0a1aee5da79924d4ee5c15cfaa\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "ac24bb830b3b6da926c71aec40150688fd3c338d", "tree": "280ce1e731cbb573344a9a7dec1fa453d3abd38f", "parents": [ "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 05 06:18:39 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 12 03:23:03 2024 +0000" }, "message": "fix(versal): update test skip list\n\nTest cases \"Query Vendor-Specific Service\" and \"Probe PMF version\"\nare failing since PMF is not supported on AMD platform.\nTest cases will be skipped till non-availability of PMF support.\n\nChange-Id: I560ee5b69244cee13003a71c8ecc5848a1b903e6\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "7dbb6c110477adaca32d3afce88135ec76dac6e7", "tree": "26bd19cda1226669eb5c8abe0e5b4995fcb606be", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Oct 04 03:22:30 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Oct 22 04:39:42 2024 +0000" }, "message": "feat(versal2): add support for AMD Versal Gen 2 platform\n\nIntroduce platform support for AMD Versal Gen 2.\n\nSummary:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 194\nTests Passed : 29\nTests Failed : 0\nTests Crashed : 0\nTotal tests : 223\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nNOTICE: Exiting tests.\n\nChange-Id: I608dd556be402f97f9960c688b7d0caa6f17c5c3\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nSigned-off-by: Michal Simek \u003cmichal.simek@amd.com\u003e\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "9f2de630d5d2472e8ec7348507e343738934940d", "tree": "4905c2ec19086fbdecde033abd1f2f766d98f692", "parents": [ "36ed009a073c64a422c769b46eede6538fa42667" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 11:48:22 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 13 18:20:18 2024 +0200" }, "message": "feat(doe): add PCIe DOE tests\n\nThis patch adds PCIe DOE tests for\n- DOE discovery protocol\n- SPDM get version\nTo build this test suite use \u0027TEST\u003dpcie-doe\u0027\noption.\n\nThe spdm.h is imported from https://github.com/DMTF/libspdm\nproject.\n\nChange-Id: I8db1048d01b4f8061d8a4ddccc198159ed61e6b7\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "36ed009a073c64a422c769b46eede6538fa42667", "tree": "e7c152d972ff234597afff7712780b0bdab3fb2c", "parents": [ "9f0dc01f4d4f6f1800e86c4c6f1e8377e119a713" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:37:54 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:37:54 2024 +0100" }, "message": "feat(pcie): add PCIe support to FVP platform\n\nThis patch adds PCIe support to FVP platform.\n\nChange-Id: If47077dac50dd090c0e949213688a6427d29872b\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "3d804155c21db7f97f00bfec7eb14ef83f45f7bc", "tree": "769aa020c30105ed45c758f177c819f3c31edaa9", "parents": [ "f13410b3e4d9a2526333d2621ad5e8aede6c2b86" ], "author": { "name": "Harsimran Singh Tungal", "email": "harsimransingh.tungal@arm.com", "time": "Wed Sep 04 14:38:03 2024 +0100" }, "committer": { "name": "hartun01-arm", "email": "harsimransingh.tungal@arm.com", "time": "Wed Sep 04 16:52:30 2024 +0200" }, "message": "fix(corstone1000): skip some TF-A tests\n\nSome of the TF-A tests get stuck when run on TF-A master for Corstone-1000.\nSo, skip those tests for now for Corstone-1000. This change is required to integrate Corstone-1000 FVP platform in TF-A Open CI\n\nChange-Id: I3fd06200141e18b9c6c767718aaf52aede136560\nSigned-off-by: Harsimran Singh Tungal \u003charsimransingh.tungal@arm.com\u003e\n" }, { "commit": "ccd82702aeb079cc5c20ef4227726c576a731fa9", "tree": "150279b593dbce693f96454daeae1090720f75b5", "parents": [ "4ccb1ef774f03e2d1cc74fdb93aa53088c1073c6" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Jul 31 16:27:23 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:35 2024 +0200" }, "message": "refactor(neoverse_rd): introduce flash and ros macros\n\nAs part of the refactoring for TFTF on the first and second\ngeneration of platforms, introduce flash related memory layout\nmacros to be added in nrd_ros_def1.h and nrd_ros_def2.h files.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I01929bbd465d777e827c3eb547bb973339bd4308\n" }, { "commit": "4ccb1ef774f03e2d1cc74fdb93aa53088c1073c6", "tree": "32e6cd47416c4032b5a49e200d597c61eb732384", "parents": [ "2d20ac071513593961e7ddd9033eae70b36aaf83" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Jul 31 13:28:08 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:31 2024 +0200" }, "message": "refactor(neoverse_rd): introduce timer and watchdog macros\n\nAs part of the refactoring for TFTF on the first and second\ngeneration of platforms, introduce timer and watchdog related\nmemory layout macros to the nrd_css_def1.h and nrd_css_def2.h\nfiles.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: Iabe4c310ed4297d71cf53869a68d45c5c589fce2\n" }, { "commit": "2d20ac071513593961e7ddd9033eae70b36aaf83", "tree": "90c6981aa04a1f1856d646ab7be335bb595fc69f", "parents": [ "3a426d6d89621fdc7e913e11dc2614742b86a584" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Jul 29 15:35:07 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:24 2024 +0200" }, "message": "refactor(neoverse_rd): define naming convention for CSS macros\n\nAs part of the refactoring for TFTF on the first and second generation\nof platforms, introduce a naming convention for macros within\nnrd_css_def*.h and nrd_css_fw_def*.h. All CSS related macros must adhere\nto the format NRD_CSS_\u003cname\u003e.\n\nChange-Id: I756c46688dd66dfc6b1d89159ebcd39d68c8f91c\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "3a426d6d89621fdc7e913e11dc2614742b86a584", "tree": "69e36c1da8305418047bd698ae17cbcdf75a07cd", "parents": [ "b79a256cfe2419ccc8c48a78a89e7b7735330fe0" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Jul 29 13:11:53 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:14 2024 +0200" }, "message": "refactor(neoverse_rd): remove deprecated header files\n\nTF-A underwent a major rehaul in directory structure. This change\ndeals with removal of the previous common include files that are\nnow deprecated.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I0c77ee262b26f7bd5d8660b481f19aab8d721246\n" }, { "commit": "b79a256cfe2419ccc8c48a78a89e7b7735330fe0", "tree": "27fb1c3e3ac16344f8cf96eb269a50967e475a74", "parents": [ "61b321e9f8f3a3cd8398b65e5f733abc5577d1a4" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Jul 29 13:07:55 2024 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 15:13:10 2024 +0100" }, "message": "refactor(neoverse_rd): refactor header files for second gen platforms\n\nTF-A underwent a major rehaul in directory structure. This change\ndeals with refactoring the header files for second generation platforms\ngrouped as nrd2 in TFTF to a structure that aligns with that of TF-A.\n\nChange-Id: I263a91e768644b491a0dc2b706e7c88d6b65e8a9\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "61b321e9f8f3a3cd8398b65e5f733abc5577d1a4", "tree": "863f915c79985c36554a565fb1daa4bffd17d566", "parents": [ "e95e53f8607b98d06afdd1302722d3f23dca3591" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Fri Jul 05 10:59:33 2024 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Aug 06 16:06:29 2024 +0100" }, "message": "refactor(neoverse_rd): refactor header files for first gen platforms\n\nTF-A underwent a major rehaul in directory structure. This change\ndeals with refactoring the header files for first generation platforms\ngrouped as nrd1 in TFTF to a structure that aligns with that of TF-A.\n\nChange-Id: I0931f369ff390ae000f49c021a8c9dfc17f34b97\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "e713f655c81cd293ed03211437281c00da444171", "tree": "2ec8d0258d90be8bf17449431855e84078e8f7a4", "parents": [ "57b94c4410d3568754feb1aede059ad794a345a7" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Mar 27 17:09:53 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:21:28 2024 +0200" }, "message": "refactor(spm): rename FF-A SIMD test suite\n\nRename \"SIMD,SVE Registers context\" test suite to \"SIMD context\nswitch tests\".\nRename test case \"Check that SIMD registers context is preserved\" to\n\"Check that Adv. SIMD registers context is preserved\".\nUpdate platform tests_to_skip files accordingly.\nRemove redundant \"SIMD,SVE Registers context\" instance from\ntftf/tests/aarch32_tests_to_skip.txt\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ida5f46a8d0ec822a6629b660c41dfcf9c7e200e7\n" }, { "commit": "d0704f69f4824d6100faabd19522e0205c926e92", "tree": "cbc56389b7c54fe0021fcfab729b9f5c48f9c5d2", "parents": [ "65442a9ca6fd1062f0eb34c4ac9f62f781dcf352", "c3cf2daed819a9d01feba31832544309c9da8d70" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Jul 29 18:54:59 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 29 18:54:59 2024 +0200" }, "message": "Merge \"feat(amu): test AMU counter restriction (RAZ)\"" }, { "commit": "cd6c94b20e7450e27254856a82008ca0595d84d1", "tree": "6a8146d2ef87f4c5a0f72f84b850e1577c57a4a4", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Feb 15 17:19:05 2022 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jul 23 14:06:14 2024 +0100" }, "message": "feat(ls64): add a test for 64byte loads/stores instructions\n\nThis patch adds a test to verify the 64 byte load and store\ninstructions introduced by FEAT_LS64.\nThe test primarily executes instructions:\n1. LD64B\n2. ST64B\nand ensures that the NS-EL2 has no dependency on EL3 while\nrunning them.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I7a4ca0ee4a2c18bf0de030c72e35eb218bc6364c\n" }, { "commit": "c3cf2daed819a9d01feba31832544309c9da8d70", "tree": "d47120e316a97ea94409e1a61594ec6da1f5a71b", "parents": [ "caff038b3f0b261b1fcc14f7918a80fa515202c1" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Apr 01 13:57:19 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri May 10 13:40:04 2024 -0500" }, "message": "feat(amu): test AMU counter restriction (RAZ)\n\nWhen using AMU counters, there is risk of exposing information to\nlower exception levels. In order to prevent this, counters are\nrestricted, so they are read as zero (RAZ) at a lower EL. This\ntest verifies that counters are read as zero after forcing counting\nthrough instructions that trigger MPMM \"gear shifting\" (e.g.: by\nexecuting SVE instructions).\n\nNote: This test applies to TC2 only, as it is the only platform that\n supports MPMM currently.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ic32ba19fa489cf479947d4467ddb84e6abd1b454\n" }, { "commit": "aa68c6cdf4ac0d13162df4e2221f90c5062fb963", "tree": "cd7895e6968a490adce5303dfbc388e51e755b7f", "parents": [ "5c5f7bdf581348dc8e483b2e4fc3b34b8bae56d2" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Wed Feb 07 09:42:28 2024 -0600" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Mon Mar 11 13:41:38 2024 -0500" }, "message": "fix(arm): check for null before calling I/O policy callback\n\nI stumbled across this when passing a non-present image id into\nthe plat_get_image_source function, which caused it to jump\ninto nowhere, and fault. The image id was less than the maximum\nsize of the policy array, but was an empty entry.\nThis check prevents the jump into nowhere.\n\nChange-Id: If5861f0e09b6b2244aee1ec52ce7c91bb7d62ec8\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\n" }, { "commit": "5c5f7bdf581348dc8e483b2e4fc3b34b8bae56d2", "tree": "2e547e822e5decb80e3a8b6262c52c2af574b31a", "parents": [ "95f5b30baa661da046d3364daf44851673000ce9", "f86d2d3a8af0084f63d8012a899c9e4eb128c0df" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Mar 08 11:50:09 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 08 11:50:09 2024 +0100" }, "message": "Merge changes from topic \"xlnx_versal_net_test_skip\"\n\n* changes:\n fix(versal-net): update test skip list\n fix(versal): update test skip list\n" }, { "commit": "7c9f2fc8f6bf5768c5643c10df8ab434129f811f", "tree": "57fb964c332bf561d604736c5e2f286961c85963", "parents": [ "1f099ddf7ac01f8e01627fd251b743e8f2d49f5a" ], "author": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Thu Feb 08 16:35:08 2024 +0530" }, "committer": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Fri Mar 08 10:29:07 2024 +0530" }, "message": "feat(zynqmp): introduce platform support\n\nIntroduce platform support for AMD-Xilinx zynqmp, an adaptive\ncompute acceleration platform (ACAP).\n\n- TF-A cadence driver is used for console.\n- TTC is used for Timers.\n\nsummary:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 193\nTests Passed : 29\nTests Failed : 0\nTests Crashed : 0\nTotal tests : 222\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nNOTICE: Exiting tests.\n\nChange-Id: Ia63df682f8e97cc3a5d88468bf0df71f6bb3fc26\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nSigned-off-by: Amit Nagal \u003camit.nagal@amd.com\u003e\n" }, { "commit": "e39d55ab48b30c610859c277551b97c65cbe82bf", "tree": "e57adfb2e031af25a9f67d68ed6f06e35065890e", "parents": [ "296fab081902f787e2cac464fe4d019b490c495b", "b5154bcc110747a4bfdb605b7a346377a55643a2" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Sat Mar 02 12:30:04 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Mar 02 12:30:04 2024 +0100" }, "message": "Merge changes from topic \"sgi_to_nrd\"\n\n* changes:\n fix(arm): fix comments referencing \"SGI platform\"\n refactor(sgi): replace references to \"SGI\"/\"sgi\" for neoverse_rd\n refactor(sgi): rename \"CSS_SGI\" macro prefixes to \"NRD\"\n refactor(sgi): move apis and types to \"nrd\" prefix\n refactor(sgi): replace build-option prefix to \"NRD\"\n refactor(sgi): regroup \"sgi\" and \"rdinfra\" to \"neoverse_rd\"\n" }, { "commit": "f86d2d3a8af0084f63d8012a899c9e4eb128c0df", "tree": "ee02cdd8d7357f3bf1edcda5ba7eb7180a7e8b00", "parents": [ "60b7f91b9009c2dee19b0e66b8833bfbdbe97df2" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Feb 16 11:05:41 2024 +0530" }, "committer": { "name": "Kummari Prasad", "email": "prasad.kummari@amd.com", "time": "Tue Feb 27 07:23:51 2024 +0100" }, "message": "fix(versal-net): update test skip list\n\nThe test case \"PSCI CPU Suspend in OSI mode\" is failing due to failure\nlogs from other firmware. Once the errors are resolved, the test cases\nwill be enabled.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I014965cb0e406ee4ec4a9d49b83e67d24ff0993b\n" }, { "commit": "60b7f91b9009c2dee19b0e66b8833bfbdbe97df2", "tree": "ea89cfe88523d6e997ec8e7754ba7872c18d0f05", "parents": [ "a8deec5c0b51719b1f268e4f106c3a095a387074" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Feb 16 09:42:55 2024 +0530" }, "committer": { "name": "Kummari Prasad", "email": "prasad.kummari@amd.com", "time": "Tue Feb 27 07:21:50 2024 +0100" }, "message": "fix(versal): update test skip list\n\nIn Versal, the SCNTR and SCNTRS registers are inaccessible from NS EL1.\nInstead of using the SCNTR register, using TTC timers. The test case\nCNTFRQ compare test compares the values of cntfrq_el0 and ns_cntfrq.\nThe cntfrq_el0 value is obtained by reading the cntfrq_el0 register,\nwhile the ns_cntfrq value is obtained by reading from the mmio address\nSYS_CNT_BASE1 + CNTBASEN_CNTFRQ (0x10), where SYS_CNT_BASE1 represents\nthe TTC base register, CNTBASEN_CNTFRQ is the counter Frequency register\noffset, is not applicable for Versal platform. The test case fails because\ncntfrq_el0 and ns_cntfrq are not equal.\n\nThe test case \"PSCI CPU Suspend in OSI mode\" is failing due to failure\nlogs from other firmware. Once the errors are resolved, the test cases\nwill be enabled.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I0598c6886dd18bcf2caa47c36c9a0d1fbd7a2ab7\n" }, { "commit": "b5154bcc110747a4bfdb605b7a346377a55643a2", "tree": "f1527b16cec5b8eb497a6531c3c100e8d21428fe", "parents": [ "381d3912cedb1c257d9829933d723b117949e1e7" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Thu Feb 15 11:32:56 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:58:44 2024 +0000" }, "message": "fix(arm): fix comments referencing \"SGI platform\"\n\nCurrently, both N1SDP and TC platforms have references to \"SGI\" within\na comment in their respective source files. Fix this by replacing it\nwith the appropriate platform name.\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I523c3ef0bfa76d35819a8f776a08820ffd197c44\n" }, { "commit": "381d3912cedb1c257d9829933d723b117949e1e7", "tree": "e002d32e202aeb6ded5d9795a2914e4de6db5259", "parents": [ "5b113e102a86fbf61137c9f700c696609cfd503b" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Thu Feb 15 11:28:31 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:58:07 2024 +0000" }, "message": "refactor(sgi): replace references to \"SGI\"/\"sgi\" for neoverse_rd\n\nCurrently, there are several reference to \"SGI\" or \"sgi\" in comments or\nas macro prefix within the neoverse_rd directory. As part of the\nmigration to neoverse_rd, rename all occurences of \"SGI/sgi\" to\n\"Neoverse-RD\" or the \"NRD\" prefix accordingly. All references in\ncomments are rephrased as \"Neoverse RD platforms\". References in code\nare renamed as \"NRD\"/\"nrd\" accordingly.\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I55bdab01051974b3ddb2dae3bc4c0e253fb85fc3\n" }, { "commit": "5b113e102a86fbf61137c9f700c696609cfd503b", "tree": "9d35921dfa15afd1826bbe55cd02b5db6d77745a", "parents": [ "3f3f3e9e4ce8de3d6737d4ae9e2dd77fea11fb9c" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Wed Feb 14 12:49:55 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:57:40 2024 +0000" }, "message": "refactor(sgi): rename \"CSS_SGI\" macro prefixes to \"NRD\"\n\nAs of now, several internal macros utilize \"CSS_SGI\" as their prefix.\nGiven the change to neoverse_rd, the prefix \"CSS_SGI\" is no longer\nappropriate. Therefore, update the macro prefixes to \"NRD\" for\nconsistency and clarity.\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I252a5ece6c82a0a5a3b451238ed0da07f8a0c81e\n" }, { "commit": "3f3f3e9e4ce8de3d6737d4ae9e2dd77fea11fb9c", "tree": "e7913a36e9f110b29da39c1a557791ee2620b0a5", "parents": [ "8836f620855c8a7ed650b262e7704c54be5d2c0a" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Wed Feb 14 12:47:42 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:57:13 2024 +0000" }, "message": "refactor(sgi): move apis and types to \"nrd\" prefix\n\nCurrently, functions and types internal to neoverse_rd platforms are\nnamed with \"sgi\" as the prefix. Since common code and platforms are no\nlonger under the \"sgi\" umbrella, move the prefix to \"nrd\". This change\nwould amend the prefixes for functions, types and objects.\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I1080259b661081c535ab46f61df9e4563420bdb0\n" }, { "commit": "8836f620855c8a7ed650b262e7704c54be5d2c0a", "tree": "5dbb309edfeefc98c057bbe5a055b66edcb2e450", "parents": [ "cac32e9262ee8e0e23d2e3b6551227767297717f" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Wed Feb 14 12:43:21 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:56:24 2024 +0000" }, "message": "refactor(sgi): replace build-option prefix to \"NRD\"\n\nAs of now, CSS_SGI_PLATFORM_VARIANT and CSS_SGI_CHIP_COUNT are the\nexternal build option that sgi platforms support. As \"sgi\" has been\nrenamed to \"neoverse_rd\", replace the prefix \"CSS_SGI\" with \"NRD\".\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I585575788c14d1c3b26ab336672ef149771dab98\n" }, { "commit": "cac32e9262ee8e0e23d2e3b6551227767297717f", "tree": "495fd75302643a9a4097fe2c75b30b8de3a7fbe9", "parents": [ "90d61cd1e36634597a71b86fcb9701b94741a553" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Tue Feb 13 22:02:45 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Sun Feb 18 15:33:02 2024 +0000" }, "message": "refactor(sgi): regroup \"sgi\" and \"rdinfra\" to \"neoverse_rd\"\n\nCurrently, reference design platforms such as RD-N2, RD-N1-Edge, RD-V1,\nand SGI-575 utilize \"sgi/common\" as the common source directory. The\n\"sgi\" prefix originated from the System Guidance Infrastructure (SGI)\nand was initially associated with the SGI-575 platform. However,\nsubsequent platforms released were under the Neoverse reference design\nproduct name.\n\nTo align with the Neoverse reference design nomenclature, regroup all\ncommon and board files within neoverse_rd directory. Consolidate common\nsources and headers under neoverse_rd/common. Board files for RD-V1,\nRD-N2, RD-N1-Edge and SGI-575 are moved to neoverse_rd/platform. With\nthe changes in this commit, the tree view would look as follows:\n\n├── neoverse_rd\n│   ├── common\n│   │   ├── arch\n│   │   └── include\n│   └── platform\n│   ├── rdn1edge\n│   ├── rdn2\n│   ├── rdv1\n│   └── sgi575\n\nAdditionally, update all file prefixes from \"sgi\" to \"nrd.\"\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I07e2af143fad82e48172612fe0e28db6464fa901\n" }, { "commit": "9c73678243bd8c27cd50b8fc097559444025cf40", "tree": "5f0f6c2eceeabb6c430740b6aa9cd4e3ae38e469", "parents": [ "90d61cd1e36634597a71b86fcb9701b94741a553" ], "author": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Fri Feb 16 12:29:16 2024 +0530" }, "committer": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Fri Feb 16 15:03:53 2024 +0530" }, "message": "refactor(xilinx): mark ttc clock select platform specific\n\nTTC clock select register(TTC_CLK_SEL) is used to select\nTTC reference clock.\nThe offset for TTC_CLK_SEL in LPD_IOU_SLCR register module\ndiffers on various AMD xilinx platforms.\nOffset is 0x380 for zynqmp platform and is 0x360 for versal\nand versal-net platforms.\nAccording define offset for TTC clock select in platform\nspecific files.\n\nChange-Id: I479f655704fcc515068425eedc5d73d24a32dde0\nSigned-off-by: Amit Nagal \u003camit.nagal@amd.com\u003e\n" }, { "commit": "8cea7c5af9c2a300c4f5d143480d04c84cd5b21b", "tree": "57c461b3762b34758df91774cbbcec09e0eb4e27", "parents": [ "a8deec5c0b51719b1f268e4f106c3a095a387074", "4f35ce6fcbb68fc1f2fb48df7f66ad0fd494a061" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Feb 15 16:57:40 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 15 16:57:40 2024 +0100" }, "message": "Merge \"tc: update UART base for TFTF\"" }, { "commit": "4f35ce6fcbb68fc1f2fb48df7f66ad0fd494a061", "tree": "18660e8c58860af4ed31186704b908c918c7201e", "parents": [ "1abd0d2332d79ef7e2889d648cd093bb90e10bf3" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jan 17 13:05:48 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Feb 13 15:14:34 2024 +0100" }, "message": "tc: update UART base for TFTF\n\nUpdated UART base for TFTF as per the TC memory map.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I98cf5318edcd793cf69ead5e940718e42f25e3c9\n" }, { "commit": "a08c7195558726a2c3abd3bf9167ff4deae7d9e1", "tree": "3701dcb74085676d356e05b92f201e2e6800860b", "parents": [ "9fd0a9a2342668fa12cf2b15bc83be907899b8a4" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Oct 18 17:49:32 2023 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Feb 07 17:03:56 2024 -0600" }, "message": "test: exercise DMA isolation for secure access to ns memory\n\nThis test helps to validate a scenario where a secure stream\nbelonging to Cactus SP accesses non-secure IPA space.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I8085f2974d53b9cec9b3ae4a17fd328607b76e2b\n" }, { "commit": "8ea96f636ebc984f6f69144a6b6ca1f84aa03900", "tree": "a069544769f52840ff5d0a018bdde6a8da45a23b", "parents": [ "0137d4b08486ebb979ff0dfa5a41f25ef422f933" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Mon Feb 05 14:10:53 2024 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Tue Feb 06 15:58:49 2024 +0530" }, "message": "feat(versal-net): remove TSP tests from skip list\n\nAll of these tests are passing on the target, so removing\nthem from the skip list.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: Ieaba2634f0501e3815c1d6ef1503a37908bcfcc1\n" }, { "commit": "0137d4b08486ebb979ff0dfa5a41f25ef422f933", "tree": "6a189e1e18e9e025a62f93f43aaac0babfef219e", "parents": [ "bca7a3ab0f23de5b4c135eb21fa4b80209d86118" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Thu Feb 01 09:55:56 2024 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Tue Feb 06 15:49:18 2024 +0530" }, "message": "fix(versal-net): correct core position function\n\nThe corrected calculation of core positions involves utilizing the\nlinear core and cluster IDs from an MPID register. The MPID register\ncomprises three affinity levels: Aff0 (bits 0 to 7), Aff1 (bits 8 to 15),\nand Aff2 (bits 16 to 23).\n\nIn the current implementation of platform_get_core_pos(), the function\nreads the MPIDR_AFF0_SHIFT (0 to 7 bits) for the core ID and\nMPIDR_AFF1_SHIFT (8 to 15 bits) for the cluster ID. For example, in\nthe output \"CPU #10 [MPID: 0x1020200],\" it incorrectly returns the\ncore position as 8 instead of the expected core position 10.\n\nIn the updated implementation of the platform_get_core_pos() function,\nthe core ID is determined by reading the bits corresponding to Affinity\nlevel 1 (MPIDR_AFF1_SHIFT), and the cluster ID is determined by reading\nthe bits corresponding to Affinity level 2 (MPIDR_AFF2_SHIFT).\n\nTo address this issue and obtain the correct core ID, it is necessary\nto read affinity level 1 bits. Additionally, affinity level 2 should\nbe read to determine the cluster ID. A check has been incorporated to\nverify the MT bit in MPIDR for enabled status, leading to a modification\nin cluster/core calculation. Additionally, it is necessary to define\nPLAT_MAX_PE_PER_CPU for the affinity test.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I07573e82908ec6f2404423d61639646d411502cd\n" }, { "commit": "0945e23153c06ed196756ac094c81ab8627d9a95", "tree": "7bc1e57bb77a4cf09cf18b75974e18e60711da53", "parents": [ "8f6b131f44bf5355d07b274f6a43490f968590b2", "16de81046dbffdfc19ca4a30524f170860eac178" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jan 31 08:48:35 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 31 08:48:35 2024 +0100" }, "message": "Merge \"test(fvp): Test trusted key certificate corruption\"" }, { "commit": "16de81046dbffdfc19ca4a30524f170860eac178", "tree": "d70655f6090cd2e8befdae3a8270682f19f551ba", "parents": [ "84ad6157a4e83834fa925b80534ca5414c368586" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Fri Aug 18 08:50:30 2023 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Mon Jan 29 13:10:08 2024 -0600" }, "message": "test(fvp): Test trusted key certificate corruption\n\nThis also includes a test framework for use with corrupting the\nroot of trust private key certificate in the boot FIP, found\nusing its UUID.\n\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\nChange-Id: I988c517637edcf6fdcaf271628eb650781c276f8\n" }, { "commit": "dbb6634fa8a3b32c377db68d3e4de2ca99bcaf7f", "tree": "26adad399deaa5a5e4bd37ade4c43c511a01884a", "parents": [ "6eec0b422131e94e9c602e5560a432b36b97f703" ], "author": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Thu Jan 18 06:25:52 2024 +0000" }, "committer": { "name": "Akshay Belsare", "email": "Akshay.Belsare@amd.com", "time": "Mon Jan 22 11:06:27 2024 +0100" }, "message": "fix(xilinx): update test skip list\n\nUnexpected errors are observed from the firmware for some test suites\ndue to conflict of SMC ID from those and SiP service SMC IDs.\n\nAdding the tests suites to the test skip list.\n\nChange-Id: I1e77fe4d12223f93bd335e3d7c438ef6bd374712\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\n" }, { "commit": "5a559420694267ecdb1e1287f54cd4a7fa00d27b", "tree": "c22f57e2473e4a019c82e6c4fb84e3b340c7e8ea", "parents": [ "b28d63d4197acf7915d8ea4ea0133ac2e929242b" ], "author": { "name": "Thomas Abraham", "email": "thomas.abraham@arm.com", "time": "Tue Dec 05 16:58:44 2023 +0000" }, "committer": { "name": "Thomas Abraham", "email": "thomas.abraham@arm.com", "time": "Tue Dec 05 17:18:14 2023 +0000" }, "message": "plat/sgi: increase number of xlat tables\n\nWith the recent updates, the SGI based platforms require a higher number\nof xlat tables. So update MAX_XLAT_TABLES macro accordingly.\n\nSigned-off-by: Thomas Abraham \u003cthomas.abraham@arm.com\u003e\nChange-Id: I0d2b16a6ceffc09a37b7f67ad519c28648dc0383\n" }, { "commit": "8c6982bef75f048d54eff99f14949f7cef3eacd8", "tree": "86c0e783a5ef4147019628e69440d27347869706", "parents": [ "9875fcb039695a67a69a1646fb3db23d0363898c" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Wed Nov 29 09:05:24 2023 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Wed Nov 29 09:07:12 2023 +0530" }, "message": "fix(versal-net): skip hanging TSP test cases\n\nThis fix temporarily disables the hanging TSP test cases for Versal\nNET until a resolution is found for the ERROR_EVENT_WAKEUP issue.\nThis decision ensures the system\u0027s optimal operation by avoiding\nunnecessary power-up attempts.\n\nTests that are skipped:\n\nIRQ support in TSP/Resume preempted STD SMC\nIRQ support in TSP/Resume preempted STD SMC from other CPUs\nIRQ support in TSP/Resume preempted STD SMC after PSCI CPU OFF/ON cycle\nIRQ support in TSP/Resume preempted STD SMC after PSCI SYSTEM SUSPEND\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: Id0c6d0b06c691d29e7b80f559e79bc983c861407\n" }, { "commit": "9875fcb039695a67a69a1646fb3db23d0363898c", "tree": "4e80f86ef33ec057ee1871b0dd6df0ebec6127c0", "parents": [ "42b99719d5dde58bdde07712bcb70a20d87f9067" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Tue Nov 28 14:52:46 2023 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Tue Nov 28 15:35:02 2023 +0530" }, "message": "fix(versal): skip hanging TSP test cases\n\nThis fix temporarily disables the hanging TSP test cases for Versal\nuntil a resolution is found for the ERROR_EVENT_WAKEUP issue. This\ndecision ensures the system\u0027s optimal operation by avoiding\nunnecessary power-up attempts.\n\nTests that are skipped:\n\nIRQ support in TSP/Resume preempted STD SMC\nIRQ support in TSP/Resume preempted STD SMC after PSCI CPU OFF/ON cycle\nIRQ support in TSP/Resume preempted STD SMC after PSCI SYSTEM SUSPEND\nTSP PSTATE test\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: Ib65599a083b8fa61e8cc9dcf3672abacd83875c3\n" }, { "commit": "6e5c99643b199e064f1e8090d963671965ced1d7", "tree": "c5079b4d7de61ed810e5241021b5005d35990ba7", "parents": [ "92b99ee435ebafa5e503b19dce753079ad35218d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Oct 06 16:38:13 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 10 14:31:18 2023 +0100" }, "message": "fix(rme): append realm.bin at end of tftf.bin\n\nCurrently realm.bin is appended to tftf.bin at offset of 10 MB.\nThis patch removes this dependency by reserving empty sections\nfor realm image and dependencies, in tftf binary after\nall loadable sections (end of binary),\nand append realm.bin at end of tftf.bin later in build process.\n\nThe patch removes the need for TFTF to map memory corresponding\nto Realm payload dynamically at runtime.\n\nChange-Id: Iead2dc62ff2965cf7bb03e61c93e76df218da973\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "1d8f2222855d4bf5c6dac48c43d66560324a04b0", "tree": "eab8162b1127b3dd6caee080a2808e86dcc0d4a9", "parents": [ "56f41cda007f73b997b687498b7f09fc72d262c6" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Aug 25 12:02:33 2023 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Tue Sep 05 10:29:01 2023 +0530" }, "message": "chore(xilinx): reorganize timer code into common path\n\nReorganized timer code into common folder, updated paths in\nplatform.mk and Versal/Versal NET ttc timer irq in platform_def.h for\nXilinx project.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I504727f55099decf07a208fc95254597e6e24902\n" }, { "commit": "56f41cda007f73b997b687498b7f09fc72d262c6", "tree": "7fe3036ca8fc2943663ed1d5f7389804d28f119c", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Aug 25 11:59:30 2023 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Mon Sep 04 12:01:34 2023 +0530" }, "message": "feat(versal-net): introduce platform support\n\nIntroduce platform support for AMD-Xilinx Versal NET, an adaptive\ncompute acceleration platform (ACAP). The Versal NET is designed to\noffer a wide range of compute, acceleration, and connectivity\noptions, including high-speed networking interfaces.\n\n- pl011 is used for console.\n- TTC is used for Timers.\n- NVM is not supported.\n\nFor Versal devices with 1 cluster and 2 cores, the SCNTR and SCNTRS\nregisters are not accessible from NS EL1, so we are using TTC timers\ninstead.\n\nFor Versal NET devices with 4 clusters and 4 cores per cluster, the\nSCNTR and SCNTRS registers are not accessible from NS EL1, so we\nare using TTC timers instead.\n\nsummary:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 128\nTests Passed : 34\nTests Failed : 7\nTests Crashed : 0\nTotal tests : 169\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nNOTICE: Exiting tests.\n\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I80e76d9f898f5ebca91a403ff802857ea70d7868\n" }, { "commit": "52aefd94f5b047e40c6c7902415cc6ae48688d8e", "tree": "a769e8e2eeed65f0261fb6e8a674e03c55d28e4e", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Tue Apr 04 10:26:40 2023 +0530" }, "committer": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Thu Jul 27 22:57:37 2023 +0530" }, "message": "feat(versal): introduce platform support\n\nIntroduce platform support for AMD-Xilinx Versal, an adaptive compute\nacceleration platform (ACAP).\n- pl011 is used for console.\n- TTC is used for Timers.\n- NVM is not supported.\n\nWatchdog timer support to come in another change\n\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 172\nTests Passed : 38\nTests Failed : 5\nTests Crashed : 0\nTotal tests : 215\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nSigned-off-by: Michal Simek \u003cmichal.simek@amd.com\u003e\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nChange-Id: If358a8018f4106d2267b6bed8eadbfdbaa48ad39\n" }, { "commit": "c19215adf93502c19c766f5b621051b3398fac05", "tree": "3f8d7037f4b9636ee16f9b7139a8b3e5dc9a7ac1", "parents": [ "35d5fe4ad5242d69d8911b57a842a77ec69f0dfa" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed May 17 13:50:36 2023 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Thu Jun 22 15:10:20 2023 +0100" }, "message": "refactor(tc): Make tc0 tftf code generic to tc.\n\nThis code can be used for tc0, tc1 and tc2 testing so change from\ntc0 naming to tc.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ied011db0cd688936d6ba20e48c5206de4891e732\n" }, { "commit": "ae1bd6f29d62f0b0b3bdc637a7b80d776220cb33", "tree": "cbfcf151e985e83a2168144c3458f6d3f3eeb129", "parents": [ "dd2d2228c3c6867b1b29d9b0a4323685980e4093" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 12 11:42:21 2023 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 12 12:02:35 2023 +0100" }, "message": "Revert \"test(interrupts): add tests for interrupt routing\"\n\nThis reverts commit 353a6cebde2586a866142f7dfbc6b8df644d03cd.\n\nReverting due to failure in Arm internal RMM CI which stops tagging of\nrc0 for v2.9 release, Once the proper fix is found it will be taken\nback either in next tag or after v2.9 release.\n\nFailure log:\nSMC_RMM_VERSION \u003e 380000\nRMM version is: 56.0\n\u003e Executing \u0027Realm payload multi CPU request\u0027\nSMC_RMM_VERSION \u003e 380000\nINFO: Booting\nSMC_RMM_VERSION \u003e 380000\nINFO: Powering off\nINFO: Booting\nSMC_RMM_VERSION \u003e 380000\nINFO: Powering off\nINFO: Booting\nSMC_RMM_VERSION \u003e 380000\nINFO: Powering off\nINFO: Booting\nSMC_RMM_VERSION \u003e 380000\nINFO: Powering off\nSMC_RMM_VERSION \u003e 380000\nINFO: Powering off\nINFO: Booting\nSMC_RMM_VERSION \u003e 380000\nINFO: Powering off\nERROR: Error: fffffffa\nPANIC in file: spm/cactus/cactus_main.c line: 108\n\nChange-Id: Id5179deb5324c1bd2fac41c7a030bf7e09a1c222\n" }, { "commit": "353a6cebde2586a866142f7dfbc6b8df644d03cd", "tree": "c498aead8680c2807f0a716c681ced2f9f011cfb", "parents": [ "c61a188e932400ab599e0a4d4b07c2df532f3590" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Mon Jan 16 19:44:03 2023 -0800" }, "committer": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Wed May 10 15:21:18 2023 -0700" }, "message": "test(interrupts): add tests for interrupt routing\n\nThis patch modifies existing secure interrupt tests to test interrupt\nrouting to particular cores/mpidr. Hafnium added a new field\n\"interrupts-target\" to enable targeting interrupts to cores that are NOT\nthe boot core. This change modifies the cactus manifest to target the\nsecure watchdog timer (existing secure interrupt on fvp) to a particular\nmpidr. To test interrupt handling, it converts the existing tests that\nuse the secure watchdog timer to test interrupt handling, to multi\ncore tests, such that the same test runs on the appropriate mpidr as\nopposed to the boot core. Since the interrupt may be targeted to a\nsecondary PE, the corresponding secondary vcpus of cactus need a round\nof ffa_run to function, which has also been added.\nThe mpidr to target to is platform specific and is defined as a platform\nspecific macro.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nChange-Id: I27f48cde68945e59fb2ce84625ca145048eaffd1\n" }, { "commit": "cbd8989c93c56bd992cf4998226ed6b247d32954", "tree": "8b1bbbce2ce2ae4c59c8af1b249c96bd3435e42b", "parents": [ "83fe74900c440b2728c458efd8b1c57be20ba039" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Feb 17 14:56:02 2023 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon May 08 08:41:38 2023 -0500" }, "message": "test: group0 interrupt triggers while VM/SP is running\n\nThis patch introduces two tests for TC platform to ensure the\nplatform firmware handles Group0 secure interrupt and resumes the\nexecution of preempted endpoint context(a VM in normal world as well\nas an SP in secure world).\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I8c4b23497eab143773dd7ab9372a05760ce78881\n" }, { "commit": "cb88add07daff59486f850be6b4cd4750f94d97c", "tree": "3737ad2a8a2aa4c4d9e8d4eea54720009ca4e94a", "parents": [ "e0400c6d2b0372d742cd2cda9aaa7c5cf4741c4a" ], "author": { "name": "Wing Li", "email": "wingers@google.com", "time": "Sat Oct 29 02:32:06 2022 +0100" }, "committer": { "name": "Wing Li", "email": "wingers@google.com", "time": "Thu Mar 23 19:37:52 2023 -0700" }, "message": "test(psci): add tests for OS-initiated mode\n\nChange-Id: I33e135f659aea600f71e053ac3db57eb0172e22b\nSigned-off-by: Wing Li \u003cwingers@google.com\u003e\n" }, { "commit": "5c71203a7f4cbfb837fe797a9b6a66f97af8b567", "tree": "1b6177e33f5ccd511885cf438093c82f2842fbdc", "parents": [ "3fd89ac55081501979d9f5c6d338783a6899eb2e" ], "author": { "name": "Tony K Nadackal", "email": "tony.nadackal@arm.com", "time": "Wed Jan 11 18:22:31 2023 +0000" }, "committer": { "name": "Tony K Nadackal", "email": "tony.nadackal@arm.com", "time": "Wed Jan 11 18:22:31 2023 +0000" }, "message": "feat(rdn2cfg3): add tftf support\n\nAdd tftf support for Neoverse Reference Design RD-N2-Cfg3 platform. It\nis a variant of RD-N2 platform with a 10x6 mesh. For this platform, the\nPLATFORM_VARIANT macro should be set to 3 at compile time.\n\nSigned-off-by: Tony K Nadackal \u003ctony.nadackal@arm.com\u003e\nChange-Id: I67cd441586c1e437d816cedd086d55f2b5c85718\n" }, { "commit": "309d95eb37808ee136e42015f81690cd5c8972bf", "tree": "030c50b66bc0700c176aa0cf6c6fc45ae59280c2", "parents": [ "b68713efb9b143ba878af18aff5c65bfa28ad8fe" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Dec 05 12:22:00 2022 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Dec 08 09:58:01 2022 +0100" }, "message": "refactor: add new test-suite \u0027tests-timer-stress\u0027\n\nMoved \u0027Stress test timer framework\u0027 as part of \u0027tests-extensive\u0027 suite\nby creating a separate test suite for timers, i.e. tests-timer-stress.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: Ibdad88e81fba55333c0ad17cc9c10d24d97e6c7e\n" }, { "commit": "002e569021f2e219456d02dfe239218eba5c7cfa", "tree": "4c2ea2d7cce38d168ce5e03849498161d537f1c2", "parents": [ "0fcfd47a5936180b754819ee928e8d5af173c5d2" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Mon Oct 10 12:36:46 2022 +0100" }, "committer": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Tue Nov 08 16:34:01 2022 +0000" }, "message": "feat: tftf realm extension\n\nThis patch adds Realm payload management capabilities to TFTF\nto act as a NS Host, it includes creation and destruction of a Realm,\nmapping of protected data and creation of all needed RTT levels,\nsharing of NS memory buffer from Host to Realm by mapping of\nunprotected IPA, create REC and auxiliary granules, exit Realm\nusing RSI_HOST_CALL ABI.\n\nOlder realm_payload name is used now for only R-EL1 test cases,\nRMI and SPM test cases have been moved to new file tests-rmi-spm.\n\nNew TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk,\nas an offset from where R-EL1 payload memory resources start.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7\n" }, { "commit": "6824dadc23f97d06620999e781e1d3f31f28743a", "tree": "e28e9bf4917c395902b1fd19d5a33552a042babd", "parents": [ "46aa2bbb093847247c2c3cca8aaafe1b8a123868" ], "author": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Wed Feb 23 20:34:45 2022 +0530" }, "committer": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Fri Sep 23 15:15:33 2022 +0530" }, "message": "feat(rdn2cfg1): add tftf support\n\nAdd tftf support for Neoverse Reference Design RD-N2-Cfg1 platform.\n\nSigned-off-by: Shriram K \u003cshriram.k@arm.com\u003e\nChange-Id: I0d9287a50f8e1867e42bc0b0f29e94e9274f5eca\n" }, { "commit": "46aa2bbb093847247c2c3cca8aaafe1b8a123868", "tree": "9bdbb81da568ce0d00a9687df49613cb72218f17", "parents": [ "d46943dafd3b240972fd85642c2c2593be49c912" ], "author": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Thu Sep 15 16:11:13 2022 +0530" }, "committer": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Fri Sep 23 09:21:36 2022 +0530" }, "message": "feat(rdn2): add support for tftf\n\nAdd tftf support for Neoverse Reference Design RD-N2 platform. The RD-N2\nplatform includes 16 Neoverse N2 CPUs, CMN-700 interconnect, GIC-700 and\nSMMU-700.\n\nSigned-off-by: Shriram K \u003cshriram.k@arm.com\u003e\nChange-Id: I48802aa6b02bb14d399a61b7c9008572db6d52fc\n" }, { "commit": "d46943dafd3b240972fd85642c2c2593be49c912", "tree": "d6e20d3cc43cfe1e7bb2b9cc5209db666ee2299c", "parents": [ "4bd6db742766e167e30b0e4878625f8f3aec0224" ], "author": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Thu Sep 15 16:03:33 2022 +0530" }, "committer": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Fri Sep 23 09:21:36 2022 +0530" }, "message": "feat(rdv1): add support for tftf\n\nAdd tftf support for Neoverse Reference Design RD-V1 platform. The RD-V1\nplatform includes 16 Neoverse V1 CPUs, CMN-650 interconnect, GIC-700 and\nSMMU-600.\n\nSigned-off-by: Shriram K \u003cshriram.k@arm.com\u003e\nChange-Id: I2ae41cb99cf1ed5560eafb8c6c7876f0adec2146\n" }, { "commit": "4bd6db742766e167e30b0e4878625f8f3aec0224", "tree": "53f239ee421a0410a710b800755b2116c95e0e9f", "parents": [ "e10a50814c4963f3e17104808da4d5e28f99262d" ], "author": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Sun Sep 18 22:19:54 2022 +0530" }, "committer": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Fri Sep 23 09:21:36 2022 +0530" }, "message": "feat(plat/sgi): introduce platform variant build option\n\nNeoverse reference design platforms can have two or more variants that\ndiffer in core count, cluster count or other peripherals. To allow reuse\nof platform code across all the variants of a platform, introduce build\noption CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design\nplatforms. The range of allowed values for the build option is platform\nspecific.\n\nSigned-off-by: Shriram K \u003cshriram.k@arm.com\u003e\nChange-Id: I4559527987ee87f0f75a84f905746b1e430a2a53\n" }, { "commit": "e10a50814c4963f3e17104808da4d5e28f99262d", "tree": "445a9639acbf4dce4d3eccdab4607b585e5bd711", "parents": [ "8687985f6fbc4f67c7396050d360b2037e1fcf67" ], "author": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Thu Aug 12 20:09:22 2021 +0530" }, "committer": { "name": "Shriram K", "email": "shriram.k@arm.com", "time": "Fri Sep 23 09:21:36 2022 +0530" }, "message": "refactor(plat/sgi): header files and macros\n\nIn preparation to add support for the latest Neoverse reference design\nplatforms, reorganize the header files to allow newer platforms to use a\ndifferent set of platform macros. In addition to this, rename the macros\nto match the names used in trusted firmware.\n\nSigned-off-by: Shriram K \u003cshriram.k@arm.com\u003e\nChange-Id: Ic21601730650d59ed8e40f763a0d5c4a5c45d3a3\n" }, { "commit": "f38f2883814e5a6783380dd84d14a2fe0b052ead", "tree": "75fa930d442e9d8903a651be17719061df9a76e3", "parents": [ "9946e97b88141cfa9cb8c559a109ed7e64740255" ], "author": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Tue Mar 22 15:42:09 2022 +0000" }, "committer": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Tue Jun 21 23:37:06 2022 +0100" }, "message": "feat(sgi): route tftf logs via secure uart\n\nFor neoverse reference design platforms, migrate to secure uart port\nfor routing tftf logs.\n\nSigned-off-by: Rohit Mathew \u003crohit.mathew@arm.com\u003e\nChange-Id: I5d48b1cd96fd50e9187ef07d369133f18b81f3fb\n" }, { "commit": "9946e97b88141cfa9cb8c559a109ed7e64740255", "tree": "d38ff0cfe386f3f205cdac9e989aec5e83e2482f", "parents": [ "756f24d71e60996470f6bed35c9293820720871a", "728cc567116e03673f4a03b00c448580c9f82158" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jun 15 15:58:04 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 15 15:58:04 2022 +0200" }, "message": "Merge \"fix: NS buffer (48b PA) memory sharing between SPs\"" }, { "commit": "7454e820ca6736baa599e43ba0ea42fe2e0bada9", "tree": "ab5a2054f5c0569b819e1fe37bc8af9ee3560cb9", "parents": [ "fb242e3ab407f43f61c73fdc7ffbce9afd850e6c" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Apr 07 15:43:35 2022 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jun 13 11:43:18 2022 -0500" }, "message": "plat(n1sdp): initial commit of N1SDP platform port\n\nThis patch allows TFTF to run on N1SDP in a limited manner and is still in\ndevelopment, some tests are disabled using the file\nplat/arm/n1sdp/tests_to_skip.txt.\n\nThe major known issue now is with PSCI commands waking up and powering\ndown cores, and SGIs do not wake up powered off cores.\n\nBuild command: \"make CROSS_COMPILE\u003daarch64-none-elf- PLAT\u003dn1sdp tftf\"\n\nTo run TFTF on N1SDP, copy tftf.bin to the /SOFTWARE directory on the SD\ncard and edit the images.txt file to load tftf.bin instead of uefi.bin.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I897ba665306413c594544d6a231555475e7c8111\n" }, { "commit": "728cc567116e03673f4a03b00c448580c9f82158", "tree": "8ce7019e77285e195565d67b0e2d907b1c2ac4ec", "parents": [ "5f591f67738a1bbe6b262c53d9dad46ed8bbcd67" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jun 09 11:37:46 2022 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jun 09 14:40:07 2022 +0200" }, "message": "fix: NS buffer (48b PA) memory sharing between SPs\n\nFix [1] by increasing cactus number of xlat tables.\nThis permits running the SP SP mem sharing of a buffer located at a\nhigh physical PA region.\nTest config [2] provides the model parameters to configurare the PE,\ninterconnect and SMMU to handle 48b physical address size.\n\n[1] https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/13599\n[2] https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/15445\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ia290f15a6d30c898a5219d2bc1c3949b6ae7e7ef\n" }, { "commit": "c2d5a9149e23fe822c84958b3121b67b064bf18a", "tree": "4a0a90e7be083f5eb4047d534a78de1dd44bc1a0", "parents": [ "207353c0107bf9cad58ab50b7b1d52fee3b5494f" ], "author": { "name": "Anthony Zhou", "email": "anzhou@nvidia.com", "time": "Fri Apr 22 20:07:15 2022 +0800" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon May 23 11:36:23 2022 +0200" }, "message": "Tegra: introduce IRQ_TWDOG_INTID macro\n\nThis patch introduce macro IRQ_TWDOG_INTID for the Tegra210, Tegra186\nTegra194 platforms to fix the compilation failures.\n\nChange-Id: Ifaf280d7938a720689418362b09ba5f3ba5decb2\nSigned-off-by: Anthony Zhou \u003canzhou@nvidia.com\u003e\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\n" }, { "commit": "bf00f8d659be9c285ea9465e0f50fec3aca7acc2", "tree": "cd947b9dc82976d613cfd43906e80f8ce3c991d5", "parents": [ "d5c67b889678d4e05ab4c43c590e11aa8b58e7f0" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Tue Mar 22 12:37:19 2022 +0000" }, "committer": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Wed May 18 15:06:17 2022 +0100" }, "message": "test(tftf): prevent secure region access from nwd\n\nThis change adds a TFTF test attempting an access to a memory region\nmarked Secure in the GPT. It is expected this results in a GPF data\nabort being caught on the PE.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: I016775e6a8ba7b398c5770c0a296c09898ebd706\n" }, { "commit": "7f660cbe5f04cf86ebe4dd09c6316634972d0934", "tree": "fcd3d939556d58bd3ced3a2e2fbd9d633cc218f9", "parents": [ "39054c3002cf0a7fa52c9b8a24813c10ad1212e9" ], "author": { "name": "Vishnu Banavath", "email": "vishnu.banavath@arm.com", "time": "Wed Apr 06 16:30:01 2022 +0100" }, "committer": { "name": "Vishnu", "email": "vishnu.banavath@arm.com", "time": "Thu Apr 28 17:42:43 2022 +0200" }, "message": "feat(plat/arm): add corstone1000 platform support\n\nThese changes are to add corstone1000 platform support\n\nSigned-off-by: Vishnu Banavath \u003cvishnu.banavath@arm.com\u003e\nChange-Id: I1a61539326b595faadcf919da24699cd8e4c3a41\n" }, { "commit": "d3749b08d49a6cb4fd69e66da1e405dbbd3de57f", "tree": "ba6fa7fa5bbf622dd54281668f885ceaa9091f53", "parents": [ "0091af97592d9cd036a4b70433b70ac9c0ed22b0" ], "author": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Fri Jan 14 15:44:45 2022 +0100" }, "committer": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Fri Mar 25 10:54:00 2022 +0100" }, "message": "fix(plat/arm/fvp): make address space configurable\n\nMake FVP physical/virtual address space sizes configurable, with\ndefault at 34-bit (previously hard-coded value).\nMaximum tested value is 48-bit, FVP interconnect doesn\u0027t yet support\n52-bit PA.\nIncrease MAX_XLAT_TABLE and consequently NS_BL1U_RW_SIZE and\nNS_BLU2_LIMIT to accommodate the increased translation tables (based\non 48-bit max PA size).\n\nCustom PA size is passed to build system through the PA_SIZE define.\n\nFVP needs to be configured in a compatible way through the parameters:\n* cluster0.PA_SIZE, for each cluster;\n* bp.dram_size, setting a memory limit corresponding at least to\n PA_SIZE;\n* cci550.addr_width, interconnect address width should match PA_SIZE;\n* pci.pci_smmuv3.mmu.SMMU_IDR5, SMMU has to be configured as well if\n present.\n\nChange-Id: I57bc898fb2c9696c01fc8e20d00b4a3d09e22326\nSigned-off-by: Federico Recanati \u003cfederico.recanati@arm.com\u003e\n" }, { "commit": "76f873bac83f6e17a2ce1ad0c94e963b9abff330", "tree": "947630ef40cfb74f36ebc533b16159fbb9d37a55", "parents": [ "6888feeb8e873b311b19b805990e3b2f25f7becf" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Mar 08 21:18:31 2022 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Mar 08 21:18:31 2022 +0000" }, "message": "fix(tftf): do not map EL3 memory in EL2 statically\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I9cc1ed29316fe3140e4a390ffbd279f9dbfedbae\n" }, { "commit": "572ee4fde07faf8c208ebfd1bcaf745a93db003d", "tree": "f2a2755cc1937255fcd11b3c89b7adfce965b9c7", "parents": [ "5f513d692006ac52b8cb87fe91cbfb002dd98e13" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jan 25 14:26:12 2022 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Mar 01 17:46:55 2022 +0000" }, "message": "feat(fvp): enable test to access el3 memory\n\nWith newly introduced test to perform invalid accesses requires platform\nto provide test memory addresses. This patch provides EL3 memory access\naddress for FVP platform.\nThe invalid_access test will try to access el3 owned memory from\ntftf(ns-el2).\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I9c9493f1b33bdd91d8d4140cf9e96b2d9007fbe2\n" }, { "commit": "c852a00195d78b2fe1729b7dd0c452e1ec1732dc", "tree": "0035d1f52a5b582f683ef2bae34b5d36cadf1738", "parents": [ "ab4b6d10d7ae5a765d7056b0a05c211b4c0220de" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Nov 23 11:51:23 2021 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Dec 06 13:56:43 2021 -0600" }, "message": "fix(tc): add notification support in tertiary SP manifest\n\nMoreover, FF-A interrupt tests are skipped for TC platform as\nit does not support TWDOG module needed for test scenario.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I63f274047bfbeed4a5ef096fe741368e253a4a77\n" }, { "commit": "d3fc83cf466c00208056896a3082597b22b8e42c", "tree": "66307fec6d848c2b8139ab246edc69ccb07fa91a", "parents": [ "ab9be20113f6512ad5ecac40a8ffc727d83a67d0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Nov 09 10:04:33 2021 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Nov 10 09:34:44 2021 -0600" }, "message": "fix(plat/arm): exclude FF-A v1.1 secure interrupt tests\n\nExcluded tests are not run but are still built. Specify TWDOG\nparameters for Arm Reference platforms to avoid below compilation\nerrors.\n\nThis is only a temporary fix. These platforms do not have SP805 IP.\nThey implement Generic Watchdog IP.\n\ntftf/tests/runtime_services/secure_service/test_ffa_secure_interrupts.c:29:50: error: \u0027IRQ_TWDOG_INTID\u0027 undeclared (first use in this function)\n 29 | ret_values \u003d cactus_interrupt_cmd(source, dest, IRQ_TWDOG_INTID,\n | ^~~~~~~~~~~~~~~\ntftf/tests/runtime_services/secure_service/test_ffa_secure_interrupts.c:29:50: note: each undeclared identifier is reported only once for each function it appears in\nmake: *** [Makefile:512: build/rdn1edge/debug/tftf/test_ffa_secure_interrupts.o] Error 1\n\ndrivers/arm/sp805/sp805.c: In function \u0027sp805_twdog_start\u0027:\ndrivers/arm/sp805/sp805.c:172:20: error: \u0027SP805_TWDOG_BASE\u0027 undeclared (first use in this function); did you mean \u0027SP805_WDOG_BASE\u0027?\n 172 | sp805_wdog_start_(SP805_TWDOG_BASE, wdog_cycles);\n | ^~~~~~~~~~~~~~~~\n | SP805_WDOG_BASE\ndrivers/arm/sp805/sp805.c:172:20: note: each undeclared identifier is reported only once for each function it appears in\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ic1e549716dd6aea4d794b964a76c402bf71a6179\n" }, { "commit": "dd7db24aaf872571b630b46add1995b3bec1b6fd", "tree": "cb1f1db984b5e8051cfdc084aee5c449c895fbcd", "parents": [ "f0c8a8853c373e046d14ab629e0ea50066df92e7" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Aug 05 14:14:15 2021 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Nov 05 15:35:57 2021 -0500" }, "message": "feat: add support for SP805 Trusted watchdog module helper APIs\n\nWe leverage this module to generate secure interrupts which we\nplan to use for exercising secure interrupt handling support in\nSPM(Hafnium) in co-ordination with Cactus SP\n\nCorrespondingly, a device region node is added to the Cactus primary\nSP manifest which captures the base address as well as other related\nproperties such as interrupts.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I410fdf926a23bd438e9899320f43a77e3697bc91\n" }, { "commit": "0b7d25f4add710ba13f4f46c54f8fe23a01ed053", "tree": "784c6ebed5eae93c7a73201097165bc2f44e6a4c", "parents": [ "1e65e855cf232560f37e64aefa75afb5239e5403" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Fri Mar 05 13:46:42 2021 +0000" }, "committer": { "name": "Maksims Svecovs", "email": "maksims.svecovs@arm.com", "time": "Thu Jul 15 16:40:22 2021 +0100" }, "message": "refactor(ff-a): partition info test functions\n\nMove common ffa_partition_info_get functions to the spm_common.\nSecure test target now supports both sending and receiving direct\nmessages.\nChanges in SP manifests to align with a new messaging method\nrepresentation in partition manifests.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: I9f6f24d6b800283a07e84a2a27708c0313b68fdc\n" }, { "commit": "1e65e855cf232560f37e64aefa75afb5239e5403", "tree": "c1082c004d480ada72179d1fd0c0ebc676bcf914", "parents": [ "d6715f10725c9e20bbca027681bcefc78208899e", "88c5345e4dec92eddd045ced4a2c437e5a197455" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Jun 30 14:54:19 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 30 14:54:19 2021 +0200" }, "message": "Merge changes from topic \"tc0_tfa_v25\"\n\n* changes:\n plat: tc0: enable managed exit for primary cactus\n plat: tc0: set PLAT_CACTUS_CORE_COUNT, disable SMMUv3 tests\n plat: tc0: Update GICR base address\n" }, { "commit": "9682b7739c9dcd7d4baa2a638127ae3994709a58", "tree": "1082ef176b86ec302e078d810088860dbbc3ec32", "parents": [ "3f6e1ec4d09d2a4b3999eab24e1a0f3baf97e7bb" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon May 24 11:08:40 2021 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 21 12:25:44 2021 +0100" }, "message": "plat: tc0: set PLAT_CACTUS_CORE_COUNT, disable SMMUv3 tests\n\nDefine platform specific SMMUv3 test driver macros. These macros will\nbe set to proper values once SMMUv3 is enabled for TC platform.\n\nDisables SMMUv3 tests.\nEnables PSCI NODE_HW_STATE API test.\n\nChange-Id: I1bd0f362521d892d4b33a2188bf8c5065c45d6f0\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\n" }, { "commit": "3f6e1ec4d09d2a4b3999eab24e1a0f3baf97e7bb", "tree": "ab841d9d9d64e87659471107b36aa03c2dc12db4", "parents": [ "e3cfd6df27e46c17f514baab275f0a6209aecb44" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon May 24 14:49:24 2021 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 21 12:25:44 2021 +0100" }, "message": "plat: tc0: Update GICR base address\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I336a815a722dfa387d5d9720ea9f22fedac55bbf\n" }, { "commit": "9f1952c9b7fe5b3f422e53bd7c1038fcd5764b2d", "tree": "bcfddb9641c785d3a5e00703e2cf586ab775619c", "parents": [ "08798acfce407339bc4433c095c6b3a5da31e12a" ], "author": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Mon Aug 24 11:32:32 2020 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jun 18 16:34:56 2021 +0100" }, "message": "SPM: Add shim layer to Ivy partition and enable PIE\n\nAdd a shim layer that runs at S-EL1 to the Ivy partition.\nAlso enable Ivy to be built with PIE.\n\nSigned-off-by: Ruari Phipps \u003cruari.phipps@arm.com\u003e\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: I821a8ac99d07200aec93ca29d182f8ab6716616c\n" }, { "commit": "172523b9ceadd0af9f6e8e4fb899cc7f354ff002", "tree": "ef3d02c2953b208aa5e1c84a23bc58a117f27e9a", "parents": [ "c5b60fce76bd56739c909fa0d5ac53d482171c88" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Dec 31 19:25:33 2020 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Apr 30 09:31:53 2021 -0500" }, "message": "Cactus test for exercising SMMUv3 driver to perform stage2 translation\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I498cb63aed497ab469a38e486a7943dd634e5b36\n" }, { "commit": "d1c81f964aacf818e1684b21ce039dcf58c41463", "tree": "73c27f50d2137dd826461428df98e4da5682c6ff", "parents": [ "424db295a8ee571efc92fc29c46ece28313c6b3d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Apr 28 14:59:25 2021 +0200" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Apr 28 14:59:25 2021 +0200" }, "message": "Revert \"Enable spurious test on Juno\"\n\nThis reverts commit 424db295a8ee571efc92fc29c46ece28313c6b3d.\n\nReason for revert: The test is unstable on Juno and intermittently fails.\n\nChange-Id: Id1b14068789a1219b1c2528e66690e7e5d8c6979\n" }, { "commit": "424db295a8ee571efc92fc29c46ece28313c6b3d", "tree": "36ea18dc01cbcf47a93a1d54cb717e2a31cf3a9e", "parents": [ "476ffb30f7e99b030bc4d257a41cb54cb6713087" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Sep 18 18:08:03 2020 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Apr 21 12:02:09 2021 -0500" }, "message": "Enable spurious test on Juno\n\nThe corresponding bug fix in tspd component of TF-A was merged\n\nhttps://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9011\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I2499f2ecef1c6f0a5687c66e67cfabc9f21bc6b0\n" }, { "commit": "6ddc37f73dc593504137d04d0c57f708d816254a", "tree": "3680dcf54950a002278246ebd5762d3c190c349e", "parents": [ "f353662d97dd0bde6abcced1d973fbe7c445521b" ], "author": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Sun Jan 17 18:05:08 2021 +0000" }, "committer": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Fri Jan 29 14:56:15 2021 +0000" }, "message": "plat/tc0: Change to 8 cores for Theodul\n\nThis includes changing to 8 cores for header file, dts\nand topology. The missing uart node is also added to\ncactus.dts.\n\nSigned-off-by: Usama Arif \u003cusama.arif@arm.com\u003e\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I1c70f9fd92273d7b5dc97875707e469d7f39c12d\n" }, { "commit": "4d0dcc8eec4e4d3d9f53b3f31afb062d160fd9aa", "tree": "eed301d98cbb89795c36c8c8016cf938d2292606", "parents": [ "79a4eaacf233b5049b05cd0f71a5d9a6dcd7f043" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Thu Jun 25 19:39:27 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Wed Oct 28 11:52:39 2020 -0700" }, "message": "Tegra210: introduce platform support\n\nThis patch introduces support for running TFTF on Tegra210\nplatforms.\n\nVerified with tftf-validation and psci test suites.\n\nVerified by: Anthony Zhou \u003canzhou@nvidia.com\u003e\nSigned-off-by: Anthony Zhou \u003canzhou@nvidia.com\u003e\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I48584d0b40142e7f49428b891a1d87a7db41c212\n" }, { "commit": "79a4eaacf233b5049b05cd0f71a5d9a6dcd7f043", "tree": "9ce3c57f643c136ca86f79da537ceb00bbec1ede", "parents": [ "8900d8ca6a36f4f675ec02bb98c28c940e40c631" ], "author": { "name": "anzhou", "email": "anzhou@nvidia.com", "time": "Tue Jul 14 22:30:54 2020 +0800" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Wed Oct 28 11:31:36 2020 -0700" }, "message": "Tegra: timer: define RTC irq number in each platform\n\nThe RTC irq number may be different for different platform.\nIntroduce new macro TEGRA_PLAT_RTC_IRQ to define the platform\nRTC irq number.\n\nSigned-off-by: anzhou \u003canzhou@nvidia.com\u003e\nChange-Id: I5b66b9720fb7fe9a71a5b800764635166da9f1ae\n" }, { "commit": "dbf8a2f79fcb10857cca95cf76c5102798c03286", "tree": "bc7eb60b941a2e105e2d74189b5d4648eaa02e14", "parents": [ "8d3ed011c68009b80ff94bb426378a1d6f06faee" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Tue Jun 23 08:13:57 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Wed Oct 28 11:30:55 2020 -0700" }, "message": "Tegra186: introduce platform support\n\nThis patch introduces initial support for Tegra186 platforms.\n\nVerified with tftf-validation.\n\n******************************* Summary *******************************\n\u003e Test suite \u0027Framework Validation\u0027\n Passed\n\u003e Test suite \u0027Timer framework Validation\u0027\n Passed\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 0\nTests Passed : 6\nTests Failed : 0\nTests Crashed : 0\nTotal tests : 6\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I9c68fce2cbc14592dbb2738adbeb64ec33e910e8\n" }, { "commit": "113d2d2f4be90ba060ccb994bbbed4ee429c820b", "tree": "3a710cd6f496a5da82f67d9582a7e427ceb50e41", "parents": [ "b3bcf77a65880049e40fa6f1b764a19dbd9faead" ], "author": { "name": "anzhou", "email": "anzhou@nvidia.com", "time": "Thu Jun 04 13:20:18 2020 +0800" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Wed Oct 28 09:00:18 2020 -0700" }, "message": "Tegra194: move drivers to common folder\n\nThe drivers: reset, timers. wake, watchdog can be used for\nother nvidia platforms. Move them to drivers and remove the\nt194 tag for the common functions and defines.\n\nSigned-off-by: anzhou \u003canzhou@nvidia.com\u003e\nChange-Id: I658341ccd5d7a0fe21e65291c8ed71f9ccc93e5d\n" } ], "next": "5884e2459faf4c0f803c5a63301f7f2d81eed21d" }