)]}'
{
  "log": [
    {
      "commit": "fe1c9b82b5ecc91778eada953135051a180b5237",
      "tree": "5c9df9ece7049e83dd728aa62d96de6c7a2122b2",
      "parents": [
        "bedd612ed9bc80d60dda50bddeb3823eb62bde21"
      ],
      "author": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Thu Oct 02 18:07:49 2025 +0100"
      },
      "committer": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Thu Oct 30 13:02:11 2025 +0000"
      },
      "message": "feat(planes): test SIMD access from plane N\n\nAdd tests to exercise access to SIMD functinality from Plane N.\nThe tests alternate execution of \u0027rdvl\u0027 instruction from Plane 0 and\nPlane N in different sequences and combinations of TRAP_SIMD values.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I55b9bf55b43b72419e8244f228c505a58c2a819c\n"
    },
    {
      "commit": "31f6f653bbc0eb6f2df84eb1fdb4574170bfba16",
      "tree": "0f58b61fa0d5a182ce062c876d70f8f385051b97",
      "parents": [
        "049b469008f0901d9aa75444f10f1c5bc195cc78"
      ],
      "author": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Tue Aug 05 18:20:55 2025 +0100"
      },
      "committer": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Fri Sep 12 17:58:28 2025 +0100"
      },
      "message": "fix(rme): RMM is not taking PSTATE into account on PN entry/exit\n\nPlane 0 is notified, through RsiPlaneExit.pstate field of RMM PSTATE\nupon plane N exit. Also, plane 0 needs to provide RMM PSTATE value upon\ncalling RsiPlaneEnter through RsiPlaneEnter.pstate value.\n\nThis patch implements that behavior on the existing tests for planes\nas it was not implemented before.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I45af6c5863af2d2b7cc92005e16b80b895639f07\n"
    },
    {
      "commit": "4a9ffd52277103082ea78d7873e5f5732ed6fdcc",
      "tree": "7465ab700d8557cd0027ccbfce37a9637ed1bcf8",
      "parents": [
        "63ea05bd16fceb7048ee625cae12394a3be5f15b"
      ],
      "author": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Thu May 22 14:45:48 2025 +0100"
      },
      "committer": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Wed Sep 10 13:18:57 2025 +0100"
      },
      "message": "feat(rme): uplift RSI_SYSREG_READ/WRITE tests to alp13\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Ia06872776d06655e0c0ceb6a48fca0e5aefac0b8\n"
    },
    {
      "commit": "aedca160ea2d648b6f46535a2cce9e4354d30e12",
      "tree": "3045a9a21bcaa2ca396fa7895796dcf5e295ecd8",
      "parents": [
        "73005a60253c98274a4a1104af0bf75ccca4d205"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Apr 21 16:39:06 2025 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Wed Jul 09 09:08:58 2025 +0000"
      },
      "message": "feat(realm_host_mgmt): support multiple devices in DA test\n\nConnect all off-chip pcie devices with TSM. This setup secure session,\nIDE and programs DVSEC RMEDA.\n\nHost assigns all devices that are connected with TSM to a Realm. And\nRealm locks and accepts the assigned device.\n\nThis patch adds host_da_workflow_on_all_offchip_devices testcase.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Id8ea54f9c9aad45787a0aac106a9260f68a63ec5\n"
    },
    {
      "commit": "08a5f16c322b75a5ed7a1b16da2bb2fc6755ca16",
      "tree": "148d48459acd68d174f5e4dfb7f33b0488a2b3b2",
      "parents": [
        "b8851a7ef8aca4385c42f63d74ac709456c8af1d"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Fri May 09 17:29:13 2025 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Fri Jun 13 17:57:03 2025 +0100"
      },
      "message": "chore(realm): rename rsi_ripas_respose_type to rsi_response_type\n\nRSI_RDEV_VALIDATE_MAPPING command\u0027s output value in X2 has RsiResponse\ntype. Rename \u0027rsi_ripas_respose_type\u0027 to \u0027rsi_response_type\u0027 and fix\ntypo.\n\nChange-Id: I7af258f67c6f18eed9443bfb922dad3a2fdfb0a9\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n"
    },
    {
      "commit": "b8851a7ef8aca4385c42f63d74ac709456c8af1d",
      "tree": "faa9bc10b3090fd1745b0190bfe8281e26065294",
      "parents": [
        "19ad61740ec71f886473c3f4d125ad062ce6c9f4"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Thu Apr 24 11:40:28 2025 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Fri Jun 13 17:57:03 2025 +0100"
      },
      "message": "chore(real_da): move realm DA support functions\n\nMove realm DA support functions from realm_da.c\nto realm_da_helpers.c.\n\nChange-Id: I53f3d8bbcaa77d5d17a9b435c0e0484af64adbd7\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n"
    },
    {
      "commit": "c58e4697c2df3d1b9d3a7d2e3da2294a13c27449",
      "tree": "8b0e4d94ab522130322b4a260f7114efa418abd4",
      "parents": [
        "51135c80730b1ce8faf30ee53a3797bdf342661c"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue Jan 28 12:28:59 2025 +0000"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Fri Jun 13 17:57:03 2025 +0100"
      },
      "message": "feat(realm): added support to invoke RSI RDEV ABIs\n\n- Updated DA RSI data types with RMM spec 1.1-alp11.1.\n- Added support to call DA RSI RDEV ABIs like\n  SMC_RSI_RDEV_CONTINUE\n  SMC_RSI_RDEV_STOP\n  SMC_RSI_RDEV_START\n  SMC_RSI_RDEV_GET_INTERFACE_REPORT\n  SMC_RSI_RDEV_LOCK\n  SMC_RSI_RDEV_GET_INFO\n  SMC_RSI_RDEV_GET_MEASUREMENTS\n  SMC_RSI_RDEV_GET_STATE\n  SMC_RSI_RDEV_GET_INSTANCE_ID\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I60664262c24f287637e91d53ecab0c8b980e58b7\n"
    },
    {
      "commit": "51135c80730b1ce8faf30ee53a3797bdf342661c",
      "tree": "b1f1864a8d8666ae08ca534bf3ea53f76e30c97e",
      "parents": [
        "c4ef92bd075d41d7d1ae03b9c5484881547946e7"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Jan 27 11:17:32 2025 +0000"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Fri Jun 13 16:53:10 2025 +0100"
      },
      "message": "feat(realm): align RSI ABIs with RMM spec 1.1-alp12\n\nThis syncs the naming of SMC RSI commands with TF-RMM.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7905f0f3788c0c659ba6f787fb002d1c5997d289\n"
    },
    {
      "commit": "8307c3367e29b068cd3e65b5bd05aa28f8fee0f8",
      "tree": "b19d216065c9af2c129b5e692024acc836b70662",
      "parents": [
        "d1cf6dc75ffa489f3055b2c453ad57893214b6bc"
      ],
      "author": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Thu Jun 12 10:30:46 2025 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Fri Jun 13 15:35:48 2025 +0000"
      },
      "message": "feat(rmm): add tests for FEAT_TCR2 on RMM\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I4dc16c5c6edcabf993ea30fe53eff5993b5af651\n"
    },
    {
      "commit": "a1fe738b1fd6212d92e20a408a0110778276732b",
      "tree": "ad9028b4524278c1b14628871964c46a72e564b8",
      "parents": [
        "5032d7bc760128a07ace8c9d4d91f7c3e9011cda"
      ],
      "author": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Fri Apr 25 20:45:17 2025 +0100"
      },
      "committer": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Fri Jun 06 17:53:31 2025 +0100"
      },
      "message": "feat(rme): test access outside PAR from Plane N\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I3c5069e14fdf27e6c36bd1e0651ceff4ee7396ef\n"
    },
    {
      "commit": "20cf8511436b51d6ad4d0db246d23c470391c1ba",
      "tree": "c3fab88bcddb573a4a9465dc593a36e585b624c8",
      "parents": [
        "37fa6b9d4f0f059ec81f163bc230fa3598ef43c1"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Tue May 20 14:37:22 2025 +0100"
      },
      "committer": {
        "name": "Alexei Fedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Wed May 21 16:31:17 2025 +0000"
      },
      "message": "fix(realm): add missing realm_printf() parameters\n\nAdd missing parameters in test_realm_reject_set_ripas()\nfor realm_printf() call.\n\nChange-Id: I005a85aaa60253fcd1c2e47bf34cf4c80083411f\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n"
    },
    {
      "commit": "43ad50d798007af9d607898597d30bf215d3aa05",
      "tree": "1d0620e5b07b525e656d82ea22e7aefedba7f6a7",
      "parents": [
        "8993e8ec7c66a849dad48f7b57e866cc40de3191"
      ],
      "author": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Fri Mar 28 17:37:04 2025 +0000"
      },
      "committer": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Fri Mar 28 17:47:36 2025 +0000"
      },
      "message": "feat(rme): update FEAT_MPAM tests on Realms\n\nCurrently, to test that accessing a FEAT_MPAM register from a Realm\ncauses an undefined abort injected back to the Realm, we only test\nby accessing a single register.\n\nThis patches updates the test by trying to access all MPAM registers\nfrom the Realm to validate that an undefined abort is taken to the\nRealm for all the registers.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I16c88d467eb2a49342694536a1c7b6358416dc34\n"
    },
    {
      "commit": "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6",
      "tree": "a0ec5b6bff32d2fa1294f33af597c0d54558306e",
      "parents": [
        "4dc4a8eff548674eb9074bf86ed4007b07ce3150",
        "c8f5a2ee90f2b376da910f08170af4c4dc7396ae"
      ],
      "author": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Mon Mar 10 14:56:43 2025 +0100"
      },
      "committer": {
        "name": "TrustedFirmware Code Review",
        "email": "review@review.trustedfirmware.org",
        "time": "Mon Mar 10 14:56:43 2025 +0100"
      },
      "message": "Merge \"test: test the save restore logic for brbcr_el1\""
    },
    {
      "commit": "c8f5a2ee90f2b376da910f08170af4c4dc7396ae",
      "tree": "625509a3d6d8838e0c31c9e89fbf23ed9361d15f",
      "parents": [
        "992c62b427ad7fc425ec3c02e6c2f5e98e94d120"
      ],
      "author": {
        "name": "Sona Mathew",
        "email": "sonarebecca.mathew@arm.com",
        "time": "Tue Feb 04 15:22:01 2025 -0600"
      },
      "committer": {
        "name": "Sona Mathew",
        "email": "sonarebecca.mathew@arm.com",
        "time": "Thu Mar 06 16:55:05 2025 -0600"
      },
      "message": "test: test the save restore logic for brbcr_el1\n\nThis patch tests the save/restore logic by enabling\nbranch recording at NS-EL2. Additionally this\npatch also tests the trap logic when FEAT_FGT is enabled\nand a Realm tries to access any FEAT_BRBE related registers.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I176ea6feaf01d42cfd6231dc65a9470da8d1e37c\n"
    },
    {
      "commit": "55d5db87b83b6a073ed3c954d455b862e7b2e7fe",
      "tree": "0019d75c61f3cbac06bc2f1e25d5944c8f9f3880",
      "parents": [
        "7d3b999376c7416584639411f36bdadf877060d3"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Mar 03 12:56:04 2025 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Mar 06 21:08:59 2025 +0000"
      },
      "message": "test(realm): extend ripas tests for planes\n\nTest that accessing page with RIPAS\u003dEMPTY from\nPlane N causes plane exit to P0.\n\nChange-Id: Ic57f049d0fa0140630aa7bfc0702a2dc729967a8\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "7d3b999376c7416584639411f36bdadf877060d3",
      "tree": "c22c6390ab2ec7977af1483c1d4dbf56bd2d388f",
      "parents": [
        "bd729193dcdb19a5f5fa9b259770f1d1f365bad0"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Tue Feb 25 15:39:55 2025 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Mar 06 19:50:15 2025 +0000"
      },
      "message": "test(realm): enhance realm memory exception tests for planes\n\nExtend memory exception tests for planes.\n\nChange-Id: Ifc98b8c67e85b04b36a78f16971d17f05d6a87d2\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "bd729193dcdb19a5f5fa9b259770f1d1f365bad0",
      "tree": "00c47d7308aee2d02a16a3d4a5fbacaf7cf4407d",
      "parents": [
        "78effaa2c47b04abd68273bdea4ebb4f6f9455c0"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Jan 24 17:02:15 2025 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Mar 06 09:57:56 2025 +0000"
      },
      "message": "test(realm): add test for multi rec planes\n\nTest exercises SMC_PSCI_CPU_ON from aux plane.\nRequest is first routed to P0 and then to Host.\nHost enters P0 and then P1 on all CPUs.\n\nChange-Id: I7e34a0070ffa7305b97a0d93de62b64042771a18\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "78effaa2c47b04abd68273bdea4ebb4f6f9455c0",
      "tree": "9ffb7b9430ee5600da7f8e0cd5cd557752ea85fa",
      "parents": [
        "992c62b427ad7fc425ec3c02e6c2f5e98e94d120"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Feb 07 10:30:15 2025 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Mar 06 09:18:01 2025 +0000"
      },
      "message": "test(realm): validate NS EL1/EL2 context is preserved by RMM\n\n- Test validates that NS EL1/EL2 registers are preserved while\n  entering and exiting realm world.\n- Test validates that accessing s2por_el1 in realm causes data abort.\n\nChange-Id: I20cbb9d0d59474507f89ee7cf8e127fff4706610\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa",
      "tree": "010803c4d3fb8186d23cfd2f54f923c8271b45cd",
      "parents": [
        "23ec8506918aff276b21b9543831d4825855906d",
        "82cd82e9868b1f381a5c8d84195657e1583cfca1"
      ],
      "author": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Wed Feb 05 14:19:06 2025 +0100"
      },
      "committer": {
        "name": "TrustedFirmware Code Review",
        "email": "review@review.trustedfirmware.org",
        "time": "Wed Feb 05 14:19:06 2025 +0100"
      },
      "message": "Merge \"feat(rme): add tests for FEAT_MPAM on Realms\""
    },
    {
      "commit": "82cd82e9868b1f381a5c8d84195657e1583cfca1",
      "tree": "c7be244d493e784e55df370f501d8c3ba9275523",
      "parents": [
        "f00a425e1592bd410ff249c1baab8f3b067b1658"
      ],
      "author": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Fri Jan 17 17:37:42 2025 +0000"
      },
      "committer": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Tue Feb 04 15:01:14 2025 +0000"
      },
      "message": "feat(rme): add tests for FEAT_MPAM on Realms\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6e138cbf121793bdaaa3a44824c0dbff74daced1\n"
    },
    {
      "commit": "c398c8f7248e9aec29bbc41c94e41005d539863c",
      "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117",
      "parents": [
        "f00a425e1592bd410ff249c1baab8f3b067b1658"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Thu Jan 16 14:35:48 2025 +0000"
      },
      "committer": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Tue Feb 04 11:38:28 2025 +0000"
      },
      "message": "fix(realm): fix realm PMU tests\n\n- FEATURE_PMU_NUM_CTRS field in feature_flag was used\nto pass number of PMU event counters in realm creation.\nThe width of this field was set to 4, which was not\nenough to pass numbers \u003e 15 and was causing PMU tests\nfailures in FVP configuration with more than 15 event\ncounters implemented.\n- This patch removes all FEATURE_XXX macros for setting\nfeature_flag and replaces them with the corresponding\nRMI_FEATURE_REGISTER_0_XXX to match feature register 0.\n- In host_set_pmu_state() function was setting PMSELR_EL0\nto incorrect value 0 instead of 31 to select PMU cycle\ncounter for configurations with no event counters implemented.\n- Test host_realm_pmuv3_mul_rec() was running incorrectly\nwith number of event counters set to 0 or 31.\n- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0\ncan be constrained unpredictable depending on the\nvalue of PMSELR_EL0.SEL and number of accessible event\ncounters. See corresponding TF-RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573\nThis patch fixes host_set_pmu_state() and\nhost_check_pmu_state() functions to avoid unpredictable access\nto these registers.\nThis patch makes Realm PMU tests pass for all possible FVP\nconfigurations clusterN.pmu-num_counters\u003d[0...31].\n\nChange-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n"
    },
    {
      "commit": "47078f35247dcb85f5a1ce8ea0bc52d3aee74451",
      "tree": "03562b94399c44ff32b0c1f81d1c8e35016d8e4f",
      "parents": [
        "414346805fa6589643780f6f9ce181facf2e1271"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Jan 16 18:54:24 2025 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Jan 31 17:44:19 2025 +0000"
      },
      "message": "test(realm): fix multi rec PMU tests\n\n- set different values of PMU event counters for each rec\n- check PMU counters are preserved for each rec\n\nChange-Id: I7c4ad3971d4a10b4515be0dfe096bebf8d903c71\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "414346805fa6589643780f6f9ce181facf2e1271",
      "tree": "69b825442caff18f8b25d6eee80140c80832d176",
      "parents": [
        "158208e895d38d659d216c793d42d132ed90e598"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Dec 05 14:57:48 2024 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Jan 31 14:53:41 2025 +0000"
      },
      "message": "test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n\ntest for RSI_PLANE_REG_READ/WRITE command\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I92e0aeef48c9b2abe26e5d3b2ea62669a22d4f8b\n"
    },
    {
      "commit": "158208e895d38d659d216c793d42d132ed90e598",
      "tree": "86cf20c9982b4b186bcc17944cd9f569701f6fe4",
      "parents": [
        "a0736c3dbf83f3c00ca98c83534070be259fb822"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Nov 27 10:12:41 2024 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Jan 31 13:55:23 2025 +0000"
      },
      "message": "test(realm): add testcase to enter all planes\n\nTestcase creates realm with all 4 planes.\nEnters all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I7a3b9103e1fbcfe98117c02827624a2fc2d24fc2\n"
    },
    {
      "commit": "a0736c3dbf83f3c00ca98c83534070be259fb822",
      "tree": "4ab625c28b93f9fe02b4072720ab05a342175b26",
      "parents": [
        "69cae79515b85f13a3ee957474231e51e879c4d8"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Nov 27 09:34:35 2024 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Jan 31 13:55:12 2025 +0000"
      },
      "message": "test(realm): handle permission fault for planes\n\nAdd support for handling permission fault in planes.\nSet s2ap in RTTs.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I590fc5a1c43357b117fa5cb76e8c699c4c7eebad\n"
    },
    {
      "commit": "69cae79515b85f13a3ee957474231e51e879c4d8",
      "tree": "80f41a9c19830d92bf024f5c9eabf65e2b505a5a",
      "parents": [
        "9110508906774bb3949fa5609a5d767021a6a4e8"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Nov 27 04:30:00 2024 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Jan 31 13:53:44 2025 +0000"
      },
      "message": "test(realm): add support for planes shared buffer\n\n- Add support for per plane shared buffer.\n- Map shared buffer in all Aux RTT if\n  realm uses multiple RTTs.\n- Support realm_printf for all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie6924bcb9e9bb3b8c368f796d33f84f4f6821935\n"
    },
    {
      "commit": "9110508906774bb3949fa5609a5d767021a6a4e8",
      "tree": "8233efd6cb8467288ae76544c0682c4e89766dc2",
      "parents": [
        "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Nov 27 05:29:55 2024 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Jan 31 13:53:25 2025 +0000"
      },
      "message": "test(realm): add plane PSI interface\n\nAdd Plane service routine interface.\nAux plane can communicate with primary plane using PSI\nPSI uses hvc conduit from aux plane.\nAdd initial printf support for planes\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I484cbd32791970c6e22c5d63e13b43807f4f3c06\n"
    },
    {
      "commit": "5abab7674959cb2fa3211e5199ac3115e72e86dc",
      "tree": "86f2a0e558571dc8e5f616e31d1564f8fbf11d5a",
      "parents": [
        "8f5dae9067e545618830abda9fc5f143c58e7c9f"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Nov 27 04:57:53 2024 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Jan 10 16:39:05 2025 +0000"
      },
      "message": "test(realm): add support for RSI Planes ABI\n\nAdd Planes RSI support.\nAdd helpers to setup initialize and enter planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I62946a185c47fe77a04f42751d0b0a467d41ceee\n"
    },
    {
      "commit": "88ffad277a35f0dcecd19d167021b26d2c7bc790",
      "tree": "bc1a7e0a794c8a79438eb9df86c5ed86757daf5e",
      "parents": [
        "c79338af9a3e9cb24b90afd79491c85b7ef11d72"
      ],
      "author": {
        "name": "Juan Pablo Conde",
        "email": "juanpablo.conde@arm.com",
        "time": "Fri Oct 11 21:22:29 2024 -0500"
      },
      "committer": {
        "name": "Juan Pablo Conde",
        "email": "juanpablo.conde@arm.com",
        "time": "Wed Nov 20 15:06:04 2024 -0600"
      },
      "message": "test(realm): add tests for realm attestation\n\nWith this patch, TFTF adds two tests for realm attestation. One tests\nthe full process of retrieving the attestation token from the host. The\nsecond one triggers a failure by calling RSI_ATTEST_TOKEN_CONTINUE\nwithout calling RSI_ATTEST_TOKEN_INIT first.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I885402377af1f02ce7e90c80dbe1079fe4c1b178\n"
    },
    {
      "commit": "46d0228e2a1a17c57be8f5011f183ea28e6ba518",
      "tree": "ce322be37116651bf3ab1d681632c176f8105233",
      "parents": [
        "7c78f7b4a74e58512ff6998f7a5438520e58c343"
      ],
      "author": {
        "name": "Manish V Badarkhe",
        "email": "Manish.Badarkhe@arm.com",
        "time": "Mon Nov 18 16:58:37 2024 +0000"
      },
      "committer": {
        "name": "Manish V Badarkhe",
        "email": "manish.badarkhe@arm.com",
        "time": "Tue Nov 19 11:22:08 2024 +0100"
      },
      "message": "fix(serror): use custom argument for incrementing elr_elx\n\nAdd a custom argument to increment the elr_elx after handling SError.\nIn some cases, to prevent re-triggering the instruction, ELR needs\nto be incremented by 4. In other cases, it may not be necessary.\n\nThis argument is passed to the handler, which then decides whether\nto increment elr_elx by setting the passed argument accordingly after\nhandling the SError.\n\nChange-Id: I404f3c5e24f894502a8d00c73649be0b2dd540fa\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n"
    },
    {
      "commit": "7c78f7b4a74e58512ff6998f7a5438520e58c343",
      "tree": "ea7bd3a6363d1bf5686e5cfbd2a92cabec7a3df6",
      "parents": [
        "4c19b48e1d0aed1cfb94785c86544d2a58190ade"
      ],
      "author": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Fri Oct 25 11:44:32 2024 +0100"
      },
      "committer": {
        "name": "Javier Almansa Sobrino",
        "email": "javier.almansasobrino@arm.com",
        "time": "Tue Nov 19 10:10:16 2024 +0000"
      },
      "message": "feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n\nWhen FEAT_DoubleFault2 is supported, TF-RMM must take into\naccount bit SCTLR2_EL1.EASE in order to decide whether to inject\na SEA into the sync exception vector or into the serror one.\n\nThe test on this patch verifies that TF-RMM injects the SEA\nto the right vector depending on SCTLR2.EASE bit.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c976fecb04d123e3efb96c5973b1466e241097f\n"
    },
    {
      "commit": "9a60ecbf209d2faf117420b9013c52216106d157",
      "tree": "21df19a240173b2d14a9633c146f66665fa1e95d",
      "parents": [
        "dff904b244bc97672dd2408fa2d38f15b3ca7ced"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Tue Aug 06 16:39:00 2024 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Oct 01 16:55:17 2024 +0100"
      },
      "message": "feat(realm): update rsi_ipa_state_get() function\n\nThis patch updates rsi_ipa_state_get() function and its\nrelated test calls as per RMM Specification 1.0-rel0-rc1.\nIt also updates RSI commands API related comments and\nmakes minor changes in test functions to improve code\nreadability.\n\nChange-Id: I28f69967ab6ff5b38c2b9efd423b0e8b4ad61dae\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n"
    },
    {
      "commit": "dff904b244bc97672dd2408fa2d38f15b3ca7ced",
      "tree": "55029d438a9f7cfd221d49bab7120480650c8b9b",
      "parents": [
        "3a137fc469a3241cfda137975dd8c9805331023b"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Mon Aug 05 17:11:18 2024 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Oct 01 16:55:17 2024 +0100"
      },
      "message": "feat(include/runtime_services): update RMI and RSI definitions\n\nThis patch:\n- updates fields definitions of RmiFeatureRegister0 type,\n- adds \u0027RSI_IO\u0027 definition to \u0027rsi_ripas_type\u0027 enumeration,\n- adds \u0027algorithm\u0027 and \u0027rpv\u0027 members to \u0027rsi_realm_config\u0027\nstructure\naccording to the RMM Specification 1.0-rel0-rc1.\n\nChange-Id: Ic1f25b0e3ddbc93a4fceb88f9db4d808b54cc628\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n"
    },
    {
      "commit": "f09c77af164cb1332a4db3d141ffc5d60625967b",
      "tree": "4d5f1085a718618101a75d36e503d0da4aba0b1d",
      "parents": [
        "f30108d8427112a11fbcd3561bdb0bed425f8896"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Tue Sep 10 15:50:44 2024 +0100"
      },
      "committer": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Thu Sep 12 11:59:53 2024 +0100"
      },
      "message": "fix(realm): fix calculation of Realm\u0027s REC index\n\nThis patch fixes the issues related to the calculation of\nRealm\u0027s REC index based on the read value of MPIDR_EL1 register\nand REC\u0027s mpidr parameter from the REC\u0027s index.\nRMM reports MPIDR_EL1.Aff0 field matching RmiRecMpidr type\nwith [7:4] bits RES0, making MPIDR_EL1\u003d0x80000100 represent\nREC 16, but not 256 as it is implemented in the existing code.\nThe patch adds the following macros:\n- RMI_REC_MPIDR(idx) which calculates RmiRecMpidr value based\non REC index.\n- REC_IDX(mpidr) gets REC index from MPIDR_EL1.\n\nChange-Id: Ieac473984f3a50d2815dcfe8d291d31bd70ebae7\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n"
    },
    {
      "commit": "f30108d8427112a11fbcd3561bdb0bed425f8896",
      "tree": "bd52b3644cc71a7a21dc41c4007748aad6926697",
      "parents": [
        "f13410b3e4d9a2526333d2621ad5e8aede6c2b86"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Fri Sep 06 17:24:24 2024 +0100"
      },
      "committer": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Wed Sep 11 16:14:33 2024 +0100"
      },
      "message": "fix(realm): fix realm initialisation code\n\nThe curent code in \u0027realm_entrypoint\u0027 relies\non primary VCPU to perform initialisation and\nsymbols relocation. This makes impossible to\nrun any REC\u003cn\u003e before REC\u003c0\u003e runs, because\nREC\u003cn\u003e will be detected as a secondary VCPU\nnot required to perform the initialisation\nwhich will cause the crash.\nThis patch fixes this issue by introducing\n\u0027cold_boot_flag\u0027 variable which is updated\nby the first VCPU which runs \u0027realm_entrypoint\u0027\nand performs initialisation.\n\nChange-Id: I0161f7132f64423cff646db74f95753aa9a5d073\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n"
    },
    {
      "commit": "042e96065620549d413c78ca29323f9156764d50",
      "tree": "d821c8d868522feab30123300dd9429ecfd3412d",
      "parents": [
        "de0e8be6dc2d4209544bcd423f735527b7d486c6"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu May 30 13:55:11 2024 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Thu May 30 17:26:59 2024 +0200"
      },
      "message": "test(realm): fix pauth exception test\n\nPauth exception tests fail when FEAT_PAUTH2 is enabled.\nFix error, return success if exception handler is hit,\nremove PAC fields check since the PAC fields can vary based\non the configuration of the system.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Id6312c7ebb7202302d8465f772deb176e419bded\n"
    },
    {
      "commit": "b1b37926917b265ef8a3f6caf59b6a20fe8b636c",
      "tree": "41baf3e3f7d6ab325f673bb5bababe955713663f",
      "parents": [
        "e3ee6e0a40b73baffd26563adb9cf49b040cbc30"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Sat Jan 13 21:49:04 2024 +0000"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Fri Mar 29 09:22:09 2024 +0100"
      },
      "message": "test(realm): add test for enabling pmu with multiple rec\n\nTest creates realm with less number of pmu counters than available\nTest verifies that only programmed num of pmu counters are available in realm\n\nChange-Id: I479dd8949950357b9814576b1b6cef142d21c75f\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "2a5abadb8e841eedeaa1ff78b6f0da5f957b2ab8",
      "tree": "42755e1512d2cf0d6abf3f0baa01a289d2a69e46",
      "parents": [
        "21a30ed1ae35a8b32d23e96cdc143702a27bda90"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Jan 17 13:48:44 2024 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Feb 14 12:51:31 2024 +0100"
      },
      "message": "test(realm): add test for FEAT_DIT\n\nAdd testcase to enable FEAT_DIT in realm.\nTest if DIT Bit is preserved across context switch RL/NS.\n\nChange-Id: I26cbaaf669b53ecba14a451955b6f847c45e0575\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "21a30ed1ae35a8b32d23e96cdc143702a27bda90",
      "tree": "bd1d61a86ff59e96c33a98a036e542f43ce185df",
      "parents": [
        "a8deec5c0b51719b1f268e4f106c3a095a387074"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Sat Jan 13 23:07:43 2024 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Feb 14 12:51:31 2024 +0100"
      },
      "message": "test(realm): test realm pauth state is preserved\n\nModify Pauth lib to work for multiple CPU\nTest if Realm pauth state is preserved for all RECs\non context switch to RMM/NS.\n\nChange-Id: Ibb393b415bab27066289b560be49e02d0c8f58ba\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "b027f5706308502152b5aade0ad509ba27370c42",
      "tree": "3a05dab054068d29e8b242f8f82daa4a864468e9",
      "parents": [
        "fd35f0a4d6125bb1fa69a671a6d2d42628229609"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Tue Jan 02 22:00:29 2024 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Feb 08 12:14:31 2024 +0100"
      },
      "message": "test(realm): add testcase for Synchronous external aborts\n\nAdd testcase to cause instruction or data abort in Realm by\naccessing addr with\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dEMPTY\n* HIPAS\u003dASSIGNED and RIPAS\u003dEMPTY\n* Unprotected IPA\n* Host injected SEA after Data abort\n\nChange-Id: I6be546c042b4983670fb7c27fca74649c68787be\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "e68494eb130e2c8021ca4af626a9cb1df8d67dbd",
      "tree": "894c262fc0aa78dcbe3b28cc6b731df068a404b6",
      "parents": [
        "daa6c795847b78692f522fd96f783a6d419aaec2"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Nov 06 11:04:57 2023 +0000"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Tue Feb 06 10:45:44 2024 +0100"
      },
      "message": "test(realm): add testcase for REC exit due to Data/Instr abort\n\nAdd testcase to cause instruction or data abort in Realm by\naccessing addr with\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dDESTROYED\n* HIPAS\u003dASSIGNED and RIPAS\u003dDESTROYED\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dRAM\nVerify rec exit due to abort\n\nChange-Id: Ic04c0ddaf1b18ec0cfd71c28753c4ed7298302da\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "affbae8163ad25534cfe4dbc4bcda5a3372d0062",
      "tree": "b75a233b78259620329179a4f6e3d8e3a3b18d79",
      "parents": [
        "ec482824eba8020f9b36b6b7a563ac3c84064c23"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Tue Aug 22 12:51:11 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri Jan 05 15:35:50 2024 +0000"
      },
      "message": "test(rmm): add testcase for multiple rec on multiple cpu\n\nTest creates and enter 8 recs on different CPUs.\nExercises CPU_ON, CPU_OFF and PSCI_AFFINITY_INFO\nfrom realm.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Iecc58ea79bfde28f307d1df99680d707e57a1d80\n"
    },
    {
      "commit": "fef8621d2d5ce3ce67a4ba3013292b7382b92355",
      "tree": "3704d2a1a84205cedf36191c7f2ebb648ecce4a2",
      "parents": [
        "bb772193864856ce5d0da9b3534316b7bc4fc3d3"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Tue Oct 17 12:15:38 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Dec 19 15:09:04 2023 +0200"
      },
      "message": "test(realm): testcase for RMI_RTT_SET_RIPAS reject\n\nAdd testcase for realm to call rsi_ipa_state_set,\nhost will reject and call RMI_RTT_SET_RIPAS\nre-enter rec with response RSI_REJECT\n\nChange-Id: I6809fdabba580b23269aedc2aa844b15fbcce981\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "bb772193864856ce5d0da9b3534316b7bc4fc3d3",
      "tree": "c2ecde3c3eaea03acb70d6fa5166e178591a1fd2",
      "parents": [
        "d5b30b42f36d9fc80d0a26c238129a2488f6a068"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 09 16:08:28 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Dec 19 15:08:13 2023 +0200"
      },
      "message": "feat(realm): add support for RSI_IPA_STATE_GET/SET\n\nAdd support for realm API rsi_ipa_state_set, rsi_ipa_state_get\nAdd testcase for following\n* Realm calls rsi_ipa_state_set to change RIPAS\u003dRAM,\n* Host accepts and call RMI_RTT_SET_RIPAS\n* Realm verifies RIPAS change was successful\n\nChange-Id: I4da6c7d25faa62afde1d0f682510bac6c8445821\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "a276b20c477aab869c74f687484d480c4a289f0a",
      "tree": "e3166fc186f557e471e3207b6602d17540adfb80",
      "parents": [
        "ac806965a1d44d1ef98919df8241a8d54141f7ca"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Dec 18 10:07:43 2023 +0000"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Mon Dec 18 13:53:03 2023 +0200"
      },
      "message": "test(realm): fix realm_printf string\n\nRemove extra Realm: string from realm printf\ncorrect the print format\n\nChange-Id: I1916cf5bda23aab2cdee59457872353c108148c7\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "43a50c3b4c1d33be07cf77fb674f7060dc93f601",
      "tree": "59a08d3befd987a7c48975f8cb068040131e9b8e",
      "parents": [
        "b28d63d4197acf7915d8ea4ea0133ac2e929242b"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Tue Nov 28 10:54:27 2023 +0000"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Mon Dec 11 13:37:52 2023 +0200"
      },
      "message": "fix(realm_test): host_call structure should be per rec\n\nThere is a chance of corruption in host_call data\nstructure leading to crash.\nThe structure needs to be allocated per rec.\n\nChange-Id: I6483168df4637392f80fcb83eae279317d4cafa7\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "5f0afde449993a006989f34f68a05e93bb280c0b",
      "tree": "ba3b755bd16bb7d50b2a1bcaaa72da4ea3809b43",
      "parents": [
        "222dee1616ffc01353e232a565a370a85bd4aeb5"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Nov 20 12:05:50 2023 +0000"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue Dec 05 09:54:24 2023 +0000"
      },
      "message": "feat(rme): add realm_print_exception for realm payload\n\nThis is a fork of exception_report.c in TFTF framework to\nrealm_exception_report.c. realm_print_exception uses realm_printf\nand removes platform specific calls.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I26c8790e5cac81bbab01fa81c4282824ded72b55\n"
    },
    {
      "commit": "222dee1616ffc01353e232a565a370a85bd4aeb5",
      "tree": "34b5b2fd5722ab7122d4637f5cd9306cfe64dd41",
      "parents": [
        "12cee415ae010d0258f238b1a51c1af117b2e0e5"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Nov 20 12:05:25 2023 +0000"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Dec 04 19:29:48 2023 +0000"
      },
      "message": "fix(rme): fix realm vbar_el1 load address\n\nFix the position independent addressing of \u0027realm_vector\u0027 using adrp+add\ninstruction pair.\n\nCalculate the base address of the 4KB aligned memory region that\ncontains the label \u0027realm_vector\u0027 using adrp instruction. Then to that\nbase address add the offset of \u0027realm_vector\u0027 (lower 12 bits).\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I9e08eea98293e2e03cecb8465cea0f2c9361795b\n"
    },
    {
      "commit": "1768e59c3a6ac8d727ac012719b4b09947c8400d",
      "tree": "cc6ad04618bb60fb861bf3e7e4da2538c1a5cf42",
      "parents": [
        "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue May 23 13:28:38 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue Oct 31 13:56:54 2023 +0000"
      },
      "message": "feat(rme): add tests to check NS SME ID registers and configurations\n\nThese tests checks the functionality of RMM for NS SME support.\n- Create Realm and test ID registers specific to SME\n- Check if Realm gets undefined abort when it accesses SME\n- Check whether RMM preserves NS SMCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ia8ffd0188297a74c095dbadfb389add50c548e10\n"
    },
    {
      "commit": "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581",
      "tree": "3e0552b2dae1f333abe34bddd7a4ea63c40f985f",
      "parents": [
        "47b702c49a622e895d70104d78a20bb979dae229"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue Jun 06 16:31:19 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Tue Oct 31 13:56:17 2023 +0000"
      },
      "message": "feat(sme): add sme helper routines and add streaming sve support\n\nThis patch adds a few helper routines to set the Streaming SVE vector\nlength (SVL) in the SMCR_EL2 register, to enable/disable FEAT_SME_FA64\nand to get CPU\u0027s Streaming SVE mode status.\n\nThis patch also makes SVE compare routines compatible for both normal\nSVE and streaming SVE mode.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7294bb17a85de395a321e99241704066662c90e8\n"
    },
    {
      "commit": "40de8ec10f4d9925c24d2b9dd22822e0c8fd4224",
      "tree": "30347a76b3f2429f8ab3d0f124526d860ee77503",
      "parents": [
        "6bb95105b289a4d9015d74af7cb7254455b2344e"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Oct 12 21:45:12 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Oct 31 02:57:53 2023 +0000"
      },
      "message": "feat(rmm-eac5): update RSI_VERSION, RMI_VERSION\n\nThis patch adds necessary support for RMI_VERSION\nand RSI_VERSION commands.\nMacro SMC_RSI_ABI_VERSION renamed to SMC_RSI_VERSION.\n\nNote.\nThis patch sets both RSI and RMI version numbers to\n1.0 as per RMM Specification 1.0-eac5.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If4eb14d93f657388e2fe64ceefee002403cc4ae8\n"
    },
    {
      "commit": "6bb95105b289a4d9015d74af7cb7254455b2344e",
      "tree": "faf71d64251c88b5aa5caa5512a76eff62601851",
      "parents": [
        "24597d136cc199d8399be2291fda2efb0a652741"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 02 13:21:37 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Oct 31 02:57:53 2023 +0000"
      },
      "message": "feat(rmm) : add api for rec force exit\n\nadd api to force exit a rec\nadded testcase for force exit rec\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I56c70234e236c7d3615237d11c773bdb970012e3\n"
    },
    {
      "commit": "24597d136cc199d8399be2291fda2efb0a652741",
      "tree": "686e70f45e398155a42fc811e6abad9eb2a84254",
      "parents": [
        "a29e811d596794b5e135904be9033e9a1662507e"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 02 10:40:19 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Tue Oct 31 02:57:53 2023 +0000"
      },
      "message": "test(rmm-eac4): add testcase for CPU_ON denied\n\n- Testcase creates multiple rec\n- Host receives CPU_ON request from realm\n- Host calls PSCI_CCMPLETE with denied status\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie89b7a3b9603916275913a273751210350075e96\n"
    },
    {
      "commit": "f369717f93ee8d7e2c12460e71d335bc702e37b4",
      "tree": "ff959de9f2e05c711dae73bedf2e5b8a34d56f2b",
      "parents": [
        "6e587999a0b2f3055d14e08b7bbcfa5735db9891"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Sep 04 15:04:46 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Oct 25 15:07:15 2023 +0100"
      },
      "message": "test(rme): check various SIMD state preserved across NS/RL switch\n\nThie test case verifies whether various SIMD related registers like\nQ[0-31], FPCR, FPSR, Z[0-31], P[0-15], FFR are preserved by RMM during\nworld switch between NS world and Realm world.\n\nRandomly verify FPU registers or SVE registers if the system supports\nSVE. Within SVE, randomly configure SVE vector length.\n\nThis testcase runs on below configs:\n* with SVE\n* without SVE\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I3fc755f75bdcdc8c24af0440d8a5f094beafca73\n"
    },
    {
      "commit": "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045",
      "tree": "68f9b32383bb80a3542368ebe9ffc15e4bba1c43",
      "parents": [
        "035899729133080ffff3ed691ba65664c34f75ca"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Aug 30 13:27:36 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Oct 25 14:24:42 2023 +0100"
      },
      "message": "feat(fpu): add helper routines to read, write, compare FPU registers\n\nAdd helper routines to read, write, write_rand and compare FPU state\nand FPU control/status registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to pass memory to read/write FPU\nregisters.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I10ae5487c9f58e46434c1bd5b42fd458ec755045\n"
    },
    {
      "commit": "035899729133080ffff3ed691ba65664c34f75ca",
      "tree": "02a0b07c127329297d5c28e0683352357c8c0d8a",
      "parents": [
        "73949a20b61def813b3265c2a6a330656bd001af"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Aug 30 11:04:51 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Oct 25 14:15:59 2023 +0100"
      },
      "message": "fix(sve): represent sve Z0-31 registers as array of bytes\n\nCurrently each Z register is type defined as sve_vector_t but the helper\nroutine to write or read Z registers works based on current vector\nlength.\n\nIf test case defines \u0027sve_vector_t zregs[32]\u0027 and reads all Z registers\nusing sve_read_vector_regs() then zregs[n] might not corresponds to Zn\nregister unless the vector length is set to max value.\n\nThis patch also renames sve_vector_length_get() to sve_rdvl_1()\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I42955f8009bdd7f40d74c5a8d21d7c16ce6d761e\n"
    },
    {
      "commit": "73949a20b61def813b3265c2a6a330656bd001af",
      "tree": "ab41f5043a87d13fcccbc8bf0473bc2817fa13a4",
      "parents": [
        "cbfec24f12c205a8c827604864e2c51f7d419b33"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Jun 05 12:01:05 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Oct 25 14:15:55 2023 +0100"
      },
      "message": "test(rme): check if non SVE realm gets undefined abort\n\nThis test checks whether a non SVE realm receives undefined abort upon\naccessing SVE register state or instructions.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2785488b1344cc4d59dde75e38d9e0d6f856af61\n"
    },
    {
      "commit": "52b5f02cf50a79efdaf7bd6682e40a069dec04b7",
      "tree": "62b0019e05420486a64cfd7507fb4f2437fd4735",
      "parents": [
        "699cd4feef98deb1e1d3bc95adc42a16da40052d"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Thu Oct 12 22:02:29 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 23 19:34:54 2023 +0200"
      },
      "message": "feat(rmm) : use shared data buf to pass arg to rec\n\nHost can pass arguments to rec using\nper rec shared buffer.\n\nChange-Id: Ic34acf6253031b3b5f184669084f15460b0fc5fd\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "699cd4feef98deb1e1d3bc95adc42a16da40052d",
      "tree": "dc08fba188c5d63d40f30d5eb382c8d0e680a2ad",
      "parents": [
        "8ce3053050bc37f5cfccadefd575a597ac86dd95"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Sep 27 16:46:54 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 23 19:34:54 2023 +0200"
      },
      "message": "feat(rmm): add psci api to realms\n\nadd wrappers for PSCI APIs\nCPU_ON\nCPU_OFF\nPSCI_AFFINITY_INFO\nPSCI_FEATURES\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ice7bc03d052a0726163c7a31a32f59688e7f516b\n"
    },
    {
      "commit": "8ce3053050bc37f5cfccadefd575a597ac86dd95",
      "tree": "bd9c9d8e6eeba40a81702f88e8cb3bcbb44b9abf",
      "parents": [
        "550e3e88891507cd514fbd8f27d6ba6b8c5a3162"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 16 15:58:38 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 23 19:34:54 2023 +0200"
      },
      "message": "feat(realm): add host call to flush realm prints\n\nadd new host call to push out realm print buffer\nbuffer is flushed after every print statement\n\nChange-Id: I6efa92a7c75ab7df4615a432802426de39d0032c\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n"
    },
    {
      "commit": "550e3e88891507cd514fbd8f27d6ba6b8c5a3162",
      "tree": "81485909f1376913447c3480d640f9717bb61de0",
      "parents": [
        "cdf525212326f8b453f22122dddc9d8bf0725981"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Aug 16 13:20:11 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Oct 23 19:34:54 2023 +0200"
      },
      "message": "feat(rmm): add support for multiple rec and cpu\n\nChanges to support creating and\nexecuting  multiple rec on multiple cpus.\nAdded per REC shared buffer between Host and Rec.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ib6dbd814ee9f68df4a53f9cfdc8b7f9c905c35fe\n"
    },
    {
      "commit": "3d3dea2c3712b9b3f6b69b1690a6c73aeefc9a3e",
      "tree": "e94fa3ce32d2f1f956059797fee04ee9a51cb095",
      "parents": [
        "44927c3293c656b878ef1c93e1c8cc4dc92944af"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Thu Apr 06 15:36:27 2023 +0100"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Wed Sep 13 09:42:51 2023 +0100"
      },
      "message": "feat(rme):set size of RsiHostCall.gprs[] to 31\n\nThis patch sets the size of gprs[] array in RsiHostCall\nstructure to 31, as per RMM Specification 1.0-eac1.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I81417009b34fca435dd070c94d8e064b8f8bfd9b\n"
    },
    {
      "commit": "9d0cfe88aedc34f1b61a51ff18013743c56e2fbc",
      "tree": "b5b65d1a477d3d46aacfb69bd3dff348a2136ce4",
      "parents": [
        "85d58f31f121445225c2b9e6ee94c8589cc36669"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Mon Apr 17 10:57:26 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Tue Jul 25 17:00:33 2023 +0100"
      },
      "message": "test(tftf): test PAuth in Realm\n\n- Enable PAuth in Realm RL1 by default.\n- Check if PAuth keys are accessible in Realm RL1.\n- Check if Realm PAuth keys are preserved across RMM entry/exit.\n- Check if NS PAuth keys are preserved across RMM entry/exit.\n- Generate PAuth fault by cloberring LR.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I85d8e03ec604c96117555e7aa866453cb2745cfe\n"
    },
    {
      "commit": "fb98ffd60a30c8d2b67b49bf7482fff8be7c6488",
      "tree": "3a192f12127f5c2f7c5a323dac343c5c4caa5ff8",
      "parents": [
        "9af432e408b3e66f3e4cd00cbc98486c7bd9be03"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Jun 05 11:33:33 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Jun 05 13:53:56 2023 +0100"
      },
      "message": "fix(realm): align realm stack\n\nrealm_entrypoint fails while accessing unaligned stack base. This\nissue happens when a newly added global variable shifts the end of\nstack to be unaligned.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I75901a2ead41adc0a19f92896be9e75b1fc882c6\n"
    },
    {
      "commit": "9af432e408b3e66f3e4cd00cbc98486c7bd9be03",
      "tree": "5dd128bc21f399ec872ecb9d8b969d29784ef78e",
      "parents": [
        "8ebb89cae65a199e80894775b80a202f50e94cec"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Fri Jun 02 17:18:23 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Mon Jun 05 11:52:21 2023 +0100"
      },
      "message": "fix(tftf): command id passed to realm to compare FPU registers\n\nThis fixes the command id passed to Realm to compare FPU/SIMD regs.\nAnd also adds a missing break statement in Realm payload main entry\nfunction for command REALM_REQ_FPU_CMP_CMD.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Iaf7073475291785990a55675746968b291fdf507\n"
    },
    {
      "commit": "5270d01e968b1b0a8b853a9263e767a467e541b9",
      "tree": "ac67959df7b5d536b4c662ed1f0a0e2f19970980",
      "parents": [
        "c1136a849fc21470313e4e852a22ae4b9db50440"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Apr 19 14:53:42 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed May 24 13:40:42 2023 +0100"
      },
      "message": "tftf(rme): check if RMM doesn\u0027t leak Realm contents in SVE registers\n\nThis test verifies that the Realm contents in SVE registers are not\nseen by NS world once the Realm returns back to the host. This test\nperforms the below steps:\n\n1. Set NS world SVE VQ to max and write a known pattern.\n2. Set NS world ZCR_EL2 with VQ as 0 (128 bits).\n3. Create Realm with max SVE VQ\n4. Call Realm to fill in Z registers\n5. Once Realm returns, NS sets ZCR_EL2 with max VQ and reads the\n   Z registers.\n6. The upper bits of Z registers must be either 0 or the old values\n   filled by NS world at step 1.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I8205190d1ce9c37b99d35cf5b15df21ca9b838c3\n"
    },
    {
      "commit": "c1136a849fc21470313e4e852a22ae4b9db50440",
      "tree": "b6b5e8854589497f4e2d2c159f0bd2e590dcd8c5",
      "parents": [
        "d179ddcc64cac3b319b301cfe6c1bc32c1ea0eaf"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Apr 12 15:24:44 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed May 24 13:40:42 2023 +0100"
      },
      "message": "tftf(rme): intermittently switch to Realm while doing NS SVE ops\n\nInterleave NS SVE operations with Realm SVE operations and check whether\nSVE vectors are not affected.\n\nThis test also configures SVE op array and SVE vector length with random\nvalue in NS and Realm for test each iteration.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7a9ba4bd0d298f187baa3048ec622eb97ec3d99f\n"
    },
    {
      "commit": "0bbdc2dff449036aa65e4c53cd351d01484e0d23",
      "tree": "60f35abe7f72ade6409b3ffcd46262502a9b6885",
      "parents": [
        "ed7cdc8b28137ab15d9f263825674d156b3c2b30"
      ],
      "author": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Wed Apr 05 15:30:18 2023 +0100"
      },
      "committer": {
        "name": "Arunachalam Ganapathy",
        "email": "arunachalam.ganapathy@arm.com",
        "time": "Thu May 18 16:08:39 2023 +0100"
      },
      "message": "feat(rme): add SVE Realm tests\n\nVerifies Realm with SVE support. Below tests are added\n- Check whether RMI features reports proper SVE VL\n- Create SVE Realm and check rdvl result\n- Create SVE Realm with invalid VL and check if it fails\n- Create SVE Realm and test ID registers\n- Create non SVE Realm and test ID registers\n- Create SVE Realm and probe all supported VLs\n- Check RMM preserves NS ZCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I98a20f34ce72c7c1a353ed13678870168fa27c48\n"
    },
    {
      "commit": "369955abac0a083f57bfb787eeda82a511eb8fc0",
      "tree": "54a35fd1b033a708569c91f2dfb1e1516d690cec",
      "parents": [
        "38133fa69bfefab6e3d1d7461b42c806d36ae33b"
      ],
      "author": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Wed Apr 19 18:05:56 2023 +0100"
      },
      "committer": {
        "name": "Shruti Gupta",
        "email": "shruti.gupta@arm.com",
        "time": "Fri May 05 13:56:12 2023 +0100"
      },
      "message": "test(tftf): test FPU state registers context is preserved in RL/SE/NS\n\nTest that FPU/SIMD state are preserved during a randomly context switch\nbetween secure/non-secure/realm(R-EL1)worlds.\nFPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers,\nthe test runs for 1000 iterations with random combination of:\nSECURE_FILL_FPU, SECURE_READ_FPU, REALM_FILL_FPU, REALM_READ_FPU,\nNONSECURE_FILL_FPU, NONSECURE_READ_FPU commands,to test all possible\nsituations of synchronous context switch between worlds, while the\ncontent of those registers is being used.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I6da5fd334777000111924bb1239b77123a3dcea6\n"
    },
    {
      "commit": "2f30f1030f186760b20cd06b59832e332b2bdd0a",
      "tree": "e06899ba1be405650b4a15603429900dac67ccc2",
      "parents": [
        "2eb601b98a245df8a31e670a7dc322c2e8f153cf"
      ],
      "author": {
        "name": "AlexeiFedorov",
        "email": "Alexei.Fedorov@arm.com",
        "time": "Mon Mar 13 19:37:46 2023 +0000"
      },
      "committer": {
        "name": "Soby Mathew",
        "email": "soby.mathew@arm.com",
        "time": "Fri Mar 31 11:41:56 2023 +0200"
      },
      "message": "feat(rme): add PMU Realm tests\n\nThis patch adds Realm PMU payload tests with\nPMU interrupt handling.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2\n"
    },
    {
      "commit": "002e569021f2e219456d02dfe239218eba5c7cfa",
      "tree": "4c2ea2d7cce38d168ce5e03849498161d537f1c2",
      "parents": [
        "0fcfd47a5936180b754819ee928e8d5af173c5d2"
      ],
      "author": {
        "name": "nabkah01",
        "email": "nabil.kahlouche@arm.com",
        "time": "Mon Oct 10 12:36:46 2022 +0100"
      },
      "committer": {
        "name": "nabkah01",
        "email": "nabil.kahlouche@arm.com",
        "time": "Tue Nov 08 16:34:01 2022 +0000"
      },
      "message": "feat: tftf realm extension\n\nThis patch adds Realm payload management capabilities to TFTF\nto act as a NS Host, it includes creation and destruction of a Realm,\nmapping of protected data and creation of all needed RTT levels,\nsharing of NS memory buffer from Host to Realm by mapping of\nunprotected IPA, create REC and auxiliary granules, exit Realm\nusing RSI_HOST_CALL ABI.\n\nOlder realm_payload name is used now for only R-EL1 test cases,\nRMI and SPM test cases have been moved to new file tests-rmi-spm.\n\nNew TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk,\nas an offset from where R-EL1 payload memory resources start.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7\n"
    }
  ]
}