)]}' { "log": [ { "commit": "8c65f72e903377d42b78239eefc6e0d78166e8c1", "tree": "8f22d22a7d7b900ac1c1d2da36f067006f6f1371", "parents": [ "970eb05ce05d9b01fd48fb420701a3145a50e223", "250fccc9557e7a746a304a17e192c9d1d4894138" ], "author": { "name": "Mark Dykes", "email": "mardyk01@review.trustedfirmware.org", "time": "Wed Oct 14 15:14:15 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 14 15:14:15 2020 +0000" }, "message": "Merge \"TFTF: Fix maximum number of CPUs in DSU cluster\"" }, { "commit": "970eb05ce05d9b01fd48fb420701a3145a50e223", "tree": "d52d49aade8fa01f7d3aa7edcca19abec54c67ab", "parents": [ "d35576f5fb6e060df19648f7e2a5143b11ad7285", "109d5c1b53779b18c98aa21d959d1182164b2eb7" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Oct 14 14:33:55 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 14 14:33:55 2020 +0000" }, "message": "Merge \"Remove dependencies from FVP to generic code\"" }, { "commit": "d35576f5fb6e060df19648f7e2a5143b11ad7285", "tree": "59c6b80b9f46b0a8dfe1986b2e86444c265fe9b2", "parents": [ "da5f4e36b2bb34f4df3b7ddb3f5424005b8f5bb4", "42318aa055e813a509be1710c6730234bec5698d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Oct 12 14:37:52 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 12 14:37:52 2020 +0000" }, "message": "Merge \"Add test for SDEI RM_ANY routing mode\"" }, { "commit": "109d5c1b53779b18c98aa21d959d1182164b2eb7", "tree": "ac7a65620ecba8d80bef1abe2462b3494c944688", "parents": [ "da5f4e36b2bb34f4df3b7ddb3f5424005b8f5bb4" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Sep 04 12:52:23 2020 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 09 15:17:01 2020 +0000" }, "message": "Remove dependencies from FVP to generic code\n\nSome generic parts of TFTF have dependencies from FVP platform\nmacros which can cause some trouble when porting the tests to a\ndifferent platform.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I11eb1af142b8c0ee1de2fcc8f298658bceedf306\n" }, { "commit": "42318aa055e813a509be1710c6730234bec5698d", "tree": "59c6b80b9f46b0a8dfe1986b2e86444c265fe9b2", "parents": [ "da5f4e36b2bb34f4df3b7ddb3f5424005b8f5bb4" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Thu Sep 17 19:46:01 2020 -0500" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Wed Oct 07 18:22:49 2020 +0000" }, "message": "Add test for SDEI RM_ANY routing mode\n\nPreviously, there were no tests using the RM_ANY routing mode. That\nparticular flag doesn\u0027t affect code flow very much, it\u0027s mainly used\nfor GIC configuration of the interrupt, so this is a test of basic\nfunctionality.\n\nThis test case makes sure RM_ANY event registrtation works and that\nevents can be routed to all CPUs. It does this by registering an SDEI\nevent with the RM_ANY flag, powering up all CPUs, then generating\nevents. Each time a CPU receives an event it shuts off and the process\nrepeats. Every CPU must receive a single event or the test will not\npass.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I1ebd0565158d93bddbf58d680d4696086ac00234\n" }, { "commit": "250fccc9557e7a746a304a17e192c9d1d4894138", "tree": "ba10cbde56d6ee01e0f25cff249f0f162a141bea", "parents": [ "da5f4e36b2bb34f4df3b7ddb3f5424005b8f5bb4" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Oct 05 13:48:26 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Oct 05 13:56:38 2020 +0100" }, "message": "TFTF: Fix maximum number of CPUs in DSU cluster\n\nAccording to \"Combinations of cores\" section in the\nArm DynamIQ Shared Unit Technical Reference Manual,\nplatforms with CPUs inside DynamIQ Shared Unit (DSU)\ncan have up to 8 CPUs in a cluster. One of the examples\nof such platform is FVP_Base_Cortex-A55x4+Cortex-A76x2\nwhich is used in CI tests. When running TFTF, test detects\nonly 4 Cortex-A55 CPUs and other 2 Cortex-A76 CPUs are\nkept in power off state:\nNOTICE: Cluster #0 [4 CPUs]\nNOTICE: CPU #0 [MPID: 0x1000000]\nNOTICE: CPU #1 [MPID: 0x1000100]\nNOTICE: CPU #2 [MPID: 0x1000200]\nNOTICE: CPU #3 [MPID: 0x1000300]\nTFTF FVP topology for CPUs with single threads supports up to 4\nclusters with up to 4 CPUs per cluster (default configuration\nis 2 x 4) and thus cannot detect 2 extra CPUs in the same cluster.\nThis patch fixes this issue by setting maximum number of CPUs\nin DSU cluster to 8.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I18acd1728e566cabb2331c988a2da972f8be3aae\n" }, { "commit": "da5f4e36b2bb34f4df3b7ddb3f5424005b8f5bb4", "tree": "08692f8cbc1218bd33a3e31da6c82d0d443050a9", "parents": [ "4f4943ad9d468e441f537bc5c963c394f52bcd22", "c654018adeb890ee52fb0bd4d44d6e0c060e6160" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Sep 25 15:04:14 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 25 15:04:14 2020 +0000" }, "message": "Merge \"docs/Makefile: use conditional assignment on sphinx variables\"" }, { "commit": "c654018adeb890ee52fb0bd4d44d6e0c060e6160", "tree": "24abfd679aeb4a06d6a040704452b8e8bf68bcc6", "parents": [ "642d8b60264aacefdcba56056d0181f1cff0d2a6" ], "author": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Fri Sep 11 13:13:13 2020 -0500" }, "committer": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Fri Sep 25 08:58:24 2020 -0500" }, "message": "docs/Makefile: use conditional assignment on sphinx variables\n\nIf \u0027makefile\u0027 variables are expected to be overwritten by environment\nand/or command line, it is better to use conditional assignment (\u0027?\u003d\u0027)\nso it clearly indicates the variable intention and usage.\n\nChange-Id: I890f71fe4bb26b5777b49e9904a1489ca8fad498\nSigned-off-by: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\n" }, { "commit": "4f4943ad9d468e441f537bc5c963c394f52bcd22", "tree": "314a2a5297650b9fda42f8ef4ca33ead3242ff1d", "parents": [ "86c45a6cedc5bd572efe5f0b8a356ce5fc9aac36", "770b431ce02750602aafa2ecced66e0f55a0055d" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Sep 24 21:37:26 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 24 21:37:26 2020 +0000" }, "message": "Merge \"makefile: silent help target\"" }, { "commit": "86c45a6cedc5bd572efe5f0b8a356ce5fc9aac36", "tree": "1367885078fad1a1ef2a3ac1e90dd30c44969908", "parents": [ "ef32e04ee4a65eea098b57be3428c973338b7760", "6b3840a0632c0a554ad5312de0a59bfc30867f42" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Sep 23 20:16:58 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 23 20:16:58 2020 +0000" }, "message": "Merge changes I37626f90,I26555391\n\n* changes:\n cactus: implement hvc call to get interrupt id\n cactus: add exception/interrupt framework\n" }, { "commit": "6b3840a0632c0a554ad5312de0a59bfc30867f42", "tree": "1367885078fad1a1ef2a3ac1e90dd30c44969908", "parents": [ "458d5534ef40440b29a5e9607732d588bed05274" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Sep 15 22:31:58 2020 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Sep 23 12:30:08 2020 +0100" }, "message": "cactus: implement hvc call to get interrupt id\n\nSince an SP cannot access GIC directly, it relies on SPMC(S-EL2) to\nget the interrupt ID.\nThis patch introduces a new hvc call \"SPM_INTERRUPT_GET\" to get\ninterrupt ID in S-EL1.\n\nChange-Id: I37626f907174ae57a24dc6b86e89d26ba8ebbddf\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "458d5534ef40440b29a5e9607732d588bed05274", "tree": "5cd5c8767b054f2012d0be5511647b0e8e2a0ed6", "parents": [ "ef32e04ee4a65eea098b57be3428c973338b7760" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jun 09 17:56:20 2020 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Sep 23 11:09:53 2020 +0100" }, "message": "cactus: add exception/interrupt framework\n\nThis patch adds following changes to cactus\n 1. Set up exception vector base address.\n 2. Add skeleton interrupt handler.\n 3. Install default tftf cpu exception handler.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I265553918b45a0e7e80ef0d7c48c09abfbec1a5f\n" }, { "commit": "ef32e04ee4a65eea098b57be3428c973338b7760", "tree": "1fb685bae3c1849dc64146e938c486ec736c9c8d", "parents": [ "b43e2c8ed33a3e5aff46ce8fccd0e776da2c09af", "05a577e0a28d6ac68b6505c62162e160fc960668" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Sep 23 09:14:50 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 23 09:14:50 2020 +0000" }, "message": "Merge \"cactus: remove deprecated hypervisor calls\"" }, { "commit": "05a577e0a28d6ac68b6505c62162e160fc960668", "tree": "1fb685bae3c1849dc64146e938c486ec736c9c8d", "parents": [ "b43e2c8ed33a3e5aff46ce8fccd0e776da2c09af" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Sep 15 10:20:19 2020 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Sep 22 14:24:25 2020 +0000" }, "message": "cactus: remove deprecated hypervisor calls\n\nHafnium provided VM get count and vcpu get count hypervisor calls which\nare now deprecated [1]. The preference is to use FFA_PARTITION_INFO_GET\ndiscovery ABI.\n\n[1] https://git.trustedfirmware.org/hafnium/hafnium.git/\ncommit/?id\u003dae3840dbc9372fd407893f32a5d624828c8933ae\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Idad95a0804a05d845dc45c2a0f0463f0120d4815\n" }, { "commit": "b43e2c8ed33a3e5aff46ce8fccd0e776da2c09af", "tree": "c5aadd3fde1dfcf08e9c2e9dcbaf849a9b552b7f", "parents": [ "642d8b60264aacefdcba56056d0181f1cff0d2a6", "73d81cf12f362e7cf80d0b9cc214b7e0d3ffb3c4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Sep 22 09:50:45 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 22 09:50:45 2020 +0000" }, "message": "Merge changes from topic \"od/ffa-id\"\n\n* changes:\n cactus: break the message loop on bad message request\n cactus: re-align secure partition id\n cactus: adjust the number of EC context to max number of PEs\n" }, { "commit": "73d81cf12f362e7cf80d0b9cc214b7e0d3ffb3c4", "tree": "c5aadd3fde1dfcf08e9c2e9dcbaf849a9b552b7f", "parents": [ "0be4abe25703475fa011257c9cd8ff8031d900b2" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Sep 15 16:57:00 2020 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Sep 17 12:18:05 2020 +0200" }, "message": "cactus: break the message loop on bad message request\n\nWhen the FF-A direct message request is not received as expected\nprefer breaking the message loop and panicing rather than replying\nwith the FF-A error ABI to the SPMC. It is improper to use this\nlatter ABI in context of Hafnium as this is treated as an invalid\nSMC issued by the SP.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I77cd0831a850e775f9996f4ecd1b5a81e6244a53\n" }, { "commit": "0be4abe25703475fa011257c9cd8ff8031d900b2", "tree": "23b4abd16ced158f59ccaa6bdfdafb541a89335f", "parents": [ "d43775e1d6165016f03564f259fc474c67b9cb33" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 04 11:26:13 2020 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Sep 17 12:18:02 2020 +0200" }, "message": "cactus: re-align secure partition id\n\nAccording to [1] and [2] secure partition ids are defined from\n0x8001 to 0xfffe. Update the cactus test payload and TFTF such\nthat it uses the appropriate IDs.\n0x8000 and 0xffff are reserved FF-A IDs respectively for the SPMC\nand the SPMD.\nConversely in the NWd, the Hypervisor ID is 0 and VMs are numbered\nin the range of 1 to 0x7fff.\n\n[1] https://trustedfirmware-a.readthedocs.io/en/latest/components/\nsecure-partition-manager.html#ffa-id-get\n[2] https://review.trustedfirmware.org/c/hafnium/hafnium/+/5165\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I3e9786212b227e6637a7650e60ddc4e59ad05a46\n" }, { "commit": "d43775e1d6165016f03564f259fc474c67b9cb33", "tree": "0b3de574c30a9edb2736575613b8ea61323e7943", "parents": [ "642d8b60264aacefdcba56056d0181f1cff0d2a6" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Sep 15 17:19:44 2020 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Sep 15 17:22:52 2020 +0200" }, "message": "cactus: adjust the number of EC context to max number of PEs\n\nAccording to [1] and in context of FF-A v1.0 a secure partition must\nhave either one EC (migratable UP) or a number of ECs equal to the\nnumber of PEs (pinned MP). Adjust the cactus manifest execution-context\nfields to maximum number of PEs.\n\n[1] https://trustedfirmware-a.readthedocs.io/en/latest/components/\nsecure-partition-manager.html#platform-topology\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I79aec4b685c8774acb9b52dd6b05674cebc6ad2e\n" }, { "commit": "770b431ce02750602aafa2ecced66e0f55a0055d", "tree": "8b7f43a4b171221fca28567b578d5e86dab00b57", "parents": [ "642d8b60264aacefdcba56056d0181f1cff0d2a6" ], "author": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Fri Sep 11 14:44:40 2020 -0500" }, "committer": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Fri Sep 11 14:46:55 2020 -0500" }, "message": "makefile: silent help target\n\nInstead of prefixing the \u0027do not echo command\u0027 \u0027@\u0027, make help as\nprerequisite of .SILENT. This avoids prefixing \u0027@\u0027 in future help\nmessages.\n\nChange-Id: If33b82b4d3bccc92e8de74703ff6af04387008a0\nSigned-off-by: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\n" }, { "commit": "642d8b60264aacefdcba56056d0181f1cff0d2a6", "tree": "e131a3f937af72a759d1afa4ce73cb913b6d6fa8", "parents": [ "aaca1c848767e2bb7935887dca3d540bdc9e6d77", "9473007967d34fede067dcb55849e0901da44688" ], "author": { "name": "Mark Dykes", "email": "mardyk01@review.trustedfirmware.org", "time": "Thu Sep 03 14:33:37 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 03 14:33:37 2020 +0000" }, "message": "Merge \"Minor bug fixes in multicore IRQ spurious test\"" }, { "commit": "9473007967d34fede067dcb55849e0901da44688", "tree": "e131a3f937af72a759d1afa4ce73cb913b6d6fa8", "parents": [ "aaca1c848767e2bb7935887dca3d540bdc9e6d77" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jun 08 16:59:38 2020 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Sep 02 11:54:08 2020 -0500" }, "message": "Minor bug fixes in multicore IRQ spurious test\n\nProgram the memory mapped GIC_ITARGETSR register with appropriate\ncpu mask and assert the expected value is returned upon reading\nthe register.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I356111d763569c229d7f4c9ea3cd4899305a4954\n" }, { "commit": "aaca1c848767e2bb7935887dca3d540bdc9e6d77", "tree": "95e65857114d1e6aa26aefdee5880c26470b4053", "parents": [ "7d6592b8e7668fde38d304ebffcf9945dc4201a8", "d8711ca47b9ba7461bf0078568e9cab1f6141ce4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Aug 20 22:59:36 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 20 22:59:36 2020 +0000" }, "message": "Merge \"Makefile: add missing help_tests info on help target\"" }, { "commit": "7d6592b8e7668fde38d304ebffcf9945dc4201a8", "tree": "a0f6eac3d1ec9ebc608032b22048a7c75b4b518b", "parents": [ "0d7ee81bd3ec4490b9870e3a2805082cc3dbe56c", "bd0a7e49d0f2b690ab5c1d8fbdac5bcb257f5183" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Aug 19 23:55:55 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 19 23:55:55 2020 +0000" }, "message": "Merge \"Cactus: Map RXTX region to third partion.\"" }, { "commit": "0d7ee81bd3ec4490b9870e3a2805082cc3dbe56c", "tree": "4755bfe082a4761e501fe2f8f1287b237166b0aa", "parents": [ "0a14ff96c8d0aa2567d3c6d1725a75a70322331d", "d75596a2462f4dc9f707e71995576e5ffbb01a65" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Aug 19 23:52:05 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 19 23:52:05 2020 +0000" }, "message": "Merge \"Cactus: Add third partion to ffa tests\"" }, { "commit": "0a14ff96c8d0aa2567d3c6d1725a75a70322331d", "tree": "2cdf8b989e088adec9e6e7fb0ecfad662ba0d0fc", "parents": [ "953ec59b3ed74380c690e550c85eefe19b07716f", "93119e3f5c91e6d79b6c917de41091880a2dc2d7" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Aug 19 23:51:27 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 19 23:51:27 2020 +0000" }, "message": "Merge \"Cactus: Create tertiary partition\"" }, { "commit": "bd0a7e49d0f2b690ab5c1d8fbdac5bcb257f5183", "tree": "a0f6eac3d1ec9ebc608032b22048a7c75b4b518b", "parents": [ "d75596a2462f4dc9f707e71995576e5ffbb01a65" ], "author": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Fri Jul 17 16:42:21 2020 +0100" }, "committer": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Wed Aug 19 11:06:26 2020 +0000" }, "message": "Cactus: Map RXTX region to third partion.\n\nWhen the third cactus partition is booted, map the RXTX\nregion using the FFA_RXTX_MAP ABI. If this is successful,\npoint the mailbox to this RXTX region.\n\nSigned-off-by: Ruari Phipps \u003cruari.phipps@arm.com\u003e\nChange-Id: Ifbe3bc70b187f75f29ef66356e714e8a905d2db8\n" }, { "commit": "d75596a2462f4dc9f707e71995576e5ffbb01a65", "tree": "4755bfe082a4761e501fe2f8f1287b237166b0aa", "parents": [ "93119e3f5c91e6d79b6c917de41091880a2dc2d7" ], "author": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Fri Jul 17 16:41:34 2020 +0100" }, "committer": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Wed Aug 19 11:06:21 2020 +0000" }, "message": "Cactus: Add third partion to ffa tests\n\nAdd the third partition to the ffa_partition_info_get test to test\nthat a partition can successfully get information about the third cactus\npartition\n\nSigned-off-by: Ruari Phipps \u003cruari.phipps@arm.com\u003e\nChange-Id: Ib8c69f16e217f9631be005c7759753d05704afd2\n" }, { "commit": "93119e3f5c91e6d79b6c917de41091880a2dc2d7", "tree": "2cdf8b989e088adec9e6e7fb0ecfad662ba0d0fc", "parents": [ "953ec59b3ed74380c690e550c85eefe19b07716f" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Wed Jul 01 14:09:48 2020 +0100" }, "committer": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Wed Aug 19 11:06:09 2020 +0000" }, "message": "Cactus: Create tertiary partition\n\nIn order to test the RXTX_MAP API a tertiary cactus partition without a\nRX_TX region specified in its manifest is required. This patch adds this\nSP which is loaded at 0x730000. The primary and secondary SP\u0027s\nRX_TX regions are moved to allow for this.\n\nSigned-off-by: Ruari Phipps \u003cruari.phipps@arm.com\u003e\nChange-Id: Idefe4bd7b589e974a0f011ba702763cadfec5df9\n" }, { "commit": "d8711ca47b9ba7461bf0078568e9cab1f6141ce4", "tree": "38b67c48bcf9f5cd0ca9001e172bcedc4243791a", "parents": [ "953ec59b3ed74380c690e550c85eefe19b07716f" ], "author": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Tue Jul 14 11:00:31 2020 -0500" }, "committer": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Tue Aug 18 16:29:19 2020 -0500" }, "message": "Makefile: add missing help_tests info on help target\n\nAlthough \u0027help_tests\u0027 target has been present for a long time, it is\nnot shown on the main \u0027help\u0027 target output. This commits includes\nbasic \u0027help_tests\u0027 info on the latter, making it visible.\n\nSigned-off-by: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\nChange-Id: Ief510ae7f340207d416412f81e97e30017866b17\n" }, { "commit": "953ec59b3ed74380c690e550c85eefe19b07716f", "tree": "2293a7fcfa63ed11dd88b4bb65e1249f9052c79b", "parents": [ "56c3942b4eaa2ad85749b11d5895fad6bfb5b61c", "7fac162cd9439783ef60aaf266d22ad454445ace" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 18 14:55:16 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 18 14:55:16 2020 +0000" }, "message": "Merge changes from topic \"af/add_branch_protection_makefiles\"\n\n* changes:\n TFTF: Add ARMv8.5 BTI support in makefiles\n TFTF: Add ARMv8.5 BTI support in xlat_tables_v2 library\n TFTF: Add ARMv8.5 BTI support in assembler files\n TFTF: Add ARMv8.5 BTI-related definitions\n" }, { "commit": "7fac162cd9439783ef60aaf266d22ad454445ace", "tree": "0696ee3d15d1e4fcdfe3f1172f0c2c3dddc06ada", "parents": [ "d6fdb6b10147038d99643a7547821c3cff76ce76" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Jun 19 14:25:43 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Aug 18 14:52:49 2020 +0000" }, "message": "TFTF: Add ARMv8.5 BTI support in makefiles\n\nThis patch adds \u0027BRANCH_PROTECTION\u0027 build option in\nTFTF makefiles which corresponds to that in TF-A.\nThe option values are documented in \u0027build-options.rst\u0027\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Iad5083aee339cec574acf5e7ab1fd8142877a122\n" }, { "commit": "d6fdb6b10147038d99643a7547821c3cff76ce76", "tree": "dd15b765586801ebfaefd26a9c3883343f16a93b", "parents": [ "45ada40c895b1087de08c05d6d6a311cb0f47c79" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 17 19:13:42 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Aug 18 14:52:44 2020 +0000" }, "message": "TFTF: Add ARMv8.5 BTI support in xlat_tables_v2 library\n\nThis patch adds BTI-related changes in xlat_tables_v2 library\nwhich fully correspond to those in TF-A source tree.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I77f3ae7e9a365406ebb3edd500dbc71d3f07ecad\n" }, { "commit": "45ada40c895b1087de08c05d6d6a311cb0f47c79", "tree": "65a33e6efec3a2a0bb62d548bb76b876a9653cb1", "parents": [ "9cd75024bf2d3abb4e620f308d26876ee75c1c01" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 17 19:07:11 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Aug 18 14:52:39 2020 +0000" }, "message": "TFTF: Add ARMv8.5 BTI support in assembler files\n\nThis patch adds BTI support in assembler files\nwhich fully correspond to those in TF-A source tree.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ie6a7b248c967684c6b2b86b915f0499fe095bba3\n" }, { "commit": "9cd75024bf2d3abb4e620f308d26876ee75c1c01", "tree": "fbd4ae555fedfe921baf99f4e88a32c13fec8b05", "parents": [ "69cf580a8de8f2695ba1e178a327f29a42058842" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 17 18:54:20 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Aug 18 14:50:18 2020 +0000" }, "message": "TFTF: Add ARMv8.5 BTI-related definitions\n\nThis patch adds BTI-related definitions in header files\nwhich fully correspond to those in TF-A source tree.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I1ae4c13dab41b0099517dd1bead221909511f2fc\n" }, { "commit": "56c3942b4eaa2ad85749b11d5895fad6bfb5b61c", "tree": "464964bc7346ad41b5c6f30cbdc61690dcb97478", "parents": [ "a5799c9f986eb0deb4838e95bc535f7e1b04b117", "073a9e46483b51ecd45dbdbc39a5367523ff05f4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Aug 17 22:01:14 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 17 22:01:14 2020 +0000" }, "message": "Merge changes from topic \"tegra194-ras-tests\"\n\n* changes:\n Tegra194: support for RAS corrected error testing\n Tegra194: introduce RAS uncorrectable error injection tests\n" }, { "commit": "073a9e46483b51ecd45dbdbc39a5367523ff05f4", "tree": "464964bc7346ad41b5c6f30cbdc61690dcb97478", "parents": [ "83aa8e4b6d3abbaf43ab453c95befc3a8c281be8" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon May 11 16:45:56 2020 -0700" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Aug 17 21:39:10 2020 +0000" }, "message": "Tegra194: support for RAS corrected error testing\n\nThis patch introduces a test to inject RAS corrected errors for\nall supported nodes from all CPUs. On injecting an error, the CPU\nverifies that the error was detected with the help of an IRQ.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I4a679e432d36e20aac64e7062fbaab438e96dfc0\n" }, { "commit": "83aa8e4b6d3abbaf43ab453c95befc3a8c281be8", "tree": "510478efec0a8257c56d20dab899683aedf87dd0", "parents": [ "a5799c9f986eb0deb4838e95bc535f7e1b04b117" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Fri Apr 24 18:15:39 2020 -0700" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Aug 17 21:39:03 2020 +0000" }, "message": "Tegra194: introduce RAS uncorrectable error injection tests\n\nPlatform vendors have some tests that are specific to their platforms.\nThis patch introduces a test suite for Tegra194 platfoms. As the first\ntest, the platform will inject the RAS uncorrectable errors and verify\nthat the platform detects and reports them.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: Id7b26d35dd4c638c2bd92959f18f12423ec1fd8b\n" }, { "commit": "a5799c9f986eb0deb4838e95bc535f7e1b04b117", "tree": "73a49b79348416f4f4d66e1a911ef9c7b69c1a70", "parents": [ "ed1cb2842c7dbf604bff059c6c7f600d39721fe5", "67593f26957255948b159484d7e65c41315fde73" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Aug 14 15:58:31 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 14 15:58:31 2020 +0000" }, "message": "Merge \"SPM: Add owner to sp_layout gen\"" }, { "commit": "67593f26957255948b159484d7e65c41315fde73", "tree": "73a49b79348416f4f4d66e1a911ef9c7b69c1a70", "parents": [ "ed1cb2842c7dbf604bff059c6c7f600d39721fe5" ], "author": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Fri Jul 24 16:21:35 2020 +0100" }, "committer": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Wed Aug 12 08:16:31 2020 +0000" }, "message": "SPM: Add owner to sp_layout gen\n\nSigned-off-by: Ruari Phipps \u003cruari.phipps@arm.com\u003e\nChange-Id: Icd57ba44d81b7d6acfc6db4221c9a7e5f56e49df\n" }, { "commit": "ed1cb2842c7dbf604bff059c6c7f600d39721fe5", "tree": "fb57b5e6d44b1a2d793a84d8ca7516fa803b7ca2", "parents": [ "96ca5b1b4b77a16cc4d39e6afbffc46ff271c378", "86c3e442ab0a53ed10f433153f68f93830687bc6" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Aug 11 10:24:15 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 11 10:24:15 2020 +0000" }, "message": "Merge \"TFTF: Fix Aarch32 zeromem() function\"" }, { "commit": "96ca5b1b4b77a16cc4d39e6afbffc46ff271c378", "tree": "f543f84ced5126e59c15507f5a5479dcbd6a2a1b", "parents": [ "6bbe5a6dad046f048b1a0b320aa3d7489a0d378e", "9bc1ee80937bd3affc4384f7b6380e3b26b25fb3" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jul 28 21:14:14 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 28 21:14:14 2020 +0000" }, "message": "Merge \"Update SMCCC_ARCH_SOC_ID test case\"" }, { "commit": "6bbe5a6dad046f048b1a0b320aa3d7489a0d378e", "tree": "22ba49b11cc3d77f1bd98563afa06714d3e725e4", "parents": [ "8a669d956699e967ca7f298d4bf74111c10dd164", "5b5bc209f4fa16ff9efdb3ae2fe97d810463aab3" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jul 28 15:10:02 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 28 15:10:02 2020 +0000" }, "message": "Merge \"doc: use docker to build documentation\"" }, { "commit": "9bc1ee80937bd3affc4384f7b6380e3b26b25fb3", "tree": "de17544e0c4f57ebb6065accc74866fd3e629a6e", "parents": [ "8a669d956699e967ca7f298d4bf74111c10dd164" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Jul 23 20:30:25 2020 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jul 28 13:35:32 2020 +0100" }, "message": "Update SMCCC_ARCH_SOC_ID test case\n\nSkip the test result if SMCCC_ARCH_SOC_ID feature is not available\nfor the platform and also, return failure in case of SMCCC_ARCH_SOC_ID\nfeature is available but platform unable to provide either\nsoc-revision or soc-version information.\n\nChange-Id: I447adb78814a902a4344d98e4f7fafe67000316f\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "8a669d956699e967ca7f298d4bf74111c10dd164", "tree": "3ca54a71167a91304db18c5ee891ce2f831f03b6", "parents": [ "d07b682769c1861bf12ef3a9177c62796c5c9d2b", "57c6ddbfddeb0d5ebe27d62b426bb1029fe8d622" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jul 27 13:57:21 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 27 13:57:21 2020 +0000" }, "message": "Merge changes from topic \"ffa_tests\"\n\n* changes:\n Cactus: tidying FFA_VERSION test.\n Cactus: FFA_PARTITION_INFO_GET test.\n Cactus: FFA_FEATURES test.\n SPM: TFTF test of FFA_FEATURES interface.\n" }, { "commit": "57c6ddbfddeb0d5ebe27d62b426bb1029fe8d622", "tree": "3ca54a71167a91304db18c5ee891ce2f831f03b6", "parents": [ "c32f47899de53f58b08c549aff396062b256c029" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Wed Jul 01 14:09:48 2020 +0100" }, "committer": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Mon Jul 27 13:36:01 2020 +0100" }, "message": "Cactus: tidying FFA_VERSION test.\n\nMoving FFA_VERSION test to separate test function.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: I09f1ca726eddbcaba0416f981eae292ba88c64b4\n" }, { "commit": "c32f47899de53f58b08c549aff396062b256c029", "tree": "01a3353098f3d59ee75de560c45e8e5780cf8816", "parents": [ "40eb6a2ee493beb61d617f249af91e4f52453700" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Tue Jun 23 09:41:15 2020 +0100" }, "committer": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Mon Jul 27 13:36:01 2020 +0100" }, "message": "Cactus: FFA_PARTITION_INFO_GET test.\n\nCalls FFA_PARTITION_INFO_GET API from secure virtual FFA-A instance.\n * Gets information about primary SP.\n * Gets information about secondary SP.\n * Gets information about all SP running.\n * Attempts to get information about non-existing SP.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: Ief4de45b4d7decb1e1dba9bdb0e7e05516062dd2\n" }, { "commit": "40eb6a2ee493beb61d617f249af91e4f52453700", "tree": "55bf174271d54fad16fb0f1d7b1e25f67216f1cb", "parents": [ "c17c1d3ad278e007b551617be23b09e13b577ef0" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Mon Jun 08 11:15:30 2020 +0100" }, "committer": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Mon Jul 27 13:36:01 2020 +0100" }, "message": "Cactus: FFA_FEATURES test.\n\nCalls FFA_FEATURES API from the secure virtual FF-A instance which is serviced by SPMC.\nExpected responses should be edited according to the feature\nimplementation progress.\nRemoving obsolete SPRT version check and cactus_tests_misc.c as a\nresult.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: I8a2e569a3bce31a735e1af04994984fda2168296\n" }, { "commit": "c17c1d3ad278e007b551617be23b09e13b577ef0", "tree": "678e8f04c0832315e5a08062d0e32d063cc1625e", "parents": [ "d07b682769c1861bf12ef3a9177c62796c5c9d2b" ], "author": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Thu Jun 11 15:03:01 2020 +0100" }, "committer": { "name": "Max Shvetsov", "email": "maksims.svecovs@arm.com", "time": "Mon Jul 27 13:36:01 2020 +0100" }, "message": "SPM: TFTF test of FFA_FEATURES interface.\n\nForwards FFA_FEATURES call to SPMC via SPMD from the normal world.\nExpected responses should be edited according to the feature\nimplementation progress.\n\nSigned-off-by: Max Shvetsov \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: I057100b4086108b0779e3fa76fbd86e0818f765c\n" }, { "commit": "86c3e442ab0a53ed10f433153f68f93830687bc6", "tree": "1e8456f80c2b0a5db69abd07284418085bbb4ca7", "parents": [ "ec87d759429e9496947aa917e012f85e98d9d5fa" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Jul 17 17:03:25 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jul 23 12:57:40 2020 +0100" }, "message": "TFTF: Fix Aarch32 zeromem() function\n\nThis patch fixes the following bugs in zeromem() Aarch32 variant:\n- Removed ASM_ASSERT for length parameter passed in R1 register.\n This is causing assertion in tftf_entrypoint() code\n \tldr\tr0, \u003d__BSS_START__\n\tldr\tr1, \u003d__BSS_SIZE__\n\tbl\tzeromem\n when __BSS_SIZE__ is not 4-byte aligned:\n 0x000000000000cced __BSS_SIZE__ \u003d SIZEOF (.bss)\n- With ENABLE_ASSERTIONS \u003d 0 for RELEASE builds and R1 not 4-bytes\n aligned zeromem() was writing 0 into all the memory in infinite\n z_loop, because of the code:\n z_loop:\n\tcmp\tr2, r0\n\tbeq\tz_end\n\tstr\tr1, [r0], #4\n\tb\tz_loop\n with R0 being increased by 4 on each step and R2 \u003d R0 condition\n would never be met.\n- BLT instruction was used for \u0027unsigned int length\u0027 value in R1\n changed to BLO.\nThis patch also fixes BLO instruction bug in \u0027memcpy4()\u0027 and function\nitself is optimised.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I8128399681def8ba80241882e355c3ca2778605f\n" }, { "commit": "d07b682769c1861bf12ef3a9177c62796c5c9d2b", "tree": "e08d4e061f3ad6d4ff43a1f07eb3b59dd0095cb1", "parents": [ "69cf580a8de8f2695ba1e178a327f29a42058842", "ef507e4a7dc99a992f78eeed25f8f51408cc0f8f" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jul 21 14:56:29 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 21 14:56:29 2020 +0000" }, "message": "Merge \"plat/arm: Move defines to platform specific header file\"" }, { "commit": "ef507e4a7dc99a992f78eeed25f8f51408cc0f8f", "tree": "e08d4e061f3ad6d4ff43a1f07eb3b59dd0095cb1", "parents": [ "69cf580a8de8f2695ba1e178a327f29a42058842" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jun 05 08:41:42 2020 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Jul 20 17:07:03 2020 +0000" }, "message": "plat/arm: Move defines to platform specific header file\n\nSome platform specific defines found in \u0027fwu_nvm.h\u0027 header\nhence moved such define to platform specific header file.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I1cfd1c95306e2ded5b78d1d6424ad159a958c502\n" }, { "commit": "5b5bc209f4fa16ff9efdb3ae2fe97d810463aab3", "tree": "2bf110dfeb2b735daa08c18f1ff6cb65af9bd344", "parents": [ "8499afc44a1642b50fce554d4fdc9356d07d53a0" ], "author": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Tue Jul 14 10:05:23 2020 -0500" }, "committer": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Fri Jul 17 09:49:21 2020 -0500" }, "message": "doc: use docker to build documentation\n\ndocker (container) is another way to build the documentation and fortunately\nthere is already a docker image (sphinxdoc/sphinx) with sphinx so we can use\nit to generate the documentation.\n\nChange-Id: I33fba6c5e4810e20546559c80a8f2eecabd4c123\nSigned-off-by: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\n" }, { "commit": "69cf580a8de8f2695ba1e178a327f29a42058842", "tree": "af6040068c0a3e6c23132a9a022fbe0411516d4c", "parents": [ "ec87d759429e9496947aa917e012f85e98d9d5fa", "d9fcb247c43e326808eb46a01b23059477b55b56" ], "author": { "name": "joanna.farley", "email": "joanna.farley@arm.com", "time": "Fri Jul 17 13:23:33 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jul 17 13:23:33 2020 +0000" }, "message": "Merge \"remove dashes and and sort tests\"" }, { "commit": "ec87d759429e9496947aa917e012f85e98d9d5fa", "tree": "e5927286f0ba0ce3feca173b9538d959394baa08", "parents": [ "8499afc44a1642b50fce554d4fdc9356d07d53a0", "29278a9151fe90167ef57d5edc93e3e7551b65ff" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 15 09:47:35 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 15 09:47:35 2020 +0000" }, "message": "Merge \"TFTF doesn\u0027t need to boot Secondary Cactus\"" }, { "commit": "d9fcb247c43e326808eb46a01b23059477b55b56", "tree": "febf223f10ca780ab4098ddab69d098c91aa930c", "parents": [ "8499afc44a1642b50fce554d4fdc9356d07d53a0" ], "author": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Tue Jul 14 11:09:45 2020 -0500" }, "committer": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Tue Jul 14 11:09:45 2020 -0500" }, "message": "remove dashes and and sort tests\n\nremove dashes on \u0027make help_tests\u0027 output aligns a bit more to main \u0027make\nhelp\u0027 output. Also, sort tests sets so users find quicker the name of the test.\n\nSigned-off-by: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\nChange-Id: If09992ddff95865233b1a311f9a52600d3756556\n" }, { "commit": "8499afc44a1642b50fce554d4fdc9356d07d53a0", "tree": "39d20b7fa667cb25499839fba56cfe69afcc1fe7", "parents": [ "fd7c7978cfee3138a645a2014b02562f94aef141", "986de72ace2591794f20ecce499593c6149c328e" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jul 08 08:55:18 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 08 08:55:18 2020 +0000" }, "message": "Merge \"Add explicit barrier before sev() in tftf_send_event_common API\"" }, { "commit": "986de72ace2591794f20ecce499593c6149c328e", "tree": "39d20b7fa667cb25499839fba56cfe69afcc1fe7", "parents": [ "fd7c7978cfee3138a645a2014b02562f94aef141" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Sat Jul 04 01:23:50 2020 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Sat Jul 04 01:27:38 2020 -0500" }, "message": "Add explicit barrier before sev() in tftf_send_event_common API\n\nConsider the following scenario: If sev() gets reordered above the\nevent-\u003ecnt+\u003dinc operation in tftf_send_event_common() on core 0, and lets\nsay core 1 is in wfe in tftf_wait_for_event, core 1 receives the event\nbefore the write to event-\u003ecnt from core 0 propagates to core 1. Later,\ncore 1 wakes up, reads event-\u003ecnt, sees that it is 0 and goes back to\nwfe, thereby leading to hang.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I2e8a5ab7c220b02d5b637dc7cdf3562ca73dbfdc\n" }, { "commit": "fd7c7978cfee3138a645a2014b02562f94aef141", "tree": "7a920da8b19af364185346d79ad1ce05834a0c3b", "parents": [ "da6ac4e88966d81ec8bef22714ac1c0e787f176a", "df954c91755578994be898e718cfe32f84b94498" ], "author": { "name": "Mark Dykes", "email": "mardyk01@review.trustedfirmware.org", "time": "Thu Jul 02 14:53:20 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jul 02 14:53:20 2020 +0000" }, "message": "Merge \"TFTF: Fix regions\u0027 mapping with no NS bit set\"" }, { "commit": "da6ac4e88966d81ec8bef22714ac1c0e787f176a", "tree": "6ad204bf24455fd657ab45432b9905d5c8a469a4", "parents": [ "424e11b5224a5f474a657ccb6057a0ffa43c2d60", "abf254fdd443ba98f23bf0fd8c51991533cd50a7" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Wed Jul 01 17:04:23 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 17:04:23 2020 +0000" }, "message": "Merge \"include \u0027path/to\u0027 prefix when specifying tftf.bin on make fip cmd\"" }, { "commit": "424e11b5224a5f474a657ccb6057a0ffa43c2d60", "tree": "6f318e682e171a3aed3949e79bc5e40d7d9e35d1", "parents": [ "7130a74a9a3f31cf6630ebc684096f8432583c42", "a9a1f27df544625a9d726b1209d0a607d5bc0249" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jul 01 07:00:12 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 07:00:12 2020 +0000" }, "message": "Merge \"sgi575: Reenable PSCI NODE_HW_STATE test\"" }, { "commit": "7130a74a9a3f31cf6630ebc684096f8432583c42", "tree": "a5b008cabfbe0c35c3177c8caa4101e4d97b253f", "parents": [ "a117303c1eeab7599588eab35f220eaeca282a24", "7cc2587da605299e175444350c064c589ad09803" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 30 23:09:06 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 23:09:06 2020 +0000" }, "message": "Merge \"TFTF: get FVP platform\u0027s topology from build options\"" }, { "commit": "29278a9151fe90167ef57d5edc93e3e7551b65ff", "tree": "d603e87c26482243003a36dc3dffd8e5b0c9095e", "parents": [ "a117303c1eeab7599588eab35f220eaeca282a24" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jun 15 16:56:50 2020 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jun 30 10:42:58 2020 +0100" }, "message": "TFTF doesn\u0027t need to boot Secondary Cactus\n\nRemoved code that was booting Cactus Secondary, using FFA_RUN interface\nfrom TFTF\u0027s SPM tests. Hafnium now boots all partitions according to\n\"boot-order\" field value in the partition manifests.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I31a3507c92bffe81f78036da121259a5c19924cd\n" }, { "commit": "abf254fdd443ba98f23bf0fd8c51991533cd50a7", "tree": "d0b4c4b1db776b3f97203147e394f566db13b0b2", "parents": [ "a117303c1eeab7599588eab35f220eaeca282a24" ], "author": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Mon Jun 29 17:46:28 2020 -0500" }, "committer": { "name": "Leonardo Sandoval", "email": "leonardo.sandoval@linaro.org", "time": "Mon Jun 29 17:51:28 2020 -0500" }, "message": "include \u0027path/to\u0027 prefix when specifying tftf.bin on make fip cmd\n\nSigned-off-by: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\nChange-Id: I7c316acd486346332403c758f632147ab71c48f2\n" }, { "commit": "a9a1f27df544625a9d726b1209d0a607d5bc0249", "tree": "fa296afc4257cb4a4ec79e1e595f1a0b64ae163d", "parents": [ "a117303c1eeab7599588eab35f220eaeca282a24" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Fri Jun 26 14:50:40 2020 -0500" }, "committer": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Fri Jun 26 14:50:40 2020 -0500" }, "message": "sgi575: Reenable PSCI NODE_HW_STATE test\n\nThis test was disabled here:\nhttps://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/3672\n\nThis was due to an outdated SCP firmware version causing it to fail. The\nSCP binaries have been updated and this test no longer fails, so it can\nbe safely reenabled.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Ieb647a1416eb99832a560c54c9e8f7d8fbbbc707\n" }, { "commit": "a117303c1eeab7599588eab35f220eaeca282a24", "tree": "0ca38bdab3923590118507c80ac349a3f462f5d7", "parents": [ "036854b119f7d055dfc04266d11377af27a313fe", "5aecd986f29140537d6a95f8e1961ecae57139e6" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jun 26 12:37:36 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 26 12:37:36 2020 +0000" }, "message": "Merge \"Tidying FFA helpers\"" }, { "commit": "5aecd986f29140537d6a95f8e1961ecae57139e6", "tree": "e15f9641fc902dc862c9aebc0f06ead0563ed286", "parents": [ "a09f6365152c08d7c8285a4841b0c0c3bb39bb0d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jun 11 10:25:33 2020 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Jun 26 13:04:01 2020 +0100" }, "message": "Tidying FFA helpers\n\nMoved SP specific functions/macros to \"sp_helpers.c/h\".\nPlaced ffa interfaces/symbols shared between tftf and SPs in\n\"ffa_helpers.c/h\".\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I4cf967f87837ce3e7d0f7244f9cc0677f608f9cd\n" }, { "commit": "036854b119f7d055dfc04266d11377af27a313fe", "tree": "291485dc4c3047a62a1a034cbb507d7c46724495", "parents": [ "a09f6365152c08d7c8285a4841b0c0c3bb39bb0d", "24a4a7c5b3158804c866d3c7b43b9e1314b474f4" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jun 26 08:36:27 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 26 08:36:27 2020 +0000" }, "message": "Merge \"Update FIP corrupt address\"" }, { "commit": "a09f6365152c08d7c8285a4841b0c0c3bb39bb0d", "tree": "65d13a6ff55542e4a3cd511beac65b4e02e1c4d7", "parents": [ "87c9a5cc97c16f6c1c991fab334bfed4e4fce296", "9f6f01476c93631455f2a50096574dd98505e830" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 23 15:12:18 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 23 15:12:18 2020 +0000" }, "message": "Merge changes from topic \"spm_ffa_version\"\n\n* changes:\n Cactus: FFA Version Test\n SPM: TFTF test of FFA_VERSION interface\n" }, { "commit": "9f6f01476c93631455f2a50096574dd98505e830", "tree": "65d13a6ff55542e4a3cd511beac65b4e02e1c4d7", "parents": [ "8f08a05490ed3ce474cc821297929bf8df5691d2" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jun 17 15:37:59 2020 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Jun 19 11:36:41 2020 +0100" }, "message": "Cactus: FFA Version Test\n\nAdded simple test of the FFA interface to cactus:\n- FFA version ABI helper;\n- New test file for test to FFA ABIs;\n- Invoking \"ffa_tests\" from cactus main.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I8c8445ad6d9da79f1880d143836e7a6da68eaff7\n" }, { "commit": "8f08a05490ed3ce474cc821297929bf8df5691d2", "tree": "da0afb6bc23221c8fd9efe95b6fdc559245a7987", "parents": [ "87c9a5cc97c16f6c1c991fab334bfed4e4fce296" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 26 17:14:40 2020 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Jun 19 09:34:30 2020 +0100" }, "message": "SPM: TFTF test of FFA_VERSION interface\n\nImplemented test to FFA_VERSION interface:\n- \"test_ffa_version.c\" contains functions to test FFA_VERSION ABI;\n- Test suite for FFA_VERSION ABI in tests-spm.xml;\n- Helper macros changed in \"ffa_helpers.h\".\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I6b0e937e30fceaa21a57c4ba0761a62049b16c0d\n" }, { "commit": "df954c91755578994be898e718cfe32f84b94498", "tree": "51b1c5627c792ed95122423cb6485dffd6a9a6db", "parents": [ "87c9a5cc97c16f6c1c991fab334bfed4e4fce296" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 17 15:37:17 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 17 15:37:17 2020 +0100" }, "message": "TFTF: Fix regions\u0027 mapping with no NS bit set\n\nThis patch fixes the bug in tftf_plat_configure_mmu()\nfunction (tf-a-tests\\plat\\common\\plat_common.c) which\nis missing setting MT_NS attribute flag when maps\nCode, RO data and RW Data + BSS memory regions, causing\nthem to be reported as Secure memory:\n [LV3] VA:0x88000000 PA:0x88000000 size:0x1000 MEM-RO-EXEC-S\n...\n [LV3] VA:0x88016000 PA:0x88016000 size:0x1000 MEM-RO-XN-S\n...\n [LV3] VA:0x88020000 PA:0x88020000 size:0x1000 MEM-RW-XN-S\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: If64aa65179ffe223d3e6f1c6bf73a7e4ce7fa536\n" }, { "commit": "87c9a5cc97c16f6c1c991fab334bfed4e4fce296", "tree": "bf3c91e4eebda0e129be310642d0ebdaad9302ee", "parents": [ "5861730b3d6333f936c2fcecaa034de0391cbd94", "00ed5a4b3b0ddfeb925708e3afb037cc89ebd816" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 09 14:39:45 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 09 14:39:45 2020 +0000" }, "message": "Merge changes from topic \"tegra194-platform-support\"\n\n* changes:\n tests: arm_arch_svc: introduce support for NVIDIA Denver CPUs\n Tegra194: introduce per-CPU Hypervisor Timer Interrupt ID\n Tegra194: skip some timer framework validation tests\n Tegra194: introduce watchdog timer\n Tegra194: timers: increase the step value to 5ms\n Tegra194: create dummy SMMU context for system resume\n Tegra194: introduce system reset\n Tegra194: disable some system suspend test cases\n Tegra194: skip CPU suspend tests requiring SGI as wake source\n Tegra194: wake: introduce support for RTC as wake source\n Tegra194: pwr_mgmt: introduce power management support\n plat: nvidia: introduce platform port for Tegra194\n drivers: ti: uart: introduce UART 16550 driver\n" }, { "commit": "24a4a7c5b3158804c866d3c7b43b9e1314b474f4", "tree": "363dc9c31c55c5e25d1f58f38e7dad4627ae48fe", "parents": [ "5861730b3d6333f936c2fcecaa034de0391cbd94" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jun 05 08:41:42 2020 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jun 09 13:24:39 2020 +0100" }, "message": "Update FIP corrupt address\n\nUpdated \"FIP_CORRUPT_OFFSET\" address which is used to corrupt\nBL2 in FIP. This address is being changed due to addition\nof fw-config image in FIP.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I003ccf9ba80b50646ed732b9306e5be757dbf4ff\n" }, { "commit": "00ed5a4b3b0ddfeb925708e3afb037cc89ebd816", "tree": "bf3c91e4eebda0e129be310642d0ebdaad9302ee", "parents": [ "607d8d662b717d80d0587c6a0e2c1df278687062" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Wed May 06 10:30:59 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:36:28 2020 -0700" }, "message": "tests: arm_arch_svc: introduce support for NVIDIA Denver CPUs\n\nThis patch introduces support for NVIDIA Denver CPUs and variants in the\nSMCCC_ARCH_WORKAROUND_1 test.\n\nVerified with TFTF ARM_ARCH_SVC test on Tegra194.\n\n\u003csnip\u003e\n\nRunning test suite \u0027ARM_ARCH_SVC\u0027\nDescription: Arm Architecture Service tests\n\n\u003e Executing \u0027SMCCC_ARCH_WORKAROUND_1 test\u0027\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\nINFO: Booting\nINFO: Powering off\n TEST COMPLETE Passed\n\n\u003csnip\u003e\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: Ibe179b43fd6a43c4fb5c6cdc7b0c78904efb1b5e\n" }, { "commit": "607d8d662b717d80d0587c6a0e2c1df278687062", "tree": "153cecc74c980110d1d2849733d83cc66a65e388", "parents": [ "941be71a56d7ec5cce98a27765c87def1dcd803f" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Fri Mar 27 09:43:24 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:36:28 2020 -0700" }, "message": "Tegra194: introduce per-CPU Hypervisor Timer Interrupt ID\n\nThis patch uses PPI 26 as the per-CPU Hypervisor Timer Interrupt ID.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I3e70aec91c129f57b39ca0d1165148880d59c8b3\n" }, { "commit": "941be71a56d7ec5cce98a27765c87def1dcd803f", "tree": "2f71042883b04b6f4ac142cf2b004e27de8b0b09", "parents": [ "8dcb737745c41222683b9c556c77c030de28e5bf" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Thu Mar 26 16:19:14 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:36:28 2020 -0700" }, "message": "Tegra194: skip some timer framework validation tests\n\nCPUs on Tegra194 platforms cannot be woken up with the RTC timer interrupt after\npower off.\n\nThis patch skips the following tests as a result:\n\n* Timer framework Validation/Target timer to a power down cpu\n* Timer framework Validation/Test scenario where multiple CPUs call same timeout\n* Timer framework Validation/Stress test the timer framework\n\nThese tests can be enabled once we figure out the right timer source to use for\nCPU wakeup.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I0f8154e285391fc35fe33428051ab1036ca9c845\n" }, { "commit": "8dcb737745c41222683b9c556c77c030de28e5bf", "tree": "c18379cc3f9c956bb430bde5f845e3dff9ec3679", "parents": [ "ae045908b4d757ce30ee4fc3aab77ca9afa5cf00" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Thu Mar 26 16:17:01 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:36:28 2020 -0700" }, "message": "Tegra194: introduce watchdog timer\n\nThis patch adds support for WDT0 that is connected to CPU0 to act as the\nwatchdog timer for Tegra194 platforms. The watchdog timer uses TMR0 as the\nsource and fires if the CPU is hung for more than 10 seconds.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: Ibe20c1130f86718b919c89436d7f5f49b74d9cc9\n" }, { "commit": "ae045908b4d757ce30ee4fc3aab77ca9afa5cf00", "tree": "5bd44d4235838a36096214b4e965ac8d3f6bed95", "parents": [ "fa6a2d27307698dadc19bf6665eae1378d3dd8b5" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Mar 23 19:29:58 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:36:28 2020 -0700" }, "message": "Tegra194: timers: increase the step value to 5ms\n\nThe RTC consumes 250us for each register read/write. Increase the step\nvalue to 5ms to cover all the register read/write in program_timer().\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: Iac0fc070dbf85a6352fbf147fc5945820e8ee495\n" }, { "commit": "fa6a2d27307698dadc19bf6665eae1378d3dd8b5", "tree": "7e8d2d9905620cb926108f02f28766684add05d9", "parents": [ "35106bd23a43797cd3ea74994498dc6cc1ceb812" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Fri Mar 20 22:41:32 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:36:27 2020 -0700" }, "message": "Tegra194: create dummy SMMU context for system resume\n\nThis patch creates a dummy SMMU context and saves the base address\nto a pre-negotiated scratch register for the System Resume Firmware\nto restore. This allows the System Resume Firmware to complete\nwithout any errors or warnings.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: Ic596e6775c6b78ac051ccff02e9574186d6f5335\n" }, { "commit": "35106bd23a43797cd3ea74994498dc6cc1ceb812", "tree": "99cabf95fcd9aa889c20e13fd9fb83b78720cfb0", "parents": [ "0107d76f084dde7e3efced050c9f0508d0310af8" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Fri Mar 20 10:12:03 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:32:44 2020 -0700" }, "message": "Tegra194: introduce system reset\n\nThis patch introduces the flexibility to reset the platform via\nthe SMC_PSCI_SYSTEM_RESET function ID.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I315315f1998d9b9d8f237ac05625328175880922\n" }, { "commit": "0107d76f084dde7e3efced050c9f0508d0310af8", "tree": "460a733e843a1dc8ad19ca2844ac1f52547f5912", "parents": [ "76724659cf86d114f59d608ffa6ca80ba420e84a" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Thu Mar 19 17:09:25 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:31:39 2020 -0700" }, "message": "Tegra194: disable some system suspend test cases\n\nThis patch disables the following test cases from the PSCI System\nSuspend Validation test suite:\n\n* system suspend from all cores\n* Suspend system with cores in suspend\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I5f6fcf01ad3b9012fac684f9b3beb87827148de0\n" }, { "commit": "76724659cf86d114f59d608ffa6ca80ba420e84a", "tree": "66fcf16ea6437c0a417bcd3a2f3aa362bb6cd6cb", "parents": [ "a287442ca1e9cea5c1f0e65b5640637cc321c069" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Mar 16 17:44:59 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:31:39 2020 -0700" }, "message": "Tegra194: skip CPU suspend tests requiring SGI as wake source\n\nTegra194 platforms do not support CPU suspend power down and cannot\nbe woken up with an SGI. This patch disables the following tests as\na result.\n\n+ PSCI Affinity Info/Affinity info level0 powerdown\n+ PSCI CPU Suspend/CPU suspend to standby at level 0\n+ PSCI CPU Suspend/CPU suspend to standby at level 1\n+ PSCI CPU Suspend/CPU suspend to standby at level 2\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I082f254fcd07f9b504f366f2f9a4b41cf7d6bbc3\n" }, { "commit": "a287442ca1e9cea5c1f0e65b5640637cc321c069", "tree": "b59873844a93ddc6d25453e5ea58e34a645422f0", "parents": [ "96b6cd2d9b5c8e9674bee633a7440326432345d8" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Mar 16 17:43:20 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:31:35 2020 -0700" }, "message": "Tegra194: wake: introduce support for RTC as wake source\n\nThis patch introduces support for adding RTC as a wake source to\nexit System Suspend state.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: Ib08d6e2ee7944cd46a91d272ceebffc67b8d7c66\n" }, { "commit": "96b6cd2d9b5c8e9674bee633a7440326432345d8", "tree": "ce5c6d96c0d5f56339573603750f1ad82e520c7c", "parents": [ "91535cdb88bc33845e5c0fae18cf88835dc8153c" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Mar 16 17:40:59 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:30:43 2020 -0700" }, "message": "Tegra194: pwr_mgmt: introduce power management support\n\nThis patch introduces support to enter the System Suspend power state. The\nrequired context is saved to allow the platform to enter and resume from\nthe state.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: Iaeaf065f87a2b20981aa92a14fa964802fada20c\n" }, { "commit": "91535cdb88bc33845e5c0fae18cf88835dc8153c", "tree": "07e231d96a7d4a518834be68fedf26e698a9e9b2", "parents": [ "9e6f757f3df716b7a1a9ac05de130617e10316fb" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Thu Mar 12 14:32:44 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:28:25 2020 -0700" }, "message": "plat: nvidia: introduce platform port for Tegra194\n\nThis patch contains the basic platform support for Tegra194 platforms\nto initialize the tftf framework and execute tests on the CPUs.\n\nThe tests require support for a timer, non-volatile memory, UART and\nGIC. This port uses Tegra_TMR0 as the timer, TI UART 16550 as the\nconsole and DRAM as NVM. The GIC driver provided by ARM is used as is.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I2da2121cb05445f47b7d3083cdd6ac6d52586797\n" }, { "commit": "9e6f757f3df716b7a1a9ac05de130617e10316fb", "tree": "9e6ea130e31face4b1012e65a55c80ee5aa1f9a9", "parents": [ "5861730b3d6333f936c2fcecaa034de0391cbd94" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Thu Mar 12 14:31:39 2020 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jun 08 16:20:40 2020 -0700" }, "message": "drivers: ti: uart: introduce UART 16550 driver\n\nThis patch introduces a console driver for the TI UART 16550\ndevice.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I46c1abacfe3c2392aee68f0f94b98a284568ddd8\n" }, { "commit": "5861730b3d6333f936c2fcecaa034de0391cbd94", "tree": "83d05162ed50140ae929b6049eb8e057eab76479", "parents": [ "9060e3e68241a3fc1ad8588c20a97218c34c6c68", "9bb75bd1a6010be4154365192e2a79bdcf80eff7" ], "author": { "name": "Mark Dykes", "email": "mardyk01@review.trustedfirmware.org", "time": "Mon Jun 08 15:33:23 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 08 15:33:23 2020 +0000" }, "message": "Merge \"Add .editorconfig from TF-A\"" }, { "commit": "7cc2587da605299e175444350c064c589ad09803", "tree": "e41b02ff4ba15df29582eaddb8f8e688a6ec4a8f", "parents": [ "9060e3e68241a3fc1ad8588c20a97218c34c6c68" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Jun 02 16:35:36 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jun 04 13:30:22 2020 +0000" }, "message": "TFTF: get FVP platform\u0027s topology from build options\n\nThis patch extends passing FVP topology parameters with\nFVP_CLUSTER_COUNT and FVP_MAX_CPUS_PER_CLUSTER build\noptions to match TF-A. The change adds more test options,\nmake FVP platform configuration more flexible and eliminates\ntest errors when the platform is configured with number\nof CPUs less than default values in the makefile.\nThese build options are documented in \u0027Arm FVP Platform\nSpecific Build Options\u0027 section of \u0027build-options.rst\u0027\ndocument.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I01c6437d468885755a5415804b3688e4c878170d\n" }, { "commit": "9060e3e68241a3fc1ad8588c20a97218c34c6c68", "tree": "1ef0aaf51b7a762d72ccf11a35f5b08764ca1c69", "parents": [ "0825704538540fa183851de902f83f7e22f69f0f", "945095ad9a97bc9469ca095f8dd057a4021297dd" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jun 03 20:46:29 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 03 20:46:29 2020 +0000" }, "message": "Merge changes from topic \"jb/8.6-features\"\n\n* changes:\n Test that TF-A supports ARMv8.6-ECV\n Test that TF-A supports ARMv8.6-FGT\n" }, { "commit": "945095ad9a97bc9469ca095f8dd057a4021297dd", "tree": "b0ef7e031939a3c397f5a4ab05cda9ff3bbc438f", "parents": [ "90f1d5caed95873e02071ef040191de52ee84a52" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Thu Apr 16 10:54:59 2020 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Wed Jun 03 13:30:29 2020 -0500" }, "message": "Test that TF-A supports ARMv8.6-ECV\n\nNote: This test will cause an unhandled exception in the case that TF-A\nis not doing its job and enabling ARMv8.6-ECV Self-Synch when the hardware\nsupports it.\n\nChange-Id: Iee19963f31fa47b0010e77d7b56b05b71ec1b507\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\n" }, { "commit": "9bb75bd1a6010be4154365192e2a79bdcf80eff7", "tree": "f98df4bd81c1f97b73f25a687c034768a3a063b3", "parents": [ "ed805928aeead72ce0ac1d3e3750ed630fb69937" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Fri Apr 24 11:23:52 2020 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Wed Jun 03 09:25:02 2020 -0500" }, "message": "Add .editorconfig from TF-A\n\nThis will configure many editors to follow the code style we use.\n\nChange-Id: I764485913adf3e93dcbb89cb859ec9350e5f4791\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\n" }, { "commit": "0825704538540fa183851de902f83f7e22f69f0f", "tree": "fd169daa7c6d701b2e20cab4f4e72ad9eef5ca68", "parents": [ "5da6f402dcc85a9a281eb93dc00d5af2eeabf3b0", "480d0985aab3c50c5afbe7db7b0f9a8244207e19" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 02 10:07:04 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 02 10:07:04 2020 +0000" }, "message": "Merge \"Bug fix in Multicore IRQ spurious test.\"" }, { "commit": "90f1d5caed95873e02071ef040191de52ee84a52", "tree": "d1b7fb445f987d6f7ff226e9dd49b14c507fe8bf", "parents": [ "5da6f402dcc85a9a281eb93dc00d5af2eeabf3b0" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Thu Apr 16 10:54:51 2020 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Fri May 29 14:19:14 2020 -0500" }, "message": "Test that TF-A supports ARMv8.6-FGT\n\nNote: This test will cause an unhandled exception in the case that TF-A\nis not doing its job and enabling ARMv8.6-FGT when the hardware supports\nit.\n\nChange-Id: Iae0fe39895909248b5e7b07a1a73f7702adce7dd\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\n" }, { "commit": "480d0985aab3c50c5afbe7db7b0f9a8244207e19", "tree": "fd169daa7c6d701b2e20cab4f4e72ad9eef5ca68", "parents": [ "5da6f402dcc85a9a281eb93dc00d5af2eeabf3b0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Mar 17 16:46:31 2020 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu May 28 05:41:40 2020 -0500" }, "message": "Bug fix in Multicore IRQ spurious test.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Iaf160c8bc9c5807fc9263f5250c0aeedc20e5a8a\n" }, { "commit": "5da6f402dcc85a9a281eb93dc00d5af2eeabf3b0", "tree": "536558dbcc3e81536a84c42010dff760b7418c08", "parents": [ "fa940145f77d1b9b625866b96108ba8eb8c62d46", "09d3ce922a82c76e5c231219fe16c719633cf048" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue May 26 09:11:49 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue May 26 09:11:49 2020 +0000" }, "message": "Merge changes from topic \"spci_to_ffa\"\n\n* changes:\n cactus: update memory/device region nodes in manifest\n cactus: map memory regions, used as RX/TX buffers in SPM\n SPCI is now called PSA FF-A\n" }, { "commit": "09d3ce922a82c76e5c231219fe16c719633cf048", "tree": "536558dbcc3e81536a84c42010dff760b7418c08", "parents": [ "26c6f8119722ad6872d45d39a19db3f44e96678a" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Apr 30 16:31:32 2020 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed May 20 10:50:43 2020 +0100" }, "message": "cactus: update memory/device region nodes in manifest\n\nadd memory/device region nodes in partition manifest to test SPM\nfunctionality, memory region has 3 entries(RX, TX and a dummy) while\ndevice regions has single dummy entry.\nRX/TX entries reference to the memory regions through phandle.\nMemory regions are mapped with following Attributes,\n RX buffer: read-only\n TX buffer: read-write\n dummy: read-write-execute\nDevice region mapped with read-write attribute.\n\nRefer to \"psa-ffa-manifest-binding.rst\" in TF-A project for details\nabout encoding of attributes.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I1937d99b9ed54e0a578f353d1a44983b9edd5ec0\n" }, { "commit": "26c6f8119722ad6872d45d39a19db3f44e96678a", "tree": "b058ced025bb5ad71b257ff4875079b93abe9cd9", "parents": [ "7581c388980a78f2938633ff0ec467c798afed91" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Apr 30 11:43:00 2020 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue May 19 17:07:20 2020 +0100" }, "message": "cactus: map memory regions, used as RX/TX buffers in SPM\n\nTo demonstrate implementation of memory-regions in SPM create RX/TX\nbuffers for each cactus VM. A VM will only map its allocated RX/TX\nmemory region.\nThe RX/TX regions start at 0x7200000 in Trusted DRAM. Each RX/TX buffer\npair in a VM will be of size 2 pages one for each of them.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I7d9dc5d82415d9543d4b9583ed6dca0d1f40b1cb\n" }, { "commit": "7581c388980a78f2938633ff0ec467c798afed91", "tree": "1c92c095a79eea03da670c31dbee58d5fd13d416", "parents": [ "fa940145f77d1b9b625866b96108ba8eb8c62d46" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 07 18:34:20 2020 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 15 16:11:32 2020 +0100" }, "message": "SPCI is now called PSA FF-A\n\nSPCI is renamed as PSA FF-A which stands for Platform Security\nArchitecture Firmware Framework for A class processors.\nThis patch replaces the occurrence of SPCI with PSA FF-A(in documents)\nor simply FFA(in code).\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I17728c1503312845944a5ba060c252c2b98f3e91\n" }, { "commit": "fa940145f77d1b9b625866b96108ba8eb8c62d46", "tree": "6b6acd48039dd7808c0e632fcbc2acb73b12b4e6", "parents": [ "705f66bd03095c14e76342c90e30fa3b76671951", "bc93a34c0db8adc674450b3452868ff3a1ec7503" ], "author": { "name": "Mark Dykes", "email": "mardyk01@review.trustedfirmware.org", "time": "Mon May 11 21:00:24 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon May 11 21:00:24 2020 +0000" }, "message": "Merge \"Add test case for SMCCC_ARCH_SOC_ID feature\"" }, { "commit": "bc93a34c0db8adc674450b3452868ff3a1ec7503", "tree": "6b6acd48039dd7808c0e632fcbc2acb73b12b4e6", "parents": [ "705f66bd03095c14e76342c90e30fa3b76671951" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Apr 28 17:59:32 2020 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Apr 29 18:10:11 2020 +0100" }, "message": "Add test case for SMCCC_ARCH_SOC_ID feature\n\nAdded test case for \"SMCCC_ARCH_SOC_ID\" SMC call.\nThis SMC call is used to retrieve SOC version and SOC revision\n\nTest execution output is as below:\n\n\u003e Executing \u0027SMCCC_ARCH_SOC_ID test\u0027\n TEST COMPLETE Passed\nSOC Rev is not implemented\nSOC Ver \u003d 0x43b0000\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I48668ce22bb5d5767dadb42ce9526d77fd916bed\n" } ], "next": "705f66bd03095c14e76342c90e30fa3b76671951" }