)]}'
{
  "log": [
    {
      "commit": "844b3629240275673d1611ab72f47ba7095b83a3",
      "tree": "2472d3d5d6c5897e15ced07de625b69be51e072f",
      "parents": [
        "a1497e32ae63fcf138b41bc96721a30751df4104"
      ],
      "author": {
        "name": "Sandrine Bailleux",
        "email": "sandrine.bailleux@arm.com",
        "time": "Mon Dec 17 16:39:29 2018 +0100"
      },
      "committer": {
        "name": "Sandrine Bailleux",
        "email": "sandrine.bailleux@arm.com",
        "time": "Tue Dec 18 14:20:22 2018 +0100"
      },
      "message": "FWU: Do not pull TFTF exception vectors code\n\nNS_BL1U and NS_BL2U images have their own exception vectors code\nprovided by lib/${ARCH}/exception_stubs.S.\n\nChange-Id: I5d2d760d9faf3d7bb4ba0bdefc5f20c193b1569d\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n"
    },
    {
      "commit": "7d34d304a5115a167102aa165c6a41124b00205d",
      "tree": "685e2e15323da617f07cda8f8db2eb73a26cf91e",
      "parents": [
        "13d99f95ae68104f4e97a58f6887c75863b4f502"
      ],
      "author": {
        "name": "Sandrine Bailleux",
        "email": "sandrine.bailleux@arm.com",
        "time": "Mon Nov 26 10:13:51 2018 +0100"
      },
      "committer": {
        "name": "Sandrine Bailleux",
        "email": "sandrine.bailleux@arm.com",
        "time": "Tue Nov 27 10:51:20 2018 +0100"
      },
      "message": "Move BL1 SMC FIDs macros out of platform layer\n\nBL1 SMC function IDs are not platform-specific so move them to a new\ngeneric header file, called bl1.h.\n\nChange-Id: I621483f7737f8101e9f370343e1a45a731c31c3b\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n"
    },
    {
      "commit": "aef556a8b784fe98fad89591e097b486ab92f6c8",
      "tree": "d04505dcb5e8c74b9a69813185f15291bd2f6bda",
      "parents": [
        "7af6c6ddaa365891b6710bc5664584349f59c11f"
      ],
      "author": {
        "name": "Sandrine Bailleux",
        "email": "sandrine.bailleux@arm.com",
        "time": "Thu Oct 25 12:47:55 2018 +0200"
      },
      "committer": {
        "name": "Sandrine Bailleux",
        "email": "sandrine.bailleux@arm.com",
        "time": "Thu Oct 25 16:28:51 2018 +0200"
      },
      "message": "Disable hardware alignment checking\n\nAt the moment, alignment fault checking is always enabled in TF-A\nTests (by setting the HSCTLR/SCTLR.A bit). Thus, for every instruction\nthat loads or stores one or more registers, the hardware checks that\nthe address being accessed is properly aligned to the size of the data\nelement(s) being accessed. If this check fails it causes an alignment\nfault, which is taken as a data abort exception.\n\nHowever, the compiler is currently unaware that it must not emit load\nand store instructions resulting in unaligned accesses because we do\nnot compile the source code with -mstrict-align (AArch64) /\n-mno-unaligned-access (AArch32). Because of this, we might get some\nunexpected alignment faults.\n\nWe could request the compiler to align all data accesses but whether\nthis gives us any performance benefit is dependent on the\nmicroarchitecture. Thus, it is simpler to just disable hardware\nalignment checking and let the compiler make the call.\n\nChange-Id: I6ef4afb09e0f87c8462a968da1ca2192ee075b40\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n"
    },
    {
      "commit": "1cf45c96b2e87a60cbed25245c2319b2a391da1e",
      "tree": "f465e3b9880c99749c5e21beed70a0129e93d40c",
      "parents": [
        "2bfcf9ef94656ad4ceb5b58b9f0be7aae4f1b589"
      ],
      "author": {
        "name": "Antonio Nino Diaz",
        "email": "antonio.ninodiaz@arm.com",
        "time": "Mon Oct 15 09:03:43 2018 +0100"
      },
      "committer": {
        "name": "Antonio Nino Diaz",
        "email": "antonio.ninodiaz@arm.com",
        "time": "Mon Oct 15 09:03:43 2018 +0100"
      },
      "message": "Move platform_helpers.S to each platform\u0027s folder\n\nIn practice, all the functions in this file are platform-specific. It is\nbetter to force all platforms to implement than having some sort of weak\nfunction placeholder.\n\nPorting guide updated.\n\nChange-Id: I5beeeb10bec6fe5178b24503d6da8ca66074a8c6\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n"
    },
    {
      "commit": "3cd87d77947ec4fc04440268ed122b4ed81c7781",
      "tree": "78fdee12b026b931029e434f29b4fe09835fe4c9",
      "parents": [],
      "author": {
        "name": "Sandrine Bailleux",
        "email": "sandrine.bailleux@arm.com",
        "time": "Tue Oct 09 11:12:55 2018 +0200"
      },
      "committer": {
        "name": "Sandrine Bailleux",
        "email": "sandrine.bailleux@arm.com",
        "time": "Wed Oct 10 12:34:34 2018 +0200"
      },
      "message": "Trusted Firmware-A Tests, version 2.0\n\nThis is the first public version of the tests for the Trusted\nFirmware-A project. Please see the documentation provided in the\nsource tree for more details.\n\nChange-Id: I6f3452046a1351ac94a71b3525c30a4ca8db7867\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\nCo-authored-by: amobal01 \u003camol.balasokamble@arm.com\u003e\nCo-authored-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\nCo-authored-by: Asha R \u003casha.r@arm.com\u003e\nCo-authored-by: Chandni Cherukuri \u003cchandni.cherukuri@arm.com\u003e\nCo-authored-by: David Cunado \u003cdavid.cunado@arm.com\u003e\nCo-authored-by: Dimitris Papastamos \u003cdimitris.papastamos@arm.com\u003e\nCo-authored-by: Douglas Raillard \u003cdouglas.raillard@arm.com\u003e\nCo-authored-by: dp-arm \u003cdimitris.papastamos@arm.com\u003e\nCo-authored-by: Jeenu Viswambharan \u003cjeenu.viswambharan@arm.com\u003e\nCo-authored-by: Jonathan Wright \u003cjonathan.wright@arm.com\u003e\nCo-authored-by: Kévin Petit \u003ckevin.petit@arm.com\u003e\nCo-authored-by: Roberto Vargas \u003croberto.vargas@arm.com\u003e\nCo-authored-by: Sathees Balya \u003csathees.balya@arm.com\u003e\nCo-authored-by: Shawon Roy \u003cShawon.Roy@arm.com\u003e\nCo-authored-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nCo-authored-by: Thomas Abraham \u003cthomas.abraham@arm.com\u003e\nCo-authored-by: Vikram Kanigiri \u003cvikram.kanigiri@arm.com\u003e\nCo-authored-by: Yatharth Kochar \u003cyatharth.kochar@arm.com\u003e\n"
    }
  ]
}