)]}' { "log": [ { "commit": "799225ffb1e2f3ea86d7a026b8fe3e2193d2000c", "tree": "7b8ffe88db797e7bb5a6d763c4e3186e4935122f", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Thaddeus Gonzalez-Serna", "email": "Thaddeus.Gonzalez-Serna@arm.com", "time": "Mon Jun 02 09:42:49 2025 -0500" }, "committer": { "name": "Thaddeus Gonzalez-Serna", "email": "Thaddeus.Gonzalez-Serna@arm.com", "time": "Fri Sep 19 11:23:02 2025 -0500" }, "message": "feat(neg-boot): tftf invalid rotpk test\n\nTest to improve code coverage in scenario with corrupt rotpk in fip certificate\n\nChange-Id: I995ab6d9f1488fda44e10ae9ef70c9056d780a89\nSigned-off-by: Thaddeus Gonzalez-Serna \u003cThaddeus.Gonzalez-Serna@arm.com\u003e\n" }, { "commit": "9b1afa7fdeaa7a57900c3aa606626a9c9bf9e405", "tree": "b63bf8e845ab5ff2bc70f711e4ef19b012ccca01", "parents": [ "e0b75ac177b9b3e7d703948387f429a665615c23" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 15 10:58:13 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 29 11:24:36 2025 -0500" }, "message": "feat(mpam): test FEAT_MPAM_PE_BW_CTRL register access\n\nThis patch introduces FEAT_MPAM_PE_BW_CTRL testing to cpu feats.\nWe check the presence of registers MPAMBW2_EL2, MPAMBW1_EL1\nand MPAMBWIDR_EL1 to verify FEAT_MPAM_PE_BW_CTRL\nis supported.\n\nChange-Id: I5f89402e8aa0ce3320f3e120f4c0c9dbed6f8c5f\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "f41d8eeb88a4759bd463ccbb2e5eac3e6ee7eb2c", "tree": "56b3830820758d600ddb6d138590c4c6aeb60ee4", "parents": [ "735050f270024e5443f1e9bf45e98a4d3954c9d5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Jul 10 16:41:28 2025 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Aug 20 20:01:47 2025 +0000" }, "message": "test(fuzzing): adding variable coverage\n\nAdding the capability to produce coverage of the arguments of the\nSMC calls as generated by the fuzzer. The output from the FVP will\nbe routed to UART3 where a python flow will read the data to create\ntables of each SMC call with its fields shown and values given. The\noption is enabled by adding SMC_FUZZ_VARIABLE_COVERAGE\u003d1 to the\ncorresponding TFTF config.\n\nChange-Id: I2d4d310976aa2c0447efbd8ec0676bb9f8699828\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "c5d4409d2dbea27291c043dc48ef0d8b4513a428", "tree": "5b6d07c16c88a6236624b574e2ccde238d7b0d57", "parents": [ "5cbf1492282685e1cc5e0d2154c3fc48458a3e91" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Thu Jul 24 19:44:09 2025 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Wed Aug 13 18:25:50 2025 -0500" }, "message": "feat(realm): add tests for min, max and default MECID\n\nThis patch introduces two tests. Each one assigns the minimum and\nmaximum MECID to a newly created Realm respectively. In addition\na third test assigns the default MECID (0) to two realms to test\nthe shared state of this MECID by default.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I0498084f9c808b6d4db16a939495635c394b2ff3\n" }, { "commit": "5cbf1492282685e1cc5e0d2154c3fc48458a3e91", "tree": "999a63f4388deff1c033cd9253ff2ca0ca3addc6", "parents": [ "2a93d283f113d3971d2247090f8235c3c1d722ac", "5d7869ffd342e999e946dfd191bf90ab29c1461f" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Aug 11 16:58:34 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 11 16:58:34 2025 +0000" }, "message": "Merge changes I02b70986,I9de84f1b,I89bf0801\n\n* changes:\n feat(realm): Remove hardcoded MECID\n feat(realm): add tests for FEAT_MEC\n feat(realm): assign MECID when creating realms\n" }, { "commit": "5d7869ffd342e999e946dfd191bf90ab29c1461f", "tree": "6026aedac90e5fa9a8b6f4e4c6447b2373bedb73", "parents": [ "7288f9283f5fe302dcbf8eb67d49fc6e5df46639" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jul 21 00:02:52 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Aug 11 17:26:43 2025 +0100" }, "message": "feat(realm): Remove hardcoded MECID\n\nThis patch removes the hardcoded fixed MECID with a number which\nis continually incremented based on MAX_MECID support.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I02b70986d7eef58248abd9c8db0eda20ea32eda0\n" }, { "commit": "7288f9283f5fe302dcbf8eb67d49fc6e5df46639", "tree": "e9ef1cb5906cf887c71cf75826e2a3986d7c915d", "parents": [ "dc23fcdec28d9c315c741710aba76c2145b73e91" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Wed May 07 14:42:50 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Aug 11 17:26:26 2025 +0100" }, "message": "feat(realm): add tests for FEAT_MEC\n\nThis patch creates two test in order to verify the correct\nassignment of MECIDs to realms.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I9de84f1ba8a8b42e55b1ea163f90e9daf56c74c9\n" }, { "commit": "dc23fcdec28d9c315c741710aba76c2145b73e91", "tree": "e54af256a0e4ef90b75f627ac6fe2217d6c1bb0b", "parents": [ "1bc61da619b0b375459ae221bd13bb25dcbf0bc2" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Sat Apr 05 14:26:13 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Aug 11 16:22:35 2025 +0000" }, "message": "feat(realm): assign MECID when creating realms\n\nThis change allows TFTF to assign a MECID to every realm that is\ncreated by passing an extra parameter to the Realm creation helpers.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I89bf08011eb005d949a195b406b073955f23f5ad\n" }, { "commit": "7066428566e6a9d2ac061ca5f62df7d09d69141a", "tree": "c708d48da4514c485460f8f050f31964adae3991", "parents": [ "27c44fd790d7fcfd9233c3d556a474d8c075755b" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Aug 07 15:36:07 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Aug 07 16:12:50 2025 -0500" }, "message": "fix: resolve static-check issues in smccc_arch_soc_id test\n\nChange-Id: I841c5fdafaaf1ec8a00dfa972fbbfd1d44a843ba\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "bdb61f3c2c4de04b71d5c9b05794c3c6c4e0a14d", "tree": "4e276403352e3549e0b346a6b5c7ae3a7c4f08f2", "parents": [ "5431ac521fcedb2993160a622fa0303a620b09d0" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Jul 16 16:16:26 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Jul 25 14:04:31 2025 -0500" }, "message": "test(smccc): add SoC Name test support to SMCCC_ARCH_SOC_ID\n\nThis patch tests the SoC Name functionality of SMCCC_ARCH_SOC_ID\nas part of SMCCC 1.6 update.\n\nReference: https://developer.arm.com/documentation/den0028/latest/\n\nChange-Id: Ic3be2bdf4e7268b28d392c338533f0603f0716e8\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "8f175150b982930774b4bc5bf18c39afc00f7fdb", "tree": "026f5f9c73de64dbed56ed1ad85a0feb39dc6e2a", "parents": [ "aa22f41c438313fe23d42656c1dff8ca56d77524" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 16:18:03 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jul 22 10:24:31 2025 +0100" }, "message": "fix(ls64): match types when printing\n\nWhen building with verbose printing, the types don\u0027t match up and the\nbuild fails. Match them up.\n\nChange-Id: I5af968872f4e707c206c4770c0000e14508a4611\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "32815d30b1d4b2126cdff5ef9908446e1880d44e", "tree": "444daec706ad840760bcd8bac23c2e286a3b79c2", "parents": [ "c229e235e317da7f13110563b30891871c2d0e91" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 09:21:54 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Jul 18 16:49:14 2025 +0100" }, "message": "perf(tftf): reduce the IRQ validation wait\n\nThe IRQ validation test waits for half a second before checking that an\ninterrupt happened and it wasn\u0027t handled. This is an eternity for any\nreasonable system and waiting that long isn\u0027t necessary. Reduce the wait\nso that testing is quicker.\n\nChange-Id: I90b2b74815815bac4272df992725a8311c6f373d\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "c229e235e317da7f13110563b30891871c2d0e91", "tree": "a16b04cb0ad70a3bc159164e4127dfdd6be5be8b", "parents": [ "d03eb8b988d90d0f62817b5ddbe584e0f9140558" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 08:45:33 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Jul 18 16:49:13 2025 +0100" }, "message": "perf(tftf): don\u0027t use waitms() for events testing\n\nWaiting for wall time on FVP takes longer than the desired time. As a\nresult this test takes a seemingly very long (over 30 seconds!) and is\nsometimes indistinguishable from hanging. Additionally, it is a tftf\nself test so the chances of it ever going wrong are practically zero.\n\nDecouple the test from time and use more primitive synchronisation to\nmaintain the same function. Since the primary waits for all secondaries\nto enter the test, we can be fairly certain that at least one has\nproceeded a little further and is waiting for an event by the time the\nprimary has caught up and we don\u0027t need the delay. Then the other\ndelays can be removed by having the secondaries wait on non-event API\nevent before waiting on the event.\n\nChange-Id: I958595b93030596633bbd08b2369ecdffe34d6d3\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "bd2b4d50484db56c919ce4dc8324c39d3055b013", "tree": "84b5262e5c4d02cd90e9916fa1161c4a469332f2", "parents": [ "81a2acccff0c88b0087753444057d577257b08fa" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jul 10 15:01:18 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jul 10 16:40:00 2025 +0000" }, "message": "fix(realm): fixup pdev_create arguments\n\nDirectly invoke host_rmi_pdev_create with invalid arguments instead of\nreferring to gbl_host_pdevs[0] as no valid devices exists in TRP\nrun config.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I424d77ff2cd3b265a1b1bdcb8e44aa6851c72d13\n" }, { "commit": "aedca160ea2d648b6f46535a2cce9e4354d30e12", "tree": "3045a9a21bcaa2ca396fa7895796dcf5e295ecd8", "parents": [ "73005a60253c98274a4a1104af0bf75ccca4d205" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Apr 21 16:39:06 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Jul 09 09:08:58 2025 +0000" }, "message": "feat(realm_host_mgmt): support multiple devices in DA test\n\nConnect all off-chip pcie devices with TSM. This setup secure session,\nIDE and programs DVSEC RMEDA.\n\nHost assigns all devices that are connected with TSM to a Realm. And\nRealm locks and accepts the assigned device.\n\nThis patch adds host_da_workflow_on_all_offchip_devices testcase.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Id8ea54f9c9aad45787a0aac106a9260f68a63ec5\n" }, { "commit": "73005a60253c98274a4a1104af0bf75ccca4d205", "tree": "4b377917909b3aeada9b6a23598112b2b63fd145", "parents": [ "b0833d26dacc0fef45e4d695f9e7028a8d20825e" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 10:37:15 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Jul 09 09:08:51 2025 +0000" }, "message": "refactor(lib/pcie): rename macro CHECK_DA_SUPPORT_IN_RMI\n\nRename macro CHECK_DA_SUPPORT_IN_RMI to SKIP_DA_TEST_IF_PREREQS_NOT_MET\nand move it to host_da_helper.h\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ie955e1dcb2edefa0f41edfc36b4b2587cb465a29\n" }, { "commit": "bbb1305abc89d5b88a4cefe374e05052f27d165c", "tree": "914c12b61f6f91da1982b906aa3dd180b911583c", "parents": [ "503b89a6b2d6ecd039401bd7f6f08f0d3cbb69a6" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 24 14:00:06 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:39 2025 +0100" }, "message": "feat(lib/pcie): add dvsec helpers\n\nAdd DVSEC RME DA support and helpers based on RME System\nArchitecture [1].\n\n[1] https://developer.arm.com/documentation/den0129/latest\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I29c2dc3c94fa295c9948f63f57f88e2763326291\n" }, { "commit": "20c2d74e687556c462b49eb1f8a5e3afc21698cb", "tree": "f1ff24aa3b26674b0fdc9395655dd359a94be504", "parents": [ "9f6afef2ff8f2f36f2df2993d1de086599955677", "51f0333e24e6c4aff44ace871c6042b507476b5e" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jun 27 14:35:51 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 27 14:35:51 2025 +0000" }, "message": "Merge \"revert: replace in-tree Event Log Lib w/ submodule\"" }, { "commit": "51f0333e24e6c4aff44ace871c6042b507476b5e", "tree": "4e7a4c0d34ab7cb3c0039bbd3b59431f646c531c", "parents": [ "cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jun 27 13:47:23 2025 +0000" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jun 27 13:57:23 2025 +0000" }, "message": "revert: replace in-tree Event Log Lib w/ submodule\n\nThis reverts commit cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849.\n\nReason for revert: Causing CI failures\n\nChange-Id: Iad32fb9ba1d32044ef647f01e3091e9b0ee0d9e2\n" }, { "commit": "9f6afef2ff8f2f36f2df2993d1de086599955677", "tree": "bdfab4c4abc2bb6e1fad51fa1b8160abe7bff085", "parents": [ "411645c66c9c95d70b6f26802b2ea41f4ee2981b", "9cc32220197b753f661f47b467c9d629dd9d030c" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 27 12:55:37 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 27 12:55:37 2025 +0000" }, "message": "Merge \"fix: update partial success for DA test case\"" }, { "commit": "cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849", "tree": "8be9469773b3f15614ee27ae9539cc29f8692c3c", "parents": [ "68ecce15bcd5db2449700d122f4e8f32cce91ae9" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu May 22 11:08:46 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 24 15:58:15 2025 +0000" }, "message": "refactor: replace in-tree Event Log Lib w/ submodule\n\nThe Event Log Library has been relocated to a separate repository and is\nnow integrated as a submodule, eliminating the need for in-tree files\nand reducing maintenance efforts for TFTF.\n\nChange-Id: I29694f8b3b08bb1d57dd685f6e42dc9f69d241bb\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "68ecce15bcd5db2449700d122f4e8f32cce91ae9", "tree": "4e7a4c0d34ab7cb3c0039bbd3b59431f646c531c", "parents": [ "550d5104ffe85f2f6994ef04a7172627cd76770e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon May 12 12:38:24 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 24 15:58:13 2025 +0000" }, "message": "feat(libtl): integrate Transfer List Library as submodule\n\nReplaces in-tree transfer_list implementation with LibTL submodule.\nRemoves legacy source and headers, updates includes and makefiles\nto use the standalone library. Adds architecture-specific inttypes\nheaders for compatibility.\n\nChange-Id: Iff8272a6417983b9fb8e7f6bde6db44c2a6020f5\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "9cc32220197b753f661f47b467c9d629dd9d030c", "tree": "bae5e24a0eaae2c69f1e33f69aff479001e3c9cb", "parents": [ "e1a53a699649c263860560a5ac784599c3b289ca" ], "author": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Mon Jun 23 14:54:42 2025 +0200" }, "committer": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Mon Jun 23 15:00:36 2025 +0200" }, "message": "fix: update partial success for DA test case\n\nThis patch returns a SUCCESS error code on partial success of DA\ntestcase so that TF-RMM can progress with partial merge of DA\npatch stack. This will be reverted when the entire DA\nflow is implemented in TF-RMM.\n\nSigned-off-by: Mate Toth-Pal \u003cmate.toth-pal@arm.com\u003e\nChange-Id: I39a682fd4a346b8f34b51a20e3b5868f71a0f214\n" }, { "commit": "a494e31d805b2ea60e1b154cdf70eba5b8239e31", "tree": "ae40d0ba75e4fec2b1a193e99114facb551f11bc", "parents": [ "f25ff9bdacb9b355935486a0b41bcd07789cac38" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jun 19 16:27:45 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 20 11:36:59 2025 +0000" }, "message": "chore(rme): get device memory regions for map/unmap\n\nSet device memory map/unmap test structures based on\nretrieved platform PCIe memory regions and remove\ndependency on the second region.\n\nChange-Id: If9d778a7d922eaf1ead3193d2916756fd74d77df\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "f25ff9bdacb9b355935486a0b41bcd07789cac38", "tree": "c2473e6292ac1463ef08f61e95f13f7c4485c297", "parents": [ "1356594a91dad701720d4c30357bc2f64f268dbf" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 18 13:51:07 2025 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 18 14:22:48 2025 +0100" }, "message": "chore(rme): dev granules delegation tests\n\nModify device granules delegatation tests to use\nall existing PCIe memory regions.\nSeed the random number generator by reading RNDR register.\n\nChange-Id: I8f6f0d321a71f1913c63dbab50b2085b308ded58\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "1356594a91dad701720d4c30357bc2f64f268dbf", "tree": "3b1967ddeb8b1e77f9b92072ed2ed26dd8c5b70d", "parents": [ "41684ab1b6655ddeddbd13cff6d3a2938aa1cf2d", "295721e357657995da7e5ee41528a5f14bff497a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jun 16 06:09:17 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 16 06:09:17 2025 +0000" }, "message": "Merge changes from topic \"da_alp12\"\n\n* changes:\n fix: allow partial success for DA test case\n fix(realm): cleanup pdev after setup\n chore(realm): rename rsi_ripas_respose_type to rsi_response_type\n chore(real_da): move realm DA support functions\n chore(host_da): move host RME DA related functions\n feat(realm): added support to invoke RSI RDEV ABIs\n feat(realm): align RSI ABIs with RMM spec 1.1-alp12\n feat(realm_host_mgmt): added support to call RMI VDEV ABIs\n feat(host_realm_mgmt): align DA RMI ABIs RMM spec 1.1-alp12\n chore(include/runtime_services): update SMC RMI commands\n" }, { "commit": "5fdb3bff1892596ae023876e62097df70cb0bb37", "tree": "a29b300157e93b11a9b38e831959f64172ebb326", "parents": [ "f54e1fea268a63b2fb6bb41b0a1be4d3f9408ffa" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 22:59:55 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Sat Jun 14 08:07:02 2025 +0000" }, "message": "fix: correct the check for MbedTLS makefile\n\nThis patch addresses an issue introduced in a previous\ncommit where the inclusion of the MbedTLS makefile was\nincorrect.\n\nChange-Id: Icdae1d85e4bc5663f68b12a9087084ce667f38f4\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "295721e357657995da7e5ee41528a5f14bff497a", "tree": "9f2feff5677fc194200d30d143f6afdbea032e8d", "parents": [ "d0d1710183402ef819629c61f1e311ef645148d0" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 00:07:23 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 17:57:03 2025 +0100" }, "message": "fix: allow partial success for DA test case\n\nThis patch returns a SUCCESS error code on partial success of DA\ntestcase so that TF-RMM can progress with partial merge of DA\npatch stack. This will be reverted when the entire DA\nflow is implemented in TF-RMM.\n\nChange-Id: Ia28da05efd93d8290c2cfc879e09ff796a5797d6\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "d0d1710183402ef819629c61f1e311ef645148d0", "tree": "b54047ef37f85f9e7215db14726368703dd56a5d", "parents": [ "08a5f16c322b75a5ed7a1b16da2bb2fc6755ca16" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 06 17:20:59 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 17:57:03 2025 +0100" }, "message": "fix(realm): cleanup pdev after setup\n\nChange-Id: Ia2f47fef71ce7336cece5f14b50e0ea4631c0358\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "19ad61740ec71f886473c3f4d125ad062ce6c9f4", "tree": "5f707d4e0cbfd1136312c33f02576745a9bf689d", "parents": [ "c58e4697c2df3d1b9d3a7d2e3da2294a13c27449" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 24 10:39:53 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 17:57:03 2025 +0100" }, "message": "chore(host_da): move host RME DA related functions\n\nMove host RME DA related functions from host_rmi_da_flow.c\nto host_da_helper.c.\n\nChange-Id: Ib5c5ba3440ba1fa26b6f25a8bfab002183252627\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "c58e4697c2df3d1b9d3a7d2e3da2294a13c27449", "tree": "8b0e4d94ab522130322b4a260f7114efa418abd4", "parents": [ "51135c80730b1ce8faf30ee53a3797bdf342661c" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jan 28 12:28:59 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 17:57:03 2025 +0100" }, "message": "feat(realm): added support to invoke RSI RDEV ABIs\n\n- Updated DA RSI data types with RMM spec 1.1-alp11.1.\n- Added support to call DA RSI RDEV ABIs like\n SMC_RSI_RDEV_CONTINUE\n SMC_RSI_RDEV_STOP\n SMC_RSI_RDEV_START\n SMC_RSI_RDEV_GET_INTERFACE_REPORT\n SMC_RSI_RDEV_LOCK\n SMC_RSI_RDEV_GET_INFO\n SMC_RSI_RDEV_GET_MEASUREMENTS\n SMC_RSI_RDEV_GET_STATE\n SMC_RSI_RDEV_GET_INSTANCE_ID\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I60664262c24f287637e91d53ecab0c8b980e58b7\n" }, { "commit": "c4ef92bd075d41d7d1ae03b9c5484881547946e7", "tree": "3471ac534950b9cde8059ed320aa4a1d4d797595", "parents": [ "ec4249f483a9ca6e5d65db7ae9c65a69b1d22a96" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Fri Jan 24 11:55:02 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 16:53:06 2025 +0100" }, "message": "feat(realm_host_mgmt): added support to call RMI VDEV ABIs\n\nThis change creates a Realm witn RMI_FEAT_DA feature and assigns\na VDEV to the Realm using RMI_VDEV_CREATE and calls various VDEV\nmanagement ABIs like:\n SMC_RMI_VDEV_DESTROY\n SMC_RMI_VDEV_STOP\n SMC_RMI_VDEV_GET_STATE\n SMC_RMI_VDEV_COMMUNICATE\n\nOnce the VDEV is assigned to a Realm. A REC enter is done to invoke\nDA RSIs calls.\n\nA common dev_communicate is implemented that is used by both PDEV\nand VDEV communicate.\n\nRenamed testcase host_test_rmi_pdev_calls to host_invoke_rmi_da_flow.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Iefe6f6ee4c0810479d20319851cd8a6590c1e4d7\n" }, { "commit": "ec4249f483a9ca6e5d65db7ae9c65a69b1d22a96", "tree": "04bb12194f885577d0ddbe29aba3008dc9c84660", "parents": [ "5dac5b087067ac7c726ba6eef13538e84d330f43" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jan 07 15:13:09 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 16:52:09 2025 +0100" }, "message": "feat(host_realm_mgmt): align DA RMI ABIs RMM spec 1.1-alp12\n\nThe DA RMI ABIs related to PDEV, VDEV are aligned to RMM specification\n1.1-alp12\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I6ac86bd2d574f93c7f7b29095b242e4cbf73a071\n" }, { "commit": "5dac5b087067ac7c726ba6eef13538e84d330f43", "tree": "6e951e9d7e671c439d7fbce6bf8554b76f9124c2", "parents": [ "f54e1fea268a63b2fb6bb41b0a1be4d3f9408ffa" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jan 07 14:51:50 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 16:52:09 2025 +0100" }, "message": "chore(include/runtime_services): update SMC RMI commands\n\nThis syncs the naming of SMC RMI commands with TF-RMM. This change helps\nto update SMC RMI commands and data types easily whenever it gets\nupdated in TF-RMM.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I8acc96d5326ad0656df0f6c7822adefe87a275c3\n" }, { "commit": "f54e1fea268a63b2fb6bb41b0a1be4d3f9408ffa", "tree": "1c688ebf6673563fdd5871dd3eda45457454cc47", "parents": [ "42c4a61e973a8d2a50f6e606ac1fc61157fa4e85", "8307c3367e29b068cd3e65b5bd05aa28f8fee0f8" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 15:36:34 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 13 15:36:34 2025 +0000" }, "message": "Merge \"feat(rmm): add tests for FEAT_TCR2 on RMM\"" }, { "commit": "8307c3367e29b068cd3e65b5bd05aa28f8fee0f8", "tree": "b19d216065c9af2c129b5e692024acc836b70662", "parents": [ "d1cf6dc75ffa489f3055b2c453ad57893214b6bc" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Jun 12 10:30:46 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 15:35:48 2025 +0000" }, "message": "feat(rmm): add tests for FEAT_TCR2 on RMM\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I4dc16c5c6edcabf993ea30fe53eff5993b5af651\n" }, { "commit": "42c4a61e973a8d2a50f6e606ac1fc61157fa4e85", "tree": "55e2cc735d7d1f1b931c1b3e1c69c689f81d0e5c", "parents": [ "d1cf6dc75ffa489f3055b2c453ad57893214b6bc", "ea34abf73d6405cd870fe1f1ff46268b635f51d6" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Jun 13 13:59:30 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 13 13:59:30 2025 +0000" }, "message": "Merge \"fix(realm): add missing size definitions for Juno\"" }, { "commit": "d1cf6dc75ffa489f3055b2c453ad57893214b6bc", "tree": "c3be96dc6a3cf24de7b5d778004a4e76d97dbbc5", "parents": [ "d479a125cbb07b63c85daf42a36215008168fd37", "a1fe738b1fd6212d92e20a408a0110778276732b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 10:53:51 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 13 10:53:51 2025 +0000" }, "message": "Merge \"feat(rme): test access outside PAR from Plane N\"" }, { "commit": "1b16dc85e01ac96b02a384a307925005a471b2e2", "tree": "56be81714e31b82397012a6203f28a17bbb203d4", "parents": [ "718fd7902c015a64b49b12dcb6005d1aa50fd72e" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Jan 14 11:40:18 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jun 12 23:30:01 2025 +0100" }, "message": "feat(rme): add dev mem map/unmap tests\n\n- Add tests for RMI_DEV_MEM_MAP and\nRMI_DEV_MEM_UNMAP commands as per RMM Specification 1.1-alp12.\n- Add RNDR and RNDRRS registers\u0027 definitions.\n- Redefine RNDR and RNDRRS read functions as:\nDEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)\nDEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS)\n\nChange-Id: Ieecc41dd6d3011bb63101bc38d527a8f57e0ef4a\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "718fd7902c015a64b49b12dcb6005d1aa50fd72e", "tree": "6be817fbd9b1073bdd876b527e31e06e45b8a782", "parents": [ "5032d7bc760128a07ace8c9d4d91f7c3e9011cda" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Nov 08 14:55:20 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jun 12 22:45:11 2025 +0100" }, "message": "feat(rme): add dev granules tests\n\nAdd tests for RMI_GRANULE_DELEGATE and\nRMI_GRANULE_UNDELEGATE commands using\ndevice granules.\nAdd plat_get_dev_region() function to\nretrieve platform PCIe memory region info.\n\nChange-Id: Ie59361dd28e11db348c30b033c156de044aa0ffc\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "ea34abf73d6405cd870fe1f1ff46268b635f51d6", "tree": "2daf50e3f07248fad9165858eab605c46fff20b7", "parents": [ "5032d7bc760128a07ace8c9d4d91f7c3e9011cda" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Jun 12 10:11:03 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Jun 12 14:01:28 2025 +0000" }, "message": "fix(realm): add missing size definitions for Juno\n\nFixes compilation failure for Juno targets by ensuring the necessary\nsize definitions from `common_def.h` are included. This resolves build\nerrors even when the tests are not executed. These tests dynamically\ncheck whether RME is enabled on a platform and run conditionally. As\npart of the standard test suite, the source files cannot be excluded\nfrom the TFTF build due to their automatic generation in the test list.\nThis change ensures that the tests compile successfully for Juno.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: I001a89108c6962a37b24bd3f17e68010a161aaca\n" }, { "commit": "a1fe738b1fd6212d92e20a408a0110778276732b", "tree": "ad9028b4524278c1b14628871964c46a72e564b8", "parents": [ "5032d7bc760128a07ace8c9d4d91f7c3e9011cda" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Apr 25 20:45:17 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jun 06 17:53:31 2025 +0100" }, "message": "feat(rme): test access outside PAR from Plane N\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I3c5069e14fdf27e6c36bd1e0651ceff4ee7396ef\n" }, { "commit": "5f1c41402b7afbd6de4979981124d5e1e76ecb32", "tree": "c9dd553669e6432c4b35fee67ecd59a0fbda3876", "parents": [ "bb64f248781aeb51b5b628298241dd5750fedf6c", "ba6ef4f4426da1aa17f76a1b8f914b53aaeb6d34" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Jun 03 21:36:22 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 03 21:36:22 2025 +0000" }, "message": "Merge \"test(fwu): validate scenario of invalid FWU IMAGE SIZE\"" }, { "commit": "ba6ef4f4426da1aa17f76a1b8f914b53aaeb6d34", "tree": "f9c5c334b18e4bc1ddd30b2d03c0053d17906103", "parents": [ "0c8bf6445cdd41d08d1b926160d2f66b3312f12b" ], "author": { "name": "Thaddeus Gonzalez-Serna", "email": "Thaddeus.Gonzalez-Serna@arm.com", "time": "Tue May 13 14:54:41 2025 -0500" }, "committer": { "name": "Thaddeus Gonzalez-Serna", "email": "Thaddeus.Gonzalez-Serna@arm.com", "time": "Mon Jun 02 09:46:51 2025 -0500" }, "message": "test(fwu): validate scenario of invalid FWU IMAGE SIZE\n\nTest to increase code coverage in bl1 directory where\nbl2 and bl2u are both corrupt with invalid image sizes\n\nbl1_fwu.c cc% improved by 10%\nbl1_main.c cc% imporved by 1%\n\nChange-Id: I4637a9e566e4edda8474da37ea4f3511fa32b6a7\nSigned-off-by: Thaddeus Gonzalez-Serna \u003cThaddeus.Gonzalez-Serna@arm.com\u003e\n" }, { "commit": "6150f5ff0687d4ee35f1e69b9ac33c5e98f047d0", "tree": "e9f474b713cf42a582fe13a4c4078c8bb348896d", "parents": [ "20cf8511436b51d6ad4d0db246d23c470391c1ba" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed May 21 13:11:35 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu May 22 15:05:20 2025 +0000" }, "message": "fix(realm_payload): skip test setting invalid SVE VL\n\nSkip host_sve_realm_test_invalid_vl() test which creates\nRealm with invalid SVE VL in case when RMM reports maximum\narchitecturally supported value.\n\nChange-Id: I9ab1d4d500db03027917d4a2769e91260cc00d44\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "37fa6b9d4f0f059ec81f163bc230fa3598ef43c1", "tree": "f0acef78bd6752927910c90bb397e2694b8c206e", "parents": [ "fa267c12f9aa790b43b38d171273cf63892e8d51" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon May 19 14:54:12 2025 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed May 21 16:31:11 2025 +0000" }, "message": "fix(realm_payload): correct error messages\n\nCorrect messages for host_realm_fold_rtt()\nand host_rmi_rtt_readentry() functions in\ncase of errors.\n\nChange-Id: Iee19583698fe93bafb66d6b7ccf7ec938585560f\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "5ab09e8174e1ec17d6b1c35483f268e0775a5b67", "tree": "3be81b31149a1c413293061bd39d41c94d2416e6", "parents": [ "060efe97ff6c31b7dbec96af9fde0b169db4183d", "089c9ad705c1f393d95dd911c76a6772af45d1fd" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "message": "Merge changes from topic \"hm/handoff-mb\"\n\n* changes:\n feat(handoff): add event log test\n feat(measured-boot): add measured boot drivers\n" }, { "commit": "089c9ad705c1f393d95dd911c76a6772af45d1fd", "tree": "1842ee9a2fabfe773b56c98a76bb7e831b26b5a0", "parents": [ "b674809e4d937d44f85ef53aa2bdbb9f74b569b2" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:54 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:37 2025 +0000" }, "message": "feat(handoff): add event log test\n\nAdds a new TFTF test to validate presence and correctness of the TPM\nevent log in the transfer list received from EL3. Uses event_log_dump to\nparse and output log data.\n\nChange-Id: I0b1f782429e4bfe3d1760fce52d40a9836dc27a2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "060efe97ff6c31b7dbec96af9fde0b169db4183d", "tree": "bc0e18f218d5facba2ae30222dad21bc7f5f3bbd", "parents": [ "336f1c20beba190b912a83756ca91626b2860c14", "2230a5955d328b4a018e72163482690892f5ff59" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Apr 25 16:18:55 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 25 16:18:55 2025 +0200" }, "message": "Merge changes from topic \"fix_pmuv3p9_test\"\n\n* changes:\n feat(ras): add RAS system registers access test\n fix(smccc): availability test: add two features and fix TRNDR\n" }, { "commit": "336f1c20beba190b912a83756ca91626b2860c14", "tree": "9e8bc8ed7479036cf408fa4e88ea354a007ca817", "parents": [ "19620adc7cbcae26cc432a28a9c3b0944957cf13", "06de4bf32ac7a605946ed6af1ea2c51756fc43c4" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Apr 25 16:17:17 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 25 16:17:17 2025 +0200" }, "message": "Merge \"fix(pauth): test an actual ARMv8.3 PointerAuth instruction\"" }, { "commit": "6186cf96b9713be1a7cb7badd7166203b6145793", "tree": "b003e74f5d98b31f0581a3d85f7babcad255aedd", "parents": [ "aeb5c5ccb10a569c258d2b3e24841da4d234d3df", "6cd8b7d4a7d4d2177f5b51827e9d75321e2a9f90" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Apr 22 17:45:33 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Apr 22 17:45:33 2025 +0200" }, "message": "Merge \"test(trp): test el3-rmm ide km interface\"" }, { "commit": "6cd8b7d4a7d4d2177f5b51827e9d75321e2a9f90", "tree": "8f0136a08fbd66642f159d206ac71c65ea6b2bb4", "parents": [ "118652bf8a430b3085b9b79c589e12d8f80c1113" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Mon Mar 31 17:14:46 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Apr 10 14:54:10 2025 +0200" }, "message": "test(trp): test el3-rmm ide km interface\n\nThis patch introduces a new test function that invokes\nPDEV_CREATE on TRP and tests the RMM-EL3 IDE KM interface\nimplemented in EL3.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: Ib7e9e769191f94927b55b099a8c80d40ffc2a756\n" }, { "commit": "112498c703d48dceea63fe7ab88a8b243513e7e8", "tree": "e46a2cbaba245a68f17c37e32af0df852c331705", "parents": [ "f6f797b92f41b6850a8289e279c55c6f30563ec4" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Feb 18 11:52:12 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Apr 10 09:56:36 2025 +0000" }, "message": "feat(handoff): add AArch32 handoff support\n\nAdd support for testing firmware handoff in AArch32 mode. This requires\nsome tweaks to enable the boot args from TF-A to be stashed for later\nuse.\n\nChange-Id: Ib1b88688b6229b10020c936319605c7ed6307ca2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "06de4bf32ac7a605946ed6af1ea2c51756fc43c4", "tree": "237951fe262707336610b6d026fea666360df891", "parents": [ "0de678ef3e7136af91b314c893030311741a7f80" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Apr 04 13:29:35 2025 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Apr 04 17:27:06 2025 +0100" }, "message": "fix(pauth): test an actual ARMv8.3 PointerAuth instruction\n\nThe PAuth instruction test promises to test instructions associated with\nFEAT_PAUTH, though actually just issues those that are located in the\nNOP space, so would always execute, even on machines without FEAT_PAUTH.\n\nReplace them with one instruction that is newly defined by FEAY_PAUTH,\nand that would trigger an UNDEF abort if not implemented or would trap\nto EL3 unless SCR_EL3.API is set.\n\nChange-Id: Iece2c60af40800450dadf5b2db609c35cfa6cf95\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "11e574835b289bc3c9742d76ea697a53023527bc", "tree": "4671e58c1aef29334f69dec38de3b4ded5aa05ed", "parents": [ "a2b6b37ed6eaf7d0f9dfc12a04499863b25cf559" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 28 11:46:16 2025 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 01 13:19:18 2025 -0500" }, "message": "test: deny prohibited ABIs while handling CPU_OFF psci msg\n\nFF-A spec states that SPs are prohibited from invoking Direct request,\nFFA_RUN and FFA_YIELD interfaces while handling power management\nframework message. Make the Cactus SP intentionally invoke prohibited\ninterfaces and attest that SPMC should deny such invocations.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I0a823bf950e3895cb4aff7320c6a0ef7fdec634b\n" }, { "commit": "611d095453cf001e436f795ac8209b27f46a2fdb", "tree": "2435b48f94395c106adc5529e5031ccd92ca3197", "parents": [ "78fb528d0e2ecb53c533f6accf0da1f90d289353" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jan 31 16:07:08 2025 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 01 13:07:09 2025 -0500" }, "message": "feat(cactus): receive psci msg through direct req framework msg\n\nCactus receives PSCI CPU_OFF power management operation message\nthrough framework direct request message and it will respond back\nwith framework direct message if all conditions are met.\n\nCactus SP1 and SP2 explicitly subscribe to CPU_OFF power management\nmessage through their respective manifests.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I790a8698d238e29847e376b4fa9447a6241ef17e\n" }, { "commit": "a35c1db92b51bb785acef300975919bbb0a69aca", "tree": "c95b395d55d04f234c968909d6483fb356c8f251", "parents": [ "677708401f13bfa0c9d974aff8e3db3f67b77c5a" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Apr 01 12:14:25 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Apr 01 12:14:25 2025 +0100" }, "message": "fix(tests): undelegate pdev granules if DA ABI fails\n\nIn host_tdi_pdev_setup undelegate pdev and aux granules upon error\nso that the next testcase in the list doesn\u0027t encounter failure.\n\nThis issue is seen when RMM is build with RMM_V1_1\u003dON and DA ABI\nSMC_RMI_PDEV_AUX_COUNT fails.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I97614dbe7c41b89ff8b72db8cfb178d3c6067249\n" }, { "commit": "677708401f13bfa0c9d974aff8e3db3f67b77c5a", "tree": "9aa226627feb27c793ecb2894519550e18dadfd5", "parents": [ "41567dc5c36eb7cb0c621cc801e99543e95093b3", "8205a64846d581937e77919a9fe858db53324a84" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Mar 31 16:28:02 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 31 16:28:02 2025 +0200" }, "message": "Merge changes from topic \"km/ffa_features\"\n\n* changes:\n refactor: refactor `get_ffa_feature_test_target`\n refactor: use an enum for FF-A errors\n" }, { "commit": "8205a64846d581937e77919a9fe858db53324a84", "tree": "77b786526b95ab4219225966828b847eaf2546ab", "parents": [ "af77b16df26371cf954fd410359f55981683d1ea" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jun 19 15:05:19 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Mar 31 11:43:01 2025 +0100" }, "message": "refactor: refactor `get_ffa_feature_test_target`\n\nChange `get_ffa_feature_test_target` to return a `size_t` instead of an\n`unsigned int`, because `size_t` is the return type of operators like\n`sizeof()`.\n\nChange `get_ffa_feature_test_target` to require its argument to be\nnon-null (and assert that it is). This function is only used for getting\nthe array of features to test, so there is no use case where passing a\nnon-null pointer would make sense.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I33597f1a2f7681eda59ece08062e48c28752c111\n" }, { "commit": "2ba1e7812b494abdfb8f440a161f0ded24bee72a", "tree": "891b504323eff7bb91489d10ae33ed84613a15c3", "parents": [ "ab680e816552ea29184084482fdf63e2f94cd46a" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Mar 26 16:50:18 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Mar 26 17:15:06 2025 -0500" }, "message": "fix(errata_abi): update Cortex-A710 errata list\n\nThis patch updates the out-of-date parameter of Cortex-A710\u0027s\n2058056 erratum in Errata ABI test.\n\nChange-Id: I194eb7fea0504b532c2e15710fbe4b455b7e631b\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "2bd104e2fc8bdf1355ae88ad3e16af9773c1541f", "tree": "8e10eed6f9d1169da2c006f4d017ebe4dcafa4ea", "parents": [ "9d84ad1ceb8256e942213537602c6434577b7bc0" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Fri Mar 21 15:35:27 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Mar 25 04:49:16 2025 +0100" }, "message": "fix(realm): Fix the LPA2 flag setting for BRBE test\n\nThis patch fixes the LPA2 flag setting for BRBE test.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: Id7c53739cc92275a7018a44c2a3b8fdcf74ec25e\n" }, { "commit": "9d84ad1ceb8256e942213537602c6434577b7bc0", "tree": "f1069ac2c0ef008601b2892cae5960fba6665787", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "fb96b980c85d916b55c78b7d22e5b6d8e086ca54" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "message": "Merge changes from topic \"kc/fuzz\"\n\n* changes:\n test(fuzz): add FF-A fuzzing\n test(fuzz): Fix single feature testing\n" }, { "commit": "fb96b980c85d916b55c78b7d22e5b6d8e086ca54", "tree": "2a4c319dd3761099924e160acca59d4075bf749d", "parents": [ "2b6c140b52790beebbb921dd0311efefb0bb0c5c" ], "author": { "name": "Kathleen Capella", "email": "katcap01@u203721.austin.arm.com", "time": "Thu Apr 25 17:09:33 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Mar 11 12:10:59 2025 -0500" }, "message": "test(fuzz): add FF-A fuzzing\n\nAdd necessary components for FF-A calls to be used in fuzzing framework\nincluding bias tree, `run_ffa_fuzz` helper function, makefile additions,\nand initial SMC description file with FF-A smc calls.\n\nCan use ffa_smc_calls.txt to generate necessary header files.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ib19714342d31cacd818471686a7e4c8910fed5c3\n" }, { "commit": "2230a5955d328b4a018e72163482690892f5ff59", "tree": "7ac3698bb9d614af35f74999fc42f4ffee5d7ee3", "parents": [ "37e3f3e1d237b6e8289fbc0a090b2b4dd2d4b9ec" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 17:19:34 2025 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 17:30:44 2025 +0000" }, "message": "feat(ras): add RAS system registers access test\n\nFEAT_RAS introduces EL1 system registers to query error records, those\nCPU specific parts of the RAS extension can be accessed independently of\nany FFH/KFH handling setup or any system specific RAS implementation.\n\nAdd a test to verify that those registers can be read, when the CPUID\nfield advertises the MPAM (CPU) extension.\n\nChange-Id: I7429fc815e7e0ee0cd736603966969b2cfb5f469\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "37e3f3e1d237b6e8289fbc0a090b2b4dd2d4b9ec", "tree": "43448a6e0d637e635d482b1abf2144f0d7dda046", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Mar 07 17:25:24 2025 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 15:04:03 2025 +0000" }, "message": "fix(smccc): availability test: add two features and fix TRNDR\n\nThe SMCCC_ARCH_FEATURE_AVAILABILITY test was not up-to-date and was\nmissing two features: FEAT_TWED and FEAT_PMUV3P9. Connect the SCR_EL3\nand MDCR_EL3 bits to their corresponding ID register fields, so that\nthey can be tested.\n\nAt the same time the FEAT_RNG_TRAP test was slightly off: the SMCCC spec\nsays it should report accessibility of the RNDR and RNDRRS registers, so\nwe should look at FEAT_RNG, not FEAT_RNG_TRAP when checking the TRNDR\nbit.\n\nThis fixes the tf-a-tests run on an FVP with ARMv9.4 enabled, which was\nreporting the following issues before:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\u003e Executing \u0027SMCCC_ARCH_FEATURE_AVAILABILITY test\u0027\n TEST COMPLETE Failed\nis_feat_rng_trap_present says feature is supported but SCR_TRNDR_BIT was\n\tnot set!\nSCR_EL3 still has values set: 0x20000000. Test needs to be updated\nMDCR_EL3 still has values set: 0x80. Test needs to be updated\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nChange-Id: I73a0d240b2cd1a16e1c64d3d66ee30e658c9c946\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "tree": "a0ec5b6bff32d2fa1294f33af597c0d54558306e", "parents": [ "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "c8f5a2ee90f2b376da910f08170af4c4dc7396ae" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "message": "Merge \"test: test the save restore logic for brbcr_el1\"" }, { "commit": "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "tree": "62adf8c4bbb438943acb6e46b52170803509a17b", "parents": [ "3d43731d485b1405c5a224f65a7c2d381d46b093", "43980f9070347622ec9b9ff1b360357a954e96f2" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Sun Mar 09 01:28:21 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sun Mar 09 01:28:21 2025 +0100" }, "message": "Merge \"test(realm): Fix Realm tests marking all memory as RAM\"" }, { "commit": "43980f9070347622ec9b9ff1b360357a954e96f2", "tree": "64495265719ce7b62c47bc5f720d88eec5ee15e9", "parents": [ "90506fbda56864b578980bc2d433f2ba38207e61" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Mar 07 20:35:21 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Mar 07 20:35:21 2025 +0000" }, "message": "test(realm): Fix Realm tests marking all memory as RAM\n\nRealm tests only need access to part of DRAM.\nChange only required region RIPAS to RAM.\n\nChange-Id: Ia0120841e51726785062992e8a32dcd8a924a325\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "3d43731d485b1405c5a224f65a7c2d381d46b093", "tree": "c8d15de87f5a5155e57a145d43cbeb18c118f33f", "parents": [ "9b63fa56b4e21ecb87d409c6a95d1d3d5ee06376", "5668f34a89dfcee72c2a8e6aa443c7436f341d61" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "message": "Merge \"fix: add split workaround check in Errata ABI test\"" }, { "commit": "c8f5a2ee90f2b376da910f08170af4c4dc7396ae", "tree": "625509a3d6d8838e0c31c9e89fbf23ed9361d15f", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Tue Feb 04 15:22:01 2025 -0600" }, "committer": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Mar 06 16:55:05 2025 -0600" }, "message": "test: test the save restore logic for brbcr_el1\n\nThis patch tests the save/restore logic by enabling\nbranch recording at NS-EL2. Additionally this\npatch also tests the trap logic when FEAT_FGT is enabled\nand a Realm tries to access any FEAT_BRBE related registers.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I176ea6feaf01d42cfd6231dc65a9470da8d1e37c\n" }, { "commit": "55d5db87b83b6a073ed3c954d455b862e7b2e7fe", "tree": "0019d75c61f3cbac06bc2f1e25d5944c8f9f3880", "parents": [ "7d3b999376c7416584639411f36bdadf877060d3" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Mar 03 12:56:04 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 21:08:59 2025 +0000" }, "message": "test(realm): extend ripas tests for planes\n\nTest that accessing page with RIPAS\u003dEMPTY from\nPlane N causes plane exit to P0.\n\nChange-Id: Ic57f049d0fa0140630aa7bfc0702a2dc729967a8\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "7d3b999376c7416584639411f36bdadf877060d3", "tree": "c22c6390ab2ec7977af1483c1d4dbf56bd2d388f", "parents": [ "bd729193dcdb19a5f5fa9b259770f1d1f365bad0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 25 15:39:55 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 19:50:15 2025 +0000" }, "message": "test(realm): enhance realm memory exception tests for planes\n\nExtend memory exception tests for planes.\n\nChange-Id: Ifc98b8c67e85b04b36a78f16971d17f05d6a87d2\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "5668f34a89dfcee72c2a8e6aa443c7436f341d61", "tree": "9a7778183d2dedaa383e4c517a4a17dae6a7fa49", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Mar 04 02:01:16 2025 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Mar 06 12:43:08 2025 -0600" }, "message": "fix: add split workaround check in Errata ABI test\n\nThis patch adds support to validate split workarounds\nas part of Errata ABI CPU Features testcase. It also\nimproves the test case, making sure it also\nruns on lead cpu.\n\nChange-Id: Ic21fffdf20714ad639e92ad0be96d2f154f37f04\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "bd729193dcdb19a5f5fa9b259770f1d1f365bad0", "tree": "00c47d7308aee2d02a16a3d4a5fbacaf7cf4407d", "parents": [ "78effaa2c47b04abd68273bdea4ebb4f6f9455c0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 24 17:02:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:57:56 2025 +0000" }, "message": "test(realm): add test for multi rec planes\n\nTest exercises SMC_PSCI_CPU_ON from aux plane.\nRequest is first routed to P0 and then to Host.\nHost enters P0 and then P1 on all CPUs.\n\nChange-Id: I7e34a0070ffa7305b97a0d93de62b64042771a18\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "78effaa2c47b04abd68273bdea4ebb4f6f9455c0", "tree": "9ffb7b9430ee5600da7f8e0cd5cd557752ea85fa", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 07 10:30:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:18:01 2025 +0000" }, "message": "test(realm): validate NS EL1/EL2 context is preserved by RMM\n\n- Test validates that NS EL1/EL2 registers are preserved while\n entering and exiting realm world.\n- Test validates that accessing s2por_el1 in realm causes data abort.\n\nChange-Id: I20cbb9d0d59474507f89ee7cf8e127fff4706610\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "dc26dfe297eaed205fdbf8a0f98706044a97032d", "tree": "730acf129621c21de4c680668a5b8391446f74b1", "parents": [ "de01b5dd3ae940a16ad9f370ad1e734190553e73" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 25 16:12:48 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 28 13:01:34 2025 +0000" }, "message": "test(realm): fix bug in RMI_RTT_SET_S2AP command helper\n\npass correct rec adr to RMI_RTT_SET_S2AP command.\nRSI_MEM_SET_PERM_INDEX can be called from any rec.\n\nChange-Id: I701d7f7f9de80f305d10d2582c614b3090fc2ac5\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "de01b5dd3ae940a16ad9f370ad1e734190553e73", "tree": "9dcf2ef13e4449a8322e044da38a1ed94579e171", "parents": [ "6164898b4355bf1f311a78f0796a75baf7f50983" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 02 21:17:11 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 28 13:01:16 2025 +0000" }, "message": "test(realm): add support for s2poe/pie for planes\n\nAdd support for s2poe/pie for planes.\nUpdate planes test to run with s2poe/s2pie\nboth enabled and disabled.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If85b8c4cff9e8fe43978088beaf848fe4b2b9a40\n" }, { "commit": "42dd088203e40911c67106d46cfccde58d55e1b5", "tree": "48f1d07ae117eadadd1c0496cc0a8ad895abff3b", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd", "c779d0d0ac9faf894963675dcccb6110e3f0229a" ], "author": { "name": "Sandrine Afsa", "email": "sandrine.afsa@arm.com", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "message": "Merge changes from topic \"xlnx_fix_custom_inval_entry\"\n\n* changes:\n fix(versal): platform definition of invalid entry\n feat(tftf): new interface to get an invalid entrypoint address\n" }, { "commit": "1e4f7a064f08205a0a37922e660b238be04a8137", "tree": "ccf0e6f9e63ee23a7b249eed564ceedafcee9035", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:40:56 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:16 2025 +0000" }, "message": "feat(tftf): new interface to get an invalid entrypoint address\n\nTFTF test for invalid entry address in cpu hotplug, validates\nfor default entry address 0x0 which doesn\u0027t account for platforms\nfor which 0x0 is a valid address. Added function to retrieve invalid\nentry address for default scenario and platform implementation to\nretrieve specific custom invalid entry address.\n\nChange-Id: I9f109acc8d0443dabd3088cb31852900e8e07853\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "2f2bd013021b4723d42c168f613c4c0ca37223bd", "tree": "968260569451b377582640305eea94d206d9a42c", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e", "af8934c8574fd64bef6ac4b0201c2144b78c8fd7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "message": "Merge \"test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\"" }, { "commit": "effca4c7db126c7e171256a8a85b60e599274c4d", "tree": "d1abf091b8992adae634a55a98ced19523f676f1", "parents": [ "b298a166f8490bb997b794ab404afa5eaae15fa1" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 16:52:23 2025 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 19:03:22 2025 -0600" }, "message": "refactor(errata_abi): add Cortex-X925 and update Cortex-X4\n\nUpdate errate list for Cortex-X4 and add Cortex-X925\nerratum list and support.\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: Ib4e3324e7289d8e400e9a7f90e384d36cdd8bbcb\n" }, { "commit": "5bccf1d188115e268101024018d26b710c86d3c9", "tree": "a185504f6b740a4bfc63fc62f8ee8d91f08d4791", "parents": [ "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "message": "fix(realm): fix PMU save/restore registers\n\nRemove pmxevcntr_el0 and pmxevtyper_el0 registers\nfrom saving/restoring as aliases for pmevcntrN_el0\nand pmevtyperN_el0, selected by pmselr_el0.sel.\n\nChange-Id: I3def527c46d53c3203f7c3ebc565a2aaf282309c\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "tree": "010803c4d3fb8186d23cfd2f54f923c8271b45cd", "parents": [ "23ec8506918aff276b21b9543831d4825855906d", "82cd82e9868b1f381a5c8d84195657e1583cfca1" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "message": "Merge \"feat(rme): add tests for FEAT_MPAM on Realms\"" }, { "commit": "82cd82e9868b1f381a5c8d84195657e1583cfca1", "tree": "c7be244d493e784e55df370f501d8c3ba9275523", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jan 17 17:37:42 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Feb 04 15:01:14 2025 +0000" }, "message": "feat(rme): add tests for FEAT_MPAM on Realms\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6e138cbf121793bdaaa3a44824c0dbff74daced1\n" }, { "commit": "c398c8f7248e9aec29bbc41c94e41005d539863c", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jan 16 14:35:48 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Feb 04 11:38:28 2025 +0000" }, "message": "fix(realm): fix realm PMU tests\n\n- FEATURE_PMU_NUM_CTRS field in feature_flag was used\nto pass number of PMU event counters in realm creation.\nThe width of this field was set to 4, which was not\nenough to pass numbers \u003e 15 and was causing PMU tests\nfailures in FVP configuration with more than 15 event\ncounters implemented.\n- This patch removes all FEATURE_XXX macros for setting\nfeature_flag and replaces them with the corresponding\nRMI_FEATURE_REGISTER_0_XXX to match feature register 0.\n- In host_set_pmu_state() function was setting PMSELR_EL0\nto incorrect value 0 instead of 31 to select PMU cycle\ncounter for configurations with no event counters implemented.\n- Test host_realm_pmuv3_mul_rec() was running incorrectly\nwith number of event counters set to 0 or 31.\n- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0\ncan be constrained unpredictable depending on the\nvalue of PMSELR_EL0.SEL and number of accessible event\ncounters. See corresponding TF-RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573\nThis patch fixes host_set_pmu_state() and\nhost_check_pmu_state() functions to avoid unpredictable access\nto these registers.\nThis patch makes Realm PMU tests pass for all possible FVP\nconfigurations clusterN.pmu-num_counters\u003d[0...31].\n\nChange-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "042541196fbdd814a7c04ee4e24be94f1a2ab4ef", "tree": "0852b3939e094f0d2fd4b848f3ebb617bfa6efd0", "parents": [ "c8943ba881807922cb84e357461f5482475a47c3", "47078f35247dcb85f5a1ce8ea0bc52d3aee74451" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "message": "Merge changes I7c4ad397,I92e0aeef\n\n* changes:\n test(realm): fix multi rec PMU tests\n test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n" }, { "commit": "c8943ba881807922cb84e357461f5482475a47c3", "tree": "a951dd70d63e29f3616dc48935890f96c8b52fab", "parents": [ "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "message": "Merge changes from topic \"fuzzinit\"\n\n* changes:\n test(fuzz) adding fuzzing for vendor-el3 smccc calls\n test(fuzz) adding fuzzing for all SDEI calls\n test(fuzz): Capability for random inputs\n" }, { "commit": "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c", "tree": "fcf9d81e4b95ffd31ccf36df51df4e1bd0e19221", "parents": [ "0fa7d21bf97d14283ebf8c3df866cd05afaff91e" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jul 23 16:42:16 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 15:13:10 2025 -0600" }, "message": "test(fuzz) adding fuzzing for vendor-el3 smccc calls\n\nChange-Id: I4fd64c0a4c02de6d67a372c9c4bf86bcb9e4d091\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "0fa7d21bf97d14283ebf8c3df866cd05afaff91e", "tree": "b1927aea547dcd718dccc20301cbc301d986faec", "parents": [ "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jun 18 11:17:01 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 14:03:27 2025 -0600" }, "message": "test(fuzz) adding fuzzing for all SDEI calls\n\nadded constraints for all calls\nadded fuzzer feature to start at arbitrary call number\nadded fuzzer features for function exclusion, fuzzer starting/ending call\nworked on additional fuzzing for event_register\n\nChange-Id: I9814b8387ea9e0fb00b53adbdbe0f8429845924e\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "47078f35247dcb85f5a1ce8ea0bc52d3aee74451", "tree": "03562b94399c44ff32b0c1f81d1c8e35016d8e4f", "parents": [ "414346805fa6589643780f6f9ce181facf2e1271" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 16 18:54:24 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 17:44:19 2025 +0000" }, "message": "test(realm): fix multi rec PMU tests\n\n- set different values of PMU event counters for each rec\n- check PMU counters are preserved for each rec\n\nChange-Id: I7c4ad3971d4a10b4515be0dfe096bebf8d903c71\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "tree": "ff6e9cd81f0c19684cf5b58067d02d58f1738b19", "parents": [ "506b98f78e4bb38314129f85da27523f18dd8f8f", "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "message": "Merge changes I7a3b9103,I590fc5a1,Ie6924bcb,I484cbd32\n\n* changes:\n test(realm): add testcase to enter all planes\n test(realm): handle permission fault for planes\n test(realm): add support for planes shared buffer\n test(realm): add plane PSI interface\n" }, { "commit": "af8934c8574fd64bef6ac4b0201c2144b78c8fd7", "tree": "33c29f9b95a29b2b879fc8055d994787b5e79fce", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Fri Jul 26 14:51:14 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Jan 31 16:48:58 2025 +0000" }, "message": "test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\n\n* This patch adds a test that suspends to affinity level 2 with another\n CPU running in a different power domain.\n\n* Previously with the bug identified and resolved in commit (01959a1),\n the function \"psci_is_last_cpu_to_idle_at_pwrlvl\" checked only one\n power domain when suspending to level2. This meant that if there was\n a cpu running outside the power domain of the calling CPU, the suspend\n request would be allowed. But in this case, the request should be\n denied. This test case validates this behaviour and ensures the\n request is denied.\n\n* This patch also adds the following global variables to parameterise\n and reuse the existing functions for the new test.\n * test_should_suspend - an boolean array that allows you to leave\n some CPUs running.\n * test_should_deny - a boolean to specify if the suspend request\n should be denied.\n * cpu_finished - an array of events so that the running CPUs know\n when to terminate.\n\n* Additionally this patch also adds a function to get a CPU that is\n in a different cluster to the lead CPU.\n\nRefer to TF-A commit (01959a1) for more information on the bug.\n\nChange-Id: Ib163aa8d5347baeaa47d1ae6f59599f1c68c11a8\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb", "tree": "506eaf722681380325bde2a5a9de784697915ba9", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Mar 15 12:49:22 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 10:23:24 2025 -0600" }, "message": "test(fuzz): Capability for random inputs\n\nAdding model for random inputs to SMC calls using a\nconstraint mechanism with a multi tiered sanity\nmetric.\n\nChange-Id: Ia750fa57359baa424f1af273ba24483ae7330c38\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "506b98f78e4bb38314129f85da27523f18dd8f8f", "tree": "da255312e5288c911622d83ee21bf8f2cf790a83", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "43d421bb292984fdc56269fb3e87e619ca0892d3" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "message": "Merge \"test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\"" }, { "commit": "414346805fa6589643780f6f9ce181facf2e1271", "tree": "69b825442caff18f8b25d6eee80140c80832d176", "parents": [ "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Dec 05 14:57:48 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 14:53:41 2025 +0000" }, "message": "test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n\ntest for RSI_PLANE_REG_READ/WRITE command\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I92e0aeef48c9b2abe26e5d3b2ea62669a22d4f8b\n" }, { "commit": "158208e895d38d659d216c793d42d132ed90e598", "tree": "86cf20c9982b4b186bcc17944cd9f569701f6fe4", "parents": [ "a0736c3dbf83f3c00ca98c83534070be259fb822" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 10:12:41 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:23 2025 +0000" }, "message": "test(realm): add testcase to enter all planes\n\nTestcase creates realm with all 4 planes.\nEnters all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I7a3b9103e1fbcfe98117c02827624a2fc2d24fc2\n" }, { "commit": "a0736c3dbf83f3c00ca98c83534070be259fb822", "tree": "4ab625c28b93f9fe02b4072720ab05a342175b26", "parents": [ "69cae79515b85f13a3ee957474231e51e879c4d8" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 09:34:35 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:12 2025 +0000" }, "message": "test(realm): handle permission fault for planes\n\nAdd support for handling permission fault in planes.\nSet s2ap in RTTs.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I590fc5a1c43357b117fa5cb76e8c699c4c7eebad\n" }, { "commit": "69cae79515b85f13a3ee957474231e51e879c4d8", "tree": "80f41a9c19830d92bf024f5c9eabf65e2b505a5a", "parents": [ "9110508906774bb3949fa5609a5d767021a6a4e8" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 04:30:00 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:53:44 2025 +0000" }, "message": "test(realm): add support for planes shared buffer\n\n- Add support for per plane shared buffer.\n- Map shared buffer in all Aux RTT if\n realm uses multiple RTTs.\n- Support realm_printf for all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie6924bcb9e9bb3b8c368f796d33f84f4f6821935\n" }, { "commit": "9110508906774bb3949fa5609a5d767021a6a4e8", "tree": "8233efd6cb8467288ae76544c0682c4e89766dc2", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 05:29:55 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:53:25 2025 +0000" }, "message": "test(realm): add plane PSI interface\n\nAdd Plane service routine interface.\nAux plane can communicate with primary plane using PSI\nPSI uses hvc conduit from aux plane.\nAdd initial printf support for planes\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I484cbd32791970c6e22c5d63e13b43807f4f3c06\n" }, { "commit": "43d421bb292984fdc56269fb3e87e619ca0892d3", "tree": "2d0fe5cbece559a93ff6eb935d36bc0dadf2a4d8", "parents": [ "ff52ad6026cbbd688f9c381a48110148e01dcf45" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Sep 11 12:01:56 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jan 30 11:51:52 2025 -0600" }, "message": "test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\n\nTesting was conducted using FVP Version 11.26.11\non Cortex-X3, Cortex-X4, Neoverse-V2, Neoverse-V3\nand Cortex-X925. Additionally, negative testing\nwas performed on Cortex-X2.\n\nThis patch tests SMCCC_ARCH_WORKAROUND_4 [1] for CVE_2024_7881 [2]\n[1]: https://developer.arm.com/documentation/den0028/latest\n[2]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881\n\nChange-Id: I4c33b7a9372236ce3ef38f9d1786d5794bb7ddbc\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" } ], "next": "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" }