)]}' { "log": [ { "commit": "716c8cc0951fb6a3e212d4bd9b79ea0b6f9bdf9b", "tree": "858cebc6186fb65cc28fc02883dec4a112534603", "parents": [ "42dd088203e40911c67106d46cfccde58d55e1b5" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Feb 25 18:22:45 2025 +0000" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Feb 26 11:33:37 2025 +0000" }, "message": "fix(lib/pcie): bdf macro\n\nThe existing PCIE_CREATE_BDF macro is a non standard way of deriving bdf\nvalue. This fix assigns 3 bits for function number, 5 bits for device\nnumber and 8 bits for bus. This bdf value is used as TDISP function id\nwhile passing it to DSM. Using a wrong bdf value results the TDISP\ncommand to fail.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I31301be4dfc9bd2409da73e54715f73079a921cb\n" }, { "commit": "42dd088203e40911c67106d46cfccde58d55e1b5", "tree": "48f1d07ae117eadadd1c0496cc0a8ad895abff3b", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd", "c779d0d0ac9faf894963675dcccb6110e3f0229a" ], "author": { "name": "Sandrine Afsa", "email": "sandrine.afsa@arm.com", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "message": "Merge changes from topic \"xlnx_fix_custom_inval_entry\"\n\n* changes:\n fix(versal): platform definition of invalid entry\n feat(tftf): new interface to get an invalid entrypoint address\n" }, { "commit": "c779d0d0ac9faf894963675dcccb6110e3f0229a", "tree": "66a0d99df1847e1ac663da0a378e4d92f3ba63bd", "parents": [ "1e4f7a064f08205a0a37922e660b238be04a8137" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:43:37 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:47 2025 +0000" }, "message": "fix(versal): platform definition of invalid entry\n\nAdd platform specific function to return custom entry address.\n\nChange-Id: I58785a8b7c197e4dae3ac9a29f8d23c29d5cb5e3\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "1e4f7a064f08205a0a37922e660b238be04a8137", "tree": "ccf0e6f9e63ee23a7b249eed564ceedafcee9035", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:40:56 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:16 2025 +0000" }, "message": "feat(tftf): new interface to get an invalid entrypoint address\n\nTFTF test for invalid entry address in cpu hotplug, validates\nfor default entry address 0x0 which doesn\u0027t account for platforms\nfor which 0x0 is a valid address. Added function to retrieve invalid\nentry address for default scenario and platform implementation to\nretrieve specific custom invalid entry address.\n\nChange-Id: I9f109acc8d0443dabd3088cb31852900e8e07853\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "2f2bd013021b4723d42c168f613c4c0ca37223bd", "tree": "968260569451b377582640305eea94d206d9a42c", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e", "af8934c8574fd64bef6ac4b0201c2144b78c8fd7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "message": "Merge \"test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\"" }, { "commit": "af821ebb6fa509f8036b2304c313883842d2c93e", "tree": "d1abf091b8992adae634a55a98ced19523f676f1", "parents": [ "b298a166f8490bb997b794ab404afa5eaae15fa1", "effca4c7db126c7e171256a8a85b60e599274c4d" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Feb 12 18:51:15 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 12 18:51:15 2025 +0100" }, "message": "Merge \"refactor(errata_abi): add Cortex-X925 and update Cortex-X4\"" }, { "commit": "effca4c7db126c7e171256a8a85b60e599274c4d", "tree": "d1abf091b8992adae634a55a98ced19523f676f1", "parents": [ "b298a166f8490bb997b794ab404afa5eaae15fa1" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 16:52:23 2025 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 19:03:22 2025 -0600" }, "message": "refactor(errata_abi): add Cortex-X925 and update Cortex-X4\n\nUpdate errate list for Cortex-X4 and add Cortex-X925\nerratum list and support.\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: Ib4e3324e7289d8e400e9a7f90e384d36cdd8bbcb\n" }, { "commit": "b298a166f8490bb997b794ab404afa5eaae15fa1", "tree": "a185504f6b740a4bfc63fc62f8ee8d91f08d4791", "parents": [ "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "5bccf1d188115e268101024018d26b710c86d3c9" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Feb 06 11:59:13 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 06 11:59:13 2025 +0100" }, "message": "Merge \"fix(realm): fix PMU save/restore registers\"" }, { "commit": "5bccf1d188115e268101024018d26b710c86d3c9", "tree": "a185504f6b740a4bfc63fc62f8ee8d91f08d4791", "parents": [ "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "message": "fix(realm): fix PMU save/restore registers\n\nRemove pmxevcntr_el0 and pmxevtyper_el0 registers\nfrom saving/restoring as aliases for pmevcntrN_el0\nand pmevtyperN_el0, selected by pmselr_el0.sel.\n\nChange-Id: I3def527c46d53c3203f7c3ebc565a2aaf282309c\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "tree": "010803c4d3fb8186d23cfd2f54f923c8271b45cd", "parents": [ "23ec8506918aff276b21b9543831d4825855906d", "82cd82e9868b1f381a5c8d84195657e1583cfca1" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "message": "Merge \"feat(rme): add tests for FEAT_MPAM on Realms\"" }, { "commit": "23ec8506918aff276b21b9543831d4825855906d", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658", "c398c8f7248e9aec29bbc41c94e41005d539863c" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 11:56:02 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 11:56:02 2025 +0100" }, "message": "Merge \"fix(realm): fix realm PMU tests\"" }, { "commit": "82cd82e9868b1f381a5c8d84195657e1583cfca1", "tree": "c7be244d493e784e55df370f501d8c3ba9275523", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jan 17 17:37:42 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Feb 04 15:01:14 2025 +0000" }, "message": "feat(rme): add tests for FEAT_MPAM on Realms\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6e138cbf121793bdaaa3a44824c0dbff74daced1\n" }, { "commit": "c398c8f7248e9aec29bbc41c94e41005d539863c", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jan 16 14:35:48 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Feb 04 11:38:28 2025 +0000" }, "message": "fix(realm): fix realm PMU tests\n\n- FEATURE_PMU_NUM_CTRS field in feature_flag was used\nto pass number of PMU event counters in realm creation.\nThe width of this field was set to 4, which was not\nenough to pass numbers \u003e 15 and was causing PMU tests\nfailures in FVP configuration with more than 15 event\ncounters implemented.\n- This patch removes all FEATURE_XXX macros for setting\nfeature_flag and replaces them with the corresponding\nRMI_FEATURE_REGISTER_0_XXX to match feature register 0.\n- In host_set_pmu_state() function was setting PMSELR_EL0\nto incorrect value 0 instead of 31 to select PMU cycle\ncounter for configurations with no event counters implemented.\n- Test host_realm_pmuv3_mul_rec() was running incorrectly\nwith number of event counters set to 0 or 31.\n- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0\ncan be constrained unpredictable depending on the\nvalue of PMSELR_EL0.SEL and number of accessible event\ncounters. See corresponding TF-RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573\nThis patch fixes host_set_pmu_state() and\nhost_check_pmu_state() functions to avoid unpredictable access\nto these registers.\nThis patch makes Realm PMU tests pass for all possible FVP\nconfigurations clusterN.pmu-num_counters\u003d[0...31].\n\nChange-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "f00a425e1592bd410ff249c1baab8f3b067b1658", "tree": "ec2b7f39414b02fb21446494409ae1729930aaa3", "parents": [ "042541196fbdd814a7c04ee4e24be94f1a2ab4ef", "cd46f276f845a4628982e85dfc38054fc94aa5c3" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Feb 03 15:46:20 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 03 15:46:20 2025 +0100" }, "message": "Merge \"feat: specify the secure partition package for an SP\"" }, { "commit": "042541196fbdd814a7c04ee4e24be94f1a2ab4ef", "tree": "0852b3939e094f0d2fd4b848f3ebb617bfa6efd0", "parents": [ "c8943ba881807922cb84e357461f5482475a47c3", "47078f35247dcb85f5a1ce8ea0bc52d3aee74451" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "message": "Merge changes I7c4ad397,I92e0aeef\n\n* changes:\n test(realm): fix multi rec PMU tests\n test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n" }, { "commit": "c8943ba881807922cb84e357461f5482475a47c3", "tree": "a951dd70d63e29f3616dc48935890f96c8b52fab", "parents": [ "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "message": "Merge changes from topic \"fuzzinit\"\n\n* changes:\n test(fuzz) adding fuzzing for vendor-el3 smccc calls\n test(fuzz) adding fuzzing for all SDEI calls\n test(fuzz): Capability for random inputs\n" }, { "commit": "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c", "tree": "fcf9d81e4b95ffd31ccf36df51df4e1bd0e19221", "parents": [ "0fa7d21bf97d14283ebf8c3df866cd05afaff91e" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jul 23 16:42:16 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 15:13:10 2025 -0600" }, "message": "test(fuzz) adding fuzzing for vendor-el3 smccc calls\n\nChange-Id: I4fd64c0a4c02de6d67a372c9c4bf86bcb9e4d091\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "0fa7d21bf97d14283ebf8c3df866cd05afaff91e", "tree": "b1927aea547dcd718dccc20301cbc301d986faec", "parents": [ "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jun 18 11:17:01 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 14:03:27 2025 -0600" }, "message": "test(fuzz) adding fuzzing for all SDEI calls\n\nadded constraints for all calls\nadded fuzzer feature to start at arbitrary call number\nadded fuzzer features for function exclusion, fuzzer starting/ending call\nworked on additional fuzzing for event_register\n\nChange-Id: I9814b8387ea9e0fb00b53adbdbe0f8429845924e\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "47078f35247dcb85f5a1ce8ea0bc52d3aee74451", "tree": "03562b94399c44ff32b0c1f81d1c8e35016d8e4f", "parents": [ "414346805fa6589643780f6f9ce181facf2e1271" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 16 18:54:24 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 17:44:19 2025 +0000" }, "message": "test(realm): fix multi rec PMU tests\n\n- set different values of PMU event counters for each rec\n- check PMU counters are preserved for each rec\n\nChange-Id: I7c4ad3971d4a10b4515be0dfe096bebf8d903c71\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "tree": "ff6e9cd81f0c19684cf5b58067d02d58f1738b19", "parents": [ "506b98f78e4bb38314129f85da27523f18dd8f8f", "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "message": "Merge changes I7a3b9103,I590fc5a1,Ie6924bcb,I484cbd32\n\n* changes:\n test(realm): add testcase to enter all planes\n test(realm): handle permission fault for planes\n test(realm): add support for planes shared buffer\n test(realm): add plane PSI interface\n" }, { "commit": "af8934c8574fd64bef6ac4b0201c2144b78c8fd7", "tree": "33c29f9b95a29b2b879fc8055d994787b5e79fce", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Fri Jul 26 14:51:14 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Jan 31 16:48:58 2025 +0000" }, "message": "test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\n\n* This patch adds a test that suspends to affinity level 2 with another\n CPU running in a different power domain.\n\n* Previously with the bug identified and resolved in commit (01959a1),\n the function \"psci_is_last_cpu_to_idle_at_pwrlvl\" checked only one\n power domain when suspending to level2. This meant that if there was\n a cpu running outside the power domain of the calling CPU, the suspend\n request would be allowed. But in this case, the request should be\n denied. This test case validates this behaviour and ensures the\n request is denied.\n\n* This patch also adds the following global variables to parameterise\n and reuse the existing functions for the new test.\n * test_should_suspend - an boolean array that allows you to leave\n some CPUs running.\n * test_should_deny - a boolean to specify if the suspend request\n should be denied.\n * cpu_finished - an array of events so that the running CPUs know\n when to terminate.\n\n* Additionally this patch also adds a function to get a CPU that is\n in a different cluster to the lead CPU.\n\nRefer to TF-A commit (01959a1) for more information on the bug.\n\nChange-Id: Ib163aa8d5347baeaa47d1ae6f59599f1c68c11a8\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb", "tree": "506eaf722681380325bde2a5a9de784697915ba9", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Mar 15 12:49:22 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 10:23:24 2025 -0600" }, "message": "test(fuzz): Capability for random inputs\n\nAdding model for random inputs to SMC calls using a\nconstraint mechanism with a multi tiered sanity\nmetric.\n\nChange-Id: Ia750fa57359baa424f1af273ba24483ae7330c38\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "506b98f78e4bb38314129f85da27523f18dd8f8f", "tree": "da255312e5288c911622d83ee21bf8f2cf790a83", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "43d421bb292984fdc56269fb3e87e619ca0892d3" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "message": "Merge \"test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\"" }, { "commit": "414346805fa6589643780f6f9ce181facf2e1271", "tree": "69b825442caff18f8b25d6eee80140c80832d176", "parents": [ "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Dec 05 14:57:48 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 14:53:41 2025 +0000" }, "message": "test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n\ntest for RSI_PLANE_REG_READ/WRITE command\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I92e0aeef48c9b2abe26e5d3b2ea62669a22d4f8b\n" }, { "commit": "158208e895d38d659d216c793d42d132ed90e598", "tree": "86cf20c9982b4b186bcc17944cd9f569701f6fe4", "parents": [ "a0736c3dbf83f3c00ca98c83534070be259fb822" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 10:12:41 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:23 2025 +0000" }, "message": "test(realm): add testcase to enter all planes\n\nTestcase creates realm with all 4 planes.\nEnters all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I7a3b9103e1fbcfe98117c02827624a2fc2d24fc2\n" }, { "commit": "a0736c3dbf83f3c00ca98c83534070be259fb822", "tree": "4ab625c28b93f9fe02b4072720ab05a342175b26", "parents": [ "69cae79515b85f13a3ee957474231e51e879c4d8" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 09:34:35 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:12 2025 +0000" }, "message": "test(realm): handle permission fault for planes\n\nAdd support for handling permission fault in planes.\nSet s2ap in RTTs.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I590fc5a1c43357b117fa5cb76e8c699c4c7eebad\n" }, { "commit": "69cae79515b85f13a3ee957474231e51e879c4d8", "tree": "80f41a9c19830d92bf024f5c9eabf65e2b505a5a", "parents": [ "9110508906774bb3949fa5609a5d767021a6a4e8" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 04:30:00 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:53:44 2025 +0000" }, "message": "test(realm): add support for planes shared buffer\n\n- Add support for per plane shared buffer.\n- Map shared buffer in all Aux RTT if\n realm uses multiple RTTs.\n- Support realm_printf for all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie6924bcb9e9bb3b8c368f796d33f84f4f6821935\n" }, { "commit": "9110508906774bb3949fa5609a5d767021a6a4e8", "tree": "8233efd6cb8467288ae76544c0682c4e89766dc2", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 05:29:55 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:53:25 2025 +0000" }, "message": "test(realm): add plane PSI interface\n\nAdd Plane service routine interface.\nAux plane can communicate with primary plane using PSI\nPSI uses hvc conduit from aux plane.\nAdd initial printf support for planes\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I484cbd32791970c6e22c5d63e13b43807f4f3c06\n" }, { "commit": "43d421bb292984fdc56269fb3e87e619ca0892d3", "tree": "2d0fe5cbece559a93ff6eb935d36bc0dadf2a4d8", "parents": [ "ff52ad6026cbbd688f9c381a48110148e01dcf45" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Sep 11 12:01:56 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jan 30 11:51:52 2025 -0600" }, "message": "test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\n\nTesting was conducted using FVP Version 11.26.11\non Cortex-X3, Cortex-X4, Neoverse-V2, Neoverse-V3\nand Cortex-X925. Additionally, negative testing\nwas performed on Cortex-X2.\n\nThis patch tests SMCCC_ARCH_WORKAROUND_4 [1] for CVE_2024_7881 [2]\n[1]: https://developer.arm.com/documentation/den0028/latest\n[2]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881\n\nChange-Id: I4c33b7a9372236ce3ef38f9d1786d5794bb7ddbc\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "tree": "05125c5f936c21bd2d9cc5915bf9544333182bd9", "parents": [ "079c37c7aaf219182d7061427e22c65aaa416b37", "ff2f1150099940a2767381df1701c9007eec8e68" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "message": "Merge changes from topic \"qemu_tests\"\n\n* changes:\n fix(test): compile error in test_irq_spurious_gicv2.c\n feat(timer): support PPI timer interrupts\n" }, { "commit": "079c37c7aaf219182d7061427e22c65aaa416b37", "tree": "31c1eabeaf17fcec944f87cee1464f62697ab5eb", "parents": [ "ff52ad6026cbbd688f9c381a48110148e01dcf45", "3fa036df6a185bcc50ef1c50b79b272e39fd7bc1" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jan 30 13:20:26 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 30 13:20:26 2025 +0100" }, "message": "Merge \"test(realm): fix compilation errors\"" }, { "commit": "3fa036df6a185bcc50ef1c50b79b272e39fd7bc1", "tree": "31c1eabeaf17fcec944f87cee1464f62697ab5eb", "parents": [ "ff52ad6026cbbd688f9c381a48110148e01dcf45" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 30 09:21:53 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 30 09:28:51 2025 +0000" }, "message": "test(realm): fix compilation errors\n\nFix compilation errors when LOG_LEVEL is verbose.\n\nChange-Id: Ic87a7ad901e1cd57a20d6ae14fbd4d8165e4e168\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "ff52ad6026cbbd688f9c381a48110148e01dcf45", "tree": "f6365f83d2b39cbfbe06fe6470fa4c970c226412", "parents": [ "1209ea4679769070dd7bf7c316354ce840060378", "6681b7a6fc142f8b1ba0f97d41d239fe6e874c37" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Jan 29 19:17:23 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 29 19:17:23 2025 +0100" }, "message": "Merge \"fix: skip CPU cycle allocation for SP vCPU to reach message loop\"" }, { "commit": "1209ea4679769070dd7bf7c316354ce840060378", "tree": "026fea5427fe5a749b88b201f0b988609420585f", "parents": [ "3e9115dc182c6240f9289912b6f528853b510e10", "7c193632dc959bb7070a667cdc1ad6171892cd35" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jan 28 17:32:05 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 28 17:32:05 2025 +0100" }, "message": "Merge \"feat(ff-a): add v1.2 fields to RXTX header\"" }, { "commit": "7c193632dc959bb7070a667cdc1ad6171892cd35", "tree": "026fea5427fe5a749b88b201f0b988609420585f", "parents": [ "3e9115dc182c6240f9289912b6f528853b510e10" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Jan 28 11:22:18 2025 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Jan 28 11:26:47 2025 +0000" }, "message": "feat(ff-a): add v1.2 fields to RXTX header\n\nAdd the new fields introduced in v1.2 to the partition message header.\nThis will fix the tests that were failing due to the `offset` being too small.\n\nChange-Id: I58ddd8f6897d0e46b7c7f754fde7ecddd012a0ca\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "6681b7a6fc142f8b1ba0f97d41d239fe6e874c37", "tree": "ce9e06d8cf11d20bfe42b02034bd2a7a2255f053", "parents": [ "3e9115dc182c6240f9289912b6f528853b510e10" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Nov 01 16:27:44 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jan 27 07:38:50 2025 -0600" }, "message": "fix: skip CPU cycle allocation for SP vCPU to reach message loop\n\nWith the support added in Hafnium SPMC for secondary CPU cold boot,\nsecondary execution contexts of SPs dont need a round of CPU cycles\nthrough ffa_run to reach the message loop.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ib02f51abb31d30329d43f0937ba30d721504bc53\n" }, { "commit": "cd46f276f845a4628982e85dfc38054fc94aa5c3", "tree": "de4c2033cf870b1646a0fda8fcae1520fdbad6ea", "parents": [ "4686bbfe1f0122f07aa65f2d9c11fca81557ec54" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Nov 25 11:18:34 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jan 13 13:34:53 2025 +0000" }, "message": "feat: specify the secure partition package for an SP\n\nSpecify the Transfer List format for the partitions:\n- cactus-secondary\n- cactus-tertiary\n- Ivy\n\nThe entrypoint offset changed when using TL as the package\nfor SPs.\n\nChange-Id: I044e3575861876ce108f0e65822d56d68bfdb427\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "3e9115dc182c6240f9289912b6f528853b510e10", "tree": "bb75b4c42e4b096554dacad9bc3b399284f04097", "parents": [ "4686bbfe1f0122f07aa65f2d9c11fca81557ec54", "5abab7674959cb2fa3211e5199ac3115e72e86dc" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jan 13 14:18:16 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 13 14:18:16 2025 +0100" }, "message": "Merge changes I62946a18,Ida808b9d,Ic71af8d0,I505a4a05\n\n* changes:\n test(realm): add support for RSI Planes ABI\n test(realm): add AUX RTT support for planes\n test(realm): allocate memory for multiple planes\n test(realm): add initial support for planes\n" }, { "commit": "5abab7674959cb2fa3211e5199ac3115e72e86dc", "tree": "86f2a0e558571dc8e5f616e31d1564f8fbf11d5a", "parents": [ "8f5dae9067e545618830abda9fc5f143c58e7c9f" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 04:57:53 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 10 16:39:05 2025 +0000" }, "message": "test(realm): add support for RSI Planes ABI\n\nAdd Planes RSI support.\nAdd helpers to setup initialize and enter planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I62946a185c47fe77a04f42751d0b0a467d41ceee\n" }, { "commit": "4686bbfe1f0122f07aa65f2d9c11fca81557ec54", "tree": "02bf7741ffc9dad822742b79fc90caa9839b9a7f", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c", "b24cc1347491fd4ac89212970eba80f3fae5438f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 09 13:57:14 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 09 13:57:14 2025 +0100" }, "message": "Merge changes from topic \"bk/smccc_feature\"\n\n* changes:\n fix(brbe): report BRBE support with later revisions\n test(SMCCC): test SMCCC_ARCH_FEATURE_AVAILABILITY\n refactor(SMCCC): use a macro to check for the SMCCC version\n feat: add register definitions needed for SMCCC_ARCH_FEATURE_AVAILABILITY\n" }, { "commit": "8f5dae9067e545618830abda9fc5f143c58e7c9f", "tree": "733dc1d8d0aeda4faae063a30dc7c46da1c1e96f", "parents": [ "31b2552f3cc950e1244377e9246a6c85467d59a0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 03:38:31 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 09 10:28:51 2025 +0000" }, "message": "test(realm): add AUX RTT support for planes\n\n- Add support for new RMI_RTT_AUX ABIs and helpers.\n- Create and destroy aux mappings for realm creation\n with multiple planes and multiple RTTs.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ida808b9d311e8a662587257e015b0f62c110ac3b\n" }, { "commit": "31b2552f3cc950e1244377e9246a6c85467d59a0", "tree": "2b2c7558cf3359fdff5b87b9c7c064d474d060b5", "parents": [ "1ea7a8612622a7f3baf14ef3bb94d59d898231b4" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 03:13:27 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 09 10:25:59 2025 +0000" }, "message": "test(realm): allocate memory for multiple planes\n\n- Update realm create helpers to allocate memory\n and copy multiple plane images.\n- Also allocate memory for multiple Aux RTTs.\n- Increase realm heap by 2 MB.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ic71af8d0b156ad60d8cb8c5bafe6f9b7df8280c7\n" }, { "commit": "1ea7a8612622a7f3baf14ef3bb94d59d898231b4", "tree": "2e0a208919dae9e7adfa2c7c95693bac3470fbca", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 02:36:40 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 09 09:52:07 2025 +0000" }, "message": "test(realm): add initial support for planes\n\n- Added changes to RMI feature register\n and RmiRealmParams for planes\n- Updated realm create helpers to support planes\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I505a4a05f222e2a28eed33bded3bae687fc29eec\n" }, { "commit": "b24cc1347491fd4ac89212970eba80f3fae5438f", "tree": "02bf7741ffc9dad822742b79fc90caa9839b9a7f", "parents": [ "7b7ca22f1b54632558663f5816d103105ce3aaec" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 28 10:35:35 2024 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "fix(brbe): report BRBE support with later revisions\n\nThere is BRBEv1p1 now, but the accessor reports the BRBE is not\nsupported altogether when that is present. The result is that the test\nis skipped. Fix the condition to return support with newer revisions\ntoo.\n\nChange-Id: Iab51b4016934d4b9eef125a6c4010ea419c99b81\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "7b7ca22f1b54632558663f5816d103105ce3aaec", "tree": "e3a9111c51ba449327eeeecbb638f03b5dab3cc6", "parents": [ "566f07da79dc559c405e79327be47740b7a66686" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 13:33:18 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "test(SMCCC): test SMCCC_ARCH_FEATURE_AVAILABILITY\n\nThis test calls the function with each valid argument and checks that\nevery bit is set if its relevant feature is present in the system. It\nalso fails the test if any set bit in the return value has not been\nchecked. This should serve as a reminder to update this test for every\nnew feature that is implemented.\n\nOnly feature that tfa supports are tested with the expectation that new\nones will be added in the future.\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I801326a49810bb76bfc3b9d06780d416dcc32a40\n" }, { "commit": "566f07da79dc559c405e79327be47740b7a66686", "tree": "02ce87e53805217055fd73771267ba2f8f9edac0", "parents": [ "4e282424143dbd73cd0248d470d03cccb9005f42" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 13:31:48 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "refactor(SMCCC): use a macro to check for the SMCCC version\n\nThis is similar to other macros that skip the test if a condition is failed.\n\nChange-Id: If8ff8b29473151edf1872636bce9ee0950851c42\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "4e282424143dbd73cd0248d470d03cccb9005f42", "tree": "b5da9ecc48fe84d374c9e04de6a0d3e2c7f8aa0d", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 14:34:13 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:16 2025 +0000" }, "message": "feat: add register definitions needed for SMCCC_ARCH_FEATURE_AVAILABILITY\n\nAlso slightly optimised some redundant feature functions\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I6dcc11060a2f3697a8aa41443e9cfc665b2b7c74\n" }, { "commit": "a4d7972176c2fdc3c66e6ba3347d24f65bac670c", "tree": "ca528cadd776c98afa91e1be5bd5b728b0c51b3c", "parents": [ "963872ed94fc063dc8597dc034ce7e45362e348f", "d1a7f4d2bd6b4867a71366b58b00759724ef99d1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Dec 20 10:03:31 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 20 10:03:31 2024 +0100" }, "message": "Merge \"feat: add tests to check SCTLR2, THE and D128 sysregs\"" }, { "commit": "d1a7f4d2bd6b4867a71366b58b00759724ef99d1", "tree": "7439900358c0026fe7c781e725e6ba0b1c3fd37b", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Tue Nov 26 12:50:47 2024 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 19 14:51:47 2024 +0000" }, "message": "feat: add tests to check SCTLR2, THE and D128 sysregs\n\nThis patch adds test cases for verifying that the system registers of\nFEAT_SCTLR2, FEAT_THE and FEAT_D128 (FEAT_SYSREG128) are working\ncorrectly by performing a series of reads and writes to the registers.\n\nChange-Id: I5c102daa358a7ec5d1801395bc875e9850e83939\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "963872ed94fc063dc8597dc034ce7e45362e348f", "tree": "4ac27884ec2a40c67d82cd00bc81675532521e19", "parents": [ "97925dae1fb8530102010a15f39aec568e75b9e9", "d8092a550b85c6369aabf96430c9b06cc8444298" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Dec 18 20:17:48 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 18 20:17:48 2024 +0100" }, "message": "Merge \"feat(mbedtls): update minimum version to latest MbedTLS v3.6.2\"" }, { "commit": "d8092a550b85c6369aabf96430c9b06cc8444298", "tree": "6303bdd1e607363980fa32b41205d1b71d3ed055", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Dec 17 09:14:50 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Dec 18 18:19:50 2024 +0200" }, "message": "feat(mbedtls): update minimum version to latest MbedTLS v3.6.2\n\nUse the latest MbedTLS version 3.6.2 as the minimum to stay in \nsync with TF-A.\n\nChange-Id: I4c70ec87805a99ba0cfaf2c23cfea51133d0daf7\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "97925dae1fb8530102010a15f39aec568e75b9e9", "tree": "c012e0e20c412bfb51f078c119f30017b7bca277", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38", "97dd9c3fe59af613c6dd7404a1f349abce3ec3d2" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Dec 18 14:08:37 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 18 14:08:37 2024 +0100" }, "message": "Merge \"fix: omit printing an error on mbedtls not cloned\"" }, { "commit": "97dd9c3fe59af613c6dd7404a1f349abce3ec3d2", "tree": "c012e0e20c412bfb51f078c119f30017b7bca277", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Dec 18 10:53:25 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Dec 18 11:00:21 2024 +0100" }, "message": "fix: omit printing an error on mbedtls not cloned\n\nUsing Makefile\u0027s wildcard statement in place of a shell find command to\nprevent the error message below when mbedtls submodule is not cloned:\n\n find: ‘ext/mbedtls/include’: No such file or directory\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I9677aa4e97485b597e00ba0bdf76967f9093afe9\n" }, { "commit": "5d10ae70d57bc836d417b7a7592ecc96a528bc38", "tree": "ebc140f0239edb16dfb4341f9d12ca33cd364cb2", "parents": [ "dc18ace1a36a4f684f1e4c7ef193a34c563d75c1", "1c06e7712d4fe6efe068f60ad8b177931dc346e8" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Dec 16 14:52:57 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Dec 16 14:52:57 2024 +0100" }, "message": "Merge \"fix(realm): rmi_realm_params structure is not zeroed upon realm creation\"" }, { "commit": "1c06e7712d4fe6efe068f60ad8b177931dc346e8", "tree": "ebc140f0239edb16dfb4341f9d12ca33cd364cb2", "parents": [ "dc18ace1a36a4f684f1e4c7ef193a34c563d75c1" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Dec 16 13:26:48 2024 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Dec 16 13:26:48 2024 +0000" }, "message": "fix(realm): rmi_realm_params structure is not zeroed upon realm creation\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I2513a6977625f98e7d81f9cb57ee3e724fcbff81\n" }, { "commit": "dc18ace1a36a4f684f1e4c7ef193a34c563d75c1", "tree": "49bb31a7dc6df8d5b09217a4e38f5e493ffa87d8", "parents": [ "a07460f4520b05d6f01624a857e6b6c0a6a41235", "1ab21e5e0f05680e5a30093fe6a7eff99fdcb150" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 12 22:42:25 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Dec 12 22:42:25 2024 +0100" }, "message": "Merge \"feat(fpmr): test FPMR register access\"" }, { "commit": "a07460f4520b05d6f01624a857e6b6c0a6a41235", "tree": "ae13a7c6fcfdd64db025b24b280d4127ac7df246", "parents": [ "d25c577499280db4b1923f924210b9590039ab0c", "425b45479fbe0b49d15ac1dfe8d8f1b532cd29e9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Dec 06 15:47:10 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 06 15:47:10 2024 +0100" }, "message": "Merge changes from topic \"od/fix-sri-handling\"\n\n* changes:\n fix(spm): handle ME in indirect msg tests\n fix(spm): omit enabling/disabling SRI physical interrupt\n fix(spm): fill TX buffer again after undelegate\n" }, { "commit": "425b45479fbe0b49d15ac1dfe8d8f1b532cd29e9", "tree": "ae13a7c6fcfdd64db025b24b280d4127ac7df246", "parents": [ "f93aef1e0ff8e8d11716c23c44f8cbc51060778a" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Nov 13 18:39:45 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 17:41:57 2024 +0100" }, "message": "fix(spm): handle ME in indirect msg tests\n\nFor the following tests involving FF-A indirect messaging:\ntest_ffa_indirect_message_sp_to_vm\ntest_ffa_indirect_message_sp_to_vm_rx_realm_fail\n\nSending an indirect message from the SP triggers the SRI NS interrupt\nwhile the SP runs and initiates a managed exit.\nBack in TFTF, add a handler for processing the SRI and resume the SP\nafter managed exit using the dedicated cactus command.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I95918fd78e9dec20470307d60c8dd31d6c5b5a7c\n" }, { "commit": "f93aef1e0ff8e8d11716c23c44f8cbc51060778a", "tree": "8dd46da9ae2a912839e164daeba4d01850f327fa", "parents": [ "6ab3fe91df8c0dd9d1589411d1ed168247ad8edf" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 15:41:34 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 16:17:27 2024 +0100" }, "message": "fix(spm): omit enabling/disabling SRI physical interrupt\n\nThe SPMC takes care of enabling the SRI physical SGI interrupt on all\ncores. Omit doing it from TFTF.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ie1a4bdc898213107959eaac912aae5c6058114f5\n" }, { "commit": "6ab3fe91df8c0dd9d1589411d1ed168247ad8edf", "tree": "48ee3ae83f90f8d2d8830b040baf3e3803e95322", "parents": [ "d25c577499280db4b1923f924210b9590039ab0c" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 11:46:28 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 14:23:07 2024 +0100" }, "message": "fix(spm): fill TX buffer again after undelegate\n\nSimilarly to the fix done in [1], the RME undelegate operation on TX\nbuffer scrubs its contents in test_ffa_memory_share_fragmented_tx_realm,\nso re-init the TX buffer again with the fragment after undelegate.\n\n[1] https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/30027\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I6a716d42f79474b8d884826a0a09eac01e487176\n" }, { "commit": "d25c577499280db4b1923f924210b9590039ab0c", "tree": "468fb7e0e6ff7d864f3483fe72c1c23d4edba18e", "parents": [ "67a3ffba147f4a5d996fa5e307fd59389925434e", "cc8543823e6104d67e74892cd6d84c52f3cc4a14" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 29 12:02:27 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 29 12:02:27 2024 +0100" }, "message": "Merge changes If007b517,I56a9f5c5\n\n* changes:\n feat(realm): call RMI_PDEV ABIs from host realm mgmt\n refactor(realm): define PCIe helpers\n" }, { "commit": "cc8543823e6104d67e74892cd6d84c52f3cc4a14", "tree": "468fb7e0e6ff7d864f3483fe72c1c23d4edba18e", "parents": [ "5929bfe75a40577efa77cf23a2fc4057ced92e7e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:29:13 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 18:10:28 2024 +0000" }, "message": "feat(realm): call RMI_PDEV ABIs from host realm mgmt\n\nInitial support to invoke RMI PDEV ABIs from host realm management. The\nPDEV management testcase host_test_rmi_pdev_calls does PDEV create, get\nstate, get aux count, communicate, set public key, stop, destroy calls.\nThese calls internally retrieve device certificate, extract public key,\nand establish a secure session with the PCIe device.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: If007b5170cbaa932c4f18a01a825a8dc0b752f26\n" }, { "commit": "5929bfe75a40577efa77cf23a2fc4057ced92e7e", "tree": "054341aebc883a57faab006f4d700d596c323203", "parents": [ "67a3ffba147f4a5d996fa5e307fd59389925434e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:28:00 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 18:10:28 2024 +0000" }, "message": "refactor(realm): define PCIe helpers\n\nThis patch refactors the existing PCIe and DOE\nhelpers to define generic helpers to make them\nreusable across more tests.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I56a9f5c59715c7916f3f737ed6d3af94b0e3679f\n" }, { "commit": "67a3ffba147f4a5d996fa5e307fd59389925434e", "tree": "d1330dfede15a22679f428e3aee6b66960038d99", "parents": [ "3e72cded39f20bebe6f22d31b4f9833f44b90128", "d49873af4a07659bbf8fd9c07119a7d85f9cda89" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 28 17:22:36 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 28 17:22:36 2024 +0100" }, "message": "Merge \"feat(neoverse_rd): add TFTF support for RD-V3 platform\"" }, { "commit": "3e72cded39f20bebe6f22d31b4f9833f44b90128", "tree": "dd9321d639bd4bc727e416fb15a6ebecf316fd96", "parents": [ "58a254ae181886efcf6e691789a67d5c145eecf4", "23788fa84220f873a21f8bca53d973e240ae8740" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 17:17:37 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 28 17:17:37 2024 +0100" }, "message": "Merge changes I0e386334,I744ef44e\n\n* changes:\n feat(lib): add mbedtls support\n feat(realm): add MbedTLS as submodule\n" }, { "commit": "23788fa84220f873a21f8bca53d973e240ae8740", "tree": "dd9321d639bd4bc727e416fb15a6ebecf316fd96", "parents": [ "c5f75b914824a6c3cb992596b44f1c2a116eb7d3" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 12:19:32 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 17:11:28 2024 +0200" }, "message": "feat(lib): add mbedtls support\n\nAdd support for compiling Mbed TLS from external source.\n\nThe Mbed TLS library is compiled from source pointed by MBEDTLS_DIR\nenvironment variable. Any TFTF test that includes mbedtls.mk will have\nsupport for mbedtls library. Note that by default the MBEDTLS_DIR will\npoint to the default submodule directory (ext/mbedtls).\n\nThis support is added for testing RMM capabilities related to\nDevice Assignment in RMM.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I0e386334078812e5ff5bdcffd4143732e0478b64\n" }, { "commit": "c5f75b914824a6c3cb992596b44f1c2a116eb7d3", "tree": "430308bdc5397e13e64366bbfefdde82c69bd47c", "parents": [ "58a254ae181886efcf6e691789a67d5c145eecf4" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 04:39:38 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:56:53 2024 +0000" }, "message": "feat(realm): add MbedTLS as submodule\n\nThis patch adds MbedTLS repository as a git submodule.\nThe version of MbedTLS added is v3.6.2.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I744ef44e61c85ade3d56920cfc1b8fd1a27bb045\n" }, { "commit": "d49873af4a07659bbf8fd9c07119a7d85f9cda89", "tree": "2b8e1f0c9e74cee68e382a53c12f085e6e76c2e6", "parents": [ "58a254ae181886efcf6e691789a67d5c145eecf4" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Thu Jul 25 13:45:13 2024 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Thu Nov 28 11:31:04 2024 +0000" }, "message": "feat(neoverse_rd): add TFTF support for RD-V3 platform\n\nAdd platform files to enable TFTF on RD-V3 platform.\n\nChange-Id: Icd6f512a01b1582e3251c8c0b242dc0999da0d15\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "58a254ae181886efcf6e691789a67d5c145eecf4", "tree": "5d5644927acc2f4a212ba18558c7ed57f3d1e07c", "parents": [ "ea43ac0daef913576cf214454cf81482d8cf109a", "2c2810f79e57e78d77899084b5439cbdd1aaa464" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 04:23:38 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 26 04:23:38 2024 +0100" }, "message": "Merge \"fix(realm): make PCIe tests default for testing\"" }, { "commit": "2c2810f79e57e78d77899084b5439cbdd1aaa464", "tree": "5d5644927acc2f4a212ba18558c7ed57f3d1e07c", "parents": [ "ea43ac0daef913576cf214454cf81482d8cf109a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 15 17:11:24 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 05:21:39 2024 +0200" }, "message": "fix(realm): make PCIe tests default for testing\n\nThis patch moves the PCIe DOE test to the default realm world\ntestsuite.\n\nAlso fixes some build issues and hardens the PCIe functions.\n\nNote that FVP_Base_RevC model needs to have the following\noptions enabled for the PCIe tests to work :\n\n -C pci.pcie_rc.ahci0.endpoint.doe_supported\u003d1\n -C pci.pcie_rc.ahci0.endpoint.ide_supported\u003d1\n\n\nChange-Id: Icfd6b68799b0bacb44299c6a3cf99a3c425f833d\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "ea43ac0daef913576cf214454cf81482d8cf109a", "tree": "92ec8ee102ec299ca25e55fac006d80139c28135", "parents": [ "0f744702ebd52d2efcf42db52613aee5b8991fd0", "ebce902b9f4088972070a10a3c63b168621b4588" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Nov 25 11:09:52 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 25 11:09:52 2024 +0100" }, "message": "Merge \"test(realm): add test for validating RTT calls\"" }, { "commit": "0f744702ebd52d2efcf42db52613aee5b8991fd0", "tree": "86b12de45737bdd4da789df65d5574eb7a47bdab", "parents": [ "6a113621a9efdc143e9270b1789046cd7d9cdfb1", "88ffad277a35f0dcecd19d167021b26d2c7bc790" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 21 18:17:36 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 21 18:17:36 2024 +0100" }, "message": "Merge changes from topic \"jpc/rmm-add-attestation-tests\"\n\n* changes:\n test(realm): add tests for realm attestation\n feat(smc): support SMC calls with no ret vals in x8\n" }, { "commit": "6a113621a9efdc143e9270b1789046cd7d9cdfb1", "tree": "99e0b5dc52529869eae94348826fc1a51c0b7b04", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa", "cf898bbaa402c3202641829558300c744dd0cd99" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Nov 20 23:26:34 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 20 23:26:34 2024 +0100" }, "message": "Merge \"docs(release): changelog for v2.12 release\"" }, { "commit": "88ffad277a35f0dcecd19d167021b26d2c7bc790", "tree": "bc1a7e0a794c8a79438eb9df86c5ed86757daf5e", "parents": [ "c79338af9a3e9cb24b90afd79491c85b7ef11d72" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri Oct 11 21:22:29 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Wed Nov 20 15:06:04 2024 -0600" }, "message": "test(realm): add tests for realm attestation\n\nWith this patch, TFTF adds two tests for realm attestation. One tests\nthe full process of retrieving the attestation token from the host. The\nsecond one triggers a failure by calling RSI_ATTEST_TOKEN_CONTINUE\nwithout calling RSI_ATTEST_TOKEN_INIT first.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I885402377af1f02ce7e90c80dbe1079fe4c1b178\n" }, { "commit": "cf898bbaa402c3202641829558300c744dd0cd99", "tree": "99e0b5dc52529869eae94348826fc1a51c0b7b04", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Nov 15 09:43:11 2024 +0000" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Nov 20 11:18:21 2024 -0600" }, "message": "docs(release): changelog for v2.12 release\n\nChange-Id: I5f4eb0ccff8dcd7e5cf3cd8c475057495e53c28f\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "1ab21e5e0f05680e5a30093fe6a7eff99fdcb150", "tree": "17c76bf9488a15d760977c0631fd35ef733554a1", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Nov 12 10:52:08 2024 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Nov 19 15:16:35 2024 -0600" }, "message": "feat(fpmr): test FPMR register access\n\nChange-Id: I326690564d01596fb4f4b449f4f314699ccfe3c4\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "c79338af9a3e9cb24b90afd79491c85b7ef11d72", "tree": "bcf79e2a50a9e49bdfbae09e71fd4176c717bc7d", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Oct 28 18:48:25 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Tue Nov 19 09:06:55 2024 -0600" }, "message": "feat(smc): support SMC calls with no ret vals in x8\n\nThe current implementation of the SMC library assumes that x8\ncontains the address of an smc_ret_values structure. Although\nthis can be convenient, it prevents from using registers x8-x17\nas arguments, since it assumes there is an address in x8.\n\nThis patch implements an alternative API for SMC calls, allowing\nthe use of registers x1-x17 as input arguments and the use of\nregisters x0-x17 as output arguments without assuming a pointer\nin x8.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I0016116b8d2ee4ef5aac9473f31e38434cda4943\n" }, { "commit": "b607317afc8c6ad5f37ac8873dfa8777c50b96aa", "tree": "ade1fb648af0b10a6080c9a8035962b7ef0176f3", "parents": [ "6abf05e7077e19281443e773012bc81e8e659786", "784c6d220ea2b62b20e58eb814ba379349ce1665" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Nov 19 15:50:14 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 19 15:50:14 2024 +0100" }, "message": "Merge changes from topic \"xlnx_plat_skip_query_pmf\"\n\n* changes:\n fix(zynqmp): update test skip list\n fix(versal-net): update test skip list\n fix(versal): update test skip list\n" }, { "commit": "6abf05e7077e19281443e773012bc81e8e659786", "tree": "13ad5ef729e1eda7fc70c89969dd774319806f25", "parents": [ "b2b581650c4af293b734a45430ba49bccd96d60d", "16059ac52d8f221c921e0766bc2b714ee52e06ed" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 12:55:00 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 19 12:55:00 2024 +0100" }, "message": "Merge \"fix: add sysreg define for ID_AA64MMFR3_EL1\"" }, { "commit": "16059ac52d8f221c921e0766bc2b714ee52e06ed", "tree": "13ad5ef729e1eda7fc70c89969dd774319806f25", "parents": [ "b2b581650c4af293b734a45430ba49bccd96d60d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 11:15:22 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 13:19:55 2024 +0200" }, "message": "fix: add sysreg define for ID_AA64MMFR3_EL1\n\nThe patch 7c78f7b4a removed the definition for ID_AA64MMFR3_EL1 sysreg.\nThis define is needed for older GCC (like GCC 11) to compile TFTF\nsuccessfully. This patch restores the define.\n\nChange-Id: I18f8e00830c8e72807b6f1613e9d9864f12669ba\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "b2b581650c4af293b734a45430ba49bccd96d60d", "tree": "ce322be37116651bf3ab1d681632c176f8105233", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade", "46d0228e2a1a17c57be8f5011f183ea28e6ba518" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 19 11:23:40 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 19 11:23:40 2024 +0100" }, "message": "Merge changes from topics \"FEAT_DoubleFault2\", \"mb/serr-fix\"\n\n* changes:\n fix(serror): use custom argument for incrementing elr_elx\n feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n" }, { "commit": "46d0228e2a1a17c57be8f5011f183ea28e6ba518", "tree": "ce322be37116651bf3ab1d681632c176f8105233", "parents": [ "7c78f7b4a74e58512ff6998f7a5438520e58c343" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Nov 18 16:58:37 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Nov 19 11:22:08 2024 +0100" }, "message": "fix(serror): use custom argument for incrementing elr_elx\n\nAdd a custom argument to increment the elr_elx after handling SError.\nIn some cases, to prevent re-triggering the instruction, ELR needs\nto be incremented by 4. In other cases, it may not be necessary.\n\nThis argument is passed to the handler, which then decides whether\nto increment elr_elx by setting the passed argument accordingly after\nhandling the SError.\n\nChange-Id: I404f3c5e24f894502a8d00c73649be0b2dd540fa\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "7c78f7b4a74e58512ff6998f7a5438520e58c343", "tree": "ea7bd3a6363d1bf5686e5cfbd2a92cabec7a3df6", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Oct 25 11:44:32 2024 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Nov 19 10:10:16 2024 +0000" }, "message": "feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n\nWhen FEAT_DoubleFault2 is supported, TF-RMM must take into\naccount bit SCTLR2_EL1.EASE in order to decide whether to inject\na SEA into the sync exception vector or into the serror one.\n\nThe test on this patch verifies that TF-RMM injects the SEA\nto the right vector depending on SCTLR2.EASE bit.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c976fecb04d123e3efb96c5973b1466e241097f\n" }, { "commit": "784c6d220ea2b62b20e58eb814ba379349ce1665", "tree": "56b6ce66cb9fd60b5d96f0680fc479e40f61e9c2", "parents": [ "746b32be41f26c3cb29031bb01ab0c3efd3d890b" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Nov 15 09:32:52 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Mon Nov 18 08:23:36 2024 +0000" }, "message": "fix(zynqmp): update test skip list\n\nTest cases \"Query Vendor-Specific Service\" and \"Probe PMF version\"\nare failing since PMF is not supported on AMD platform.\nTest cases will be skipped till non-availability of PMF support.\n\nChange-Id: I82c85838b2b10ccf2d044925b7b713a0edf5556a\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "ff2f1150099940a2767381df1701c9007eec8e68", "tree": "967bb3dde609bc228d80457c803adc7d65cbc641", "parents": [ "5a44078f017c581c9def5cfd697f0579fc6ff89c" ], "author": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Thu Jun 20 13:00:16 2024 +0200" }, "committer": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Fri Nov 15 09:06:21 2024 +0100" }, "message": "fix(test): compile error in test_irq_spurious_gicv2.c\n\nPrior to this patch with PLATFORM_CORE_COUNT defined to 32 test_irq_spurious_gicv2.c fails to compile with the following error:\ntftf/tests/runtime_services/trusted_os/tsp/test_irq_spurious_gicv2.c: In function ‘test_multicore_spurious_interrupt’:\ntftf/tests/runtime_services/trusted_os/tsp/test_irq_spurious_gicv2.c:26:37: error: left shift count \u003e\u003d width of type [-Werror\u003dshift-count-overflow]\n 26 | #define CPU_TARGET_FIELD ((1 \u003c\u003c PLATFORM_CORE_COUNT) - 1)\n | ^~\ntftf/tests/runtime_services/trusted_os/tsp/test_irq_spurious_gicv2.c:232:48: note: in expansion of macro ‘CPU_TARGET_FIELD’\n 232 | gicv2_set_itargetsr_value(TEST_SPI_ID, CPU_TARGET_FIELD);\n | ^~~~~~~~~~~~~~~~\n\nFix this by using 0xFF as the width of each field in GIC_ITARGETSR is 8\nbits.\n\nChange-Id: I310cf7ada7230051ba3cedf6752f26c80528b198\nSigned-off-by: Jens Wiklander \u003cjens.wiklander@linaro.org\u003e\n" }, { "commit": "5a44078f017c581c9def5cfd697f0579fc6ff89c", "tree": "4d63ddf377e00735bcbb1d5fdacc1885f8401377", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Tue Jun 25 12:36:20 2024 +0200" }, "committer": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Fri Nov 15 09:06:21 2024 +0100" }, "message": "feat(timer): support PPI timer interrupts\n\nAdd support for timers that use a PPI as timer interrupt. A new\nfunction, tftf_initialise_timer_secondary_core(), is added to initialize\nthe PPI on the secondary CPUs from tftf_warm_boot_main().\n\nChange-Id: Ia343ce10b0b51e72b9e520b1fab0ea7ba0a43f2c\nSigned-off-by: Jens Wiklander \u003cjens.wiklander@linaro.org\u003e\n" }, { "commit": "4c19b48e1d0aed1cfb94785c86544d2a58190ade", "tree": "94a32197863ac3dc2d6a050eb4321887fdf41ceb", "parents": [ "27f833a0817002e1ea9b88e11ba173357588afcc", "f675feb04d6583e80770a1cda48989a3f27e61fa" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Nov 14 17:25:42 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 14 17:25:42 2024 +0100" }, "message": "Merge \"fix(versal2): move timer clk offset definition to platform header\"" }, { "commit": "f675feb04d6583e80770a1cda48989a3f27e61fa", "tree": "94a32197863ac3dc2d6a050eb4321887fdf41ceb", "parents": [ "27f833a0817002e1ea9b88e11ba173357588afcc" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Wed Nov 13 11:37:30 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Thu Nov 14 09:09:57 2024 +0000" }, "message": "fix(versal2): move timer clk offset definition to platform header\n\nFor Versal2 platform TTC_CLK_SEL_OFFSET is defined in common timers source\nwhich is creating build conflict for other platform.\n\nMoving the definition for TTC_CLK_SEL_OFFSET to versal2 platform header.\n\nChange-Id: I1e2db4c591520be12e568d84da290b17d72bf897\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "27f833a0817002e1ea9b88e11ba173357588afcc", "tree": "37a9c57f2fed61dc7115b4a0104a62567d390834", "parents": [ "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f", "891856dd39671e0f996a5ac5c21e7444c24c49eb" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Nov 12 16:59:17 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 12 16:59:17 2024 +0100" }, "message": "Merge \"fix(timer): enable virtual timer in respective test\"" }, { "commit": "891856dd39671e0f996a5ac5c21e7444c24c49eb", "tree": "37a9c57f2fed61dc7115b4a0104a62567d390834", "parents": [ "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 12 14:02:46 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 12 15:14:31 2024 +0000" }, "message": "fix(timer): enable virtual timer in respective test\n\nThe virtual timer interrupt was enabled from main function.\nEnablement HVC is implementation defined to Hafnium SPMC.\n\nCactus SP is loaded on top of EL3 SPMC tests in spm-l3-boot-tests\ngroup, which failed due to enablement function.\n\nThis patch moves the code enabling code from cactus main\ninto the respective command handler to operate the architectural\ntimer.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Iee7b884003ca1e9b7fcee4e89b563970ffe753a0\n" }, { "commit": "ebce902b9f4088972070a10a3c63b168621b4588", "tree": "8491cfde6a9444c216a9bf4b4939966103f43919", "parents": [ "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Sep 23 14:36:47 2024 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Nov 12 11:19:14 2024 +0100" }, "message": "test(realm): add test for validating RTT calls\n\nadd test to validate RMI_RTT_CREATE and RMI_RTT_MAP_UNPROTECTED command\nfail when LPA2 is disabled and PA \u003e\u003d 48 bits\n\nChange-Id: I6281da6b68d78bc42c1c87e2572c63c4aae63cfd\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "746b32be41f26c3cb29031bb01ab0c3efd3d890b", "tree": "e94b5d241de2e796ae6a540c814ea9eb00072194", "parents": [ "ac24bb830b3b6da926c71aec40150688fd3c338d" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 05 06:18:51 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 12 03:23:10 2024 +0000" }, "message": "fix(versal-net): update test skip list\n\nTest cases \"Query Vendor-Specific Service\" and \"Probe PMF version\"\nare failing since PMF is not supported on AMD platform.\nTest cases will be skipped till non-availability of PMF support.\n\nChange-Id: I40fd7defea853d0a1aee5da79924d4ee5c15cfaa\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "ac24bb830b3b6da926c71aec40150688fd3c338d", "tree": "280ce1e731cbb573344a9a7dec1fa453d3abd38f", "parents": [ "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 05 06:18:39 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Nov 12 03:23:03 2024 +0000" }, "message": "fix(versal): update test skip list\n\nTest cases \"Query Vendor-Specific Service\" and \"Probe PMF version\"\nare failing since PMF is not supported on AMD platform.\nTest cases will be skipped till non-availability of PMF support.\n\nChange-Id: I560ee5b69244cee13003a71c8ecc5848a1b903e6\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f", "tree": "f8979bc2f589f87671ed5e50216364e64e1dc06d", "parents": [ "a7aa825f328ce0d844f134af8f0cd7468f811d07", "e9c18128b5234f1e76aa0147666d04de61bca93b" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Nov 11 18:48:06 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 11 18:48:06 2024 +0100" }, "message": "Merge \"test: arch timer in nwd is honored across world switch\"" }, { "commit": "a7aa825f328ce0d844f134af8f0cd7468f811d07", "tree": "4775918602e40087fcf0f9a9795009292b961972", "parents": [ "0d42dceeb1382652091f709d2d286773b46a4936", "e42561dbcd9d66d4de22d1b2bf48e124872b815c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Nov 11 16:03:08 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 11 16:03:08 2024 +0100" }, "message": "Merge \"fix: update definitions for sysregs on older toolchains\"" }, { "commit": "0d42dceeb1382652091f709d2d286773b46a4936", "tree": "2c2dc48110b1fbabc90a96a78483bd885868c5bb", "parents": [ "73d5bbd188aa33ad7ef4c28acbddaf2d8b9433a7", "11221142eac86235c7efdec6eb8ba195c14af8e8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Nov 11 14:36:53 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 11 14:36:53 2024 +0100" }, "message": "Merge changes Ibafc696c,I2d976951\n\n* changes:\n fix(build): add a dependency to the build directory\n fix(build): use a grouped target for the tests_list files\n" }, { "commit": "e42561dbcd9d66d4de22d1b2bf48e124872b815c", "tree": "eab01079c905b0f119a826ca02ecb8e65a642647", "parents": [ "73d5bbd188aa33ad7ef4c28acbddaf2d8b9433a7" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Nov 11 11:22:03 2024 +0100" }, "committer": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Nov 11 13:00:46 2024 +0100" }, "message": "fix: update definitions for sysregs on older toolchains\n\nThe patch 0db4a3cd added new sysreg access which older toolchains\ndo not support. This fix opts to use the renaming variant of the\nnecessary preprocessor macros for the registers used as part of\nthat patch, so that TFTF can compile with older toolchains.\n\nChange-Id: I1d4cdfc3f67a085af35a3b51477eda79e9e93db7\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "73d5bbd188aa33ad7ef4c28acbddaf2d8b9433a7", "tree": "b5d66c48a39a422a902364d694a41521c35de431", "parents": [ "8e65838b7baaf9a0c57582aa7deee11d78012931", "4b67210c4ae32e723fc5805f3b7e8c48fb8ec962" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Nov 08 18:41:30 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 08 18:41:30 2024 +0100" }, "message": "Merge changes from topic \"jc/context_mgmt_tests\"\n\n* changes:\n feat(cm): add test to validate EL2 regs during context switch\n feat(cm): add el2-ctx registers helper macros\n feat(cm): add tests to validate EL1 regs during context switch\n feat(cm): add el1-ctx register helper macros\n" }, { "commit": "4b67210c4ae32e723fc5805f3b7e8c48fb8ec962", "tree": "b5d66c48a39a422a902364d694a41521c35de431", "parents": [ "0db4a3cdde090a94721a8a598cbbbf857f7cf47f" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Sep 23 13:06:15 2024 +0200" }, "committer": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Fri Nov 08 17:48:28 2024 +0100" }, "message": "feat(cm): add test to validate EL2 regs during context switch\n\nVerify that EL2 system registers are preserved when switching\nfrom Normal world to Secure world and vice versa. Do this by\nmodifying the live EL2 register state and dumping it to memory,\nthen performing an FF-A Cactus call and checking whether the\nstate matches the previously saved context.\n\nChange-Id: I0537b4d671c72c0a2fd29ac7e218bf69e1c66001\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "0db4a3cdde090a94721a8a598cbbbf857f7cf47f", "tree": "30581ed1d668fe4be2075f5ce034dedc1e3ee5e3", "parents": [ "86e5e5d500a839920edcf71783f31b7e4fc20c42" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Sep 23 12:52:15 2024 +0200" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 16:52:44 2024 +0000" }, "message": "feat(cm): add el2-ctx registers helper macros\n\nThis patch adds the necessary definitions for the registers\nand helpers that are used in the EL2 context switch test.\n\nChange-Id: Ie846f9341d600ae8fb7a46a9655a8f8ee62d84b0\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" } ], "next": "86e5e5d500a839920edcf71783f31b7e4fc20c42" }