)]}' { "log": [ { "commit": "699cd4feef98deb1e1d3bc95adc42a16da40052d", "tree": "dc08fba188c5d63d40f30d5eb382c8d0e680a2ad", "parents": [ "8ce3053050bc37f5cfccadefd575a597ac86dd95" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Sep 27 16:46:54 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(rmm): add psci api to realms\n\nadd wrappers for PSCI APIs\nCPU_ON\nCPU_OFF\nPSCI_AFFINITY_INFO\nPSCI_FEATURES\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ice7bc03d052a0726163c7a31a32f59688e7f516b\n" }, { "commit": "8ce3053050bc37f5cfccadefd575a597ac86dd95", "tree": "bd9c9d8e6eeba40a81702f88e8cb3bcbb44b9abf", "parents": [ "550e3e88891507cd514fbd8f27d6ba6b8c5a3162" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 16 15:58:38 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(realm): add host call to flush realm prints\n\nadd new host call to push out realm print buffer\nbuffer is flushed after every print statement\n\nChange-Id: I6efa92a7c75ab7df4615a432802426de39d0032c\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "550e3e88891507cd514fbd8f27d6ba6b8c5a3162", "tree": "81485909f1376913447c3480d640f9717bb61de0", "parents": [ "cdf525212326f8b453f22122dddc9d8bf0725981" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Aug 16 13:20:11 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(rmm): add support for multiple rec and cpu\n\nChanges to support creating and\nexecuting multiple rec on multiple cpus.\nAdded per REC shared buffer between Host and Rec.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ib6dbd814ee9f68df4a53f9cfdc8b7f9c905c35fe\n" }, { "commit": "cdf525212326f8b453f22122dddc9d8bf0725981", "tree": "cb2921b3cfa538802547572d0e8ea360bc0eb309", "parents": [ "9b2f7db4f52d6f144641761b2d2b01644b2b6684", "9e267a0f899d699cb840572eb8fc12936ac49d03" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 20 18:49:36 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 20 18:49:36 2023 +0200" }, "message": "Merge \"test: exercise secure espi interrupt handling\"" }, { "commit": "9b2f7db4f52d6f144641761b2d2b01644b2b6684", "tree": "3c3ba03b6f61ce41caebeba94bae5c81427bb5df", "parents": [ "6f74a663f0b2fa1731640d7e74bfb45347bb260e", "04fc4f2f642b0edad8f1a0fa61d132e9cf35e370" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Oct 16 20:07:15 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 16 20:07:15 2023 +0200" }, "message": "Merge \"test(spm): clear memory flag with two constituents\"" }, { "commit": "6f74a663f0b2fa1731640d7e74bfb45347bb260e", "tree": "bf07329f33a6b39d1fc04ec2964370df9dd7cca0", "parents": [ "89a46c094f9b392f146f0d41e6f1e34fd9d0a925", "dbd5ac26d8c10ec32a546b9d4f6c96b20b62091d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Oct 16 20:05:02 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 16 20:05:02 2023 +0200" }, "message": "Merge changes from topic \"ja/ffa_memory_sharing_rme\"\n\n* changes:\n fix(memory share): reclaim and check memory\n test: normal world can\u0027t share root memory\n feat(cactus): use security state attribute\n feat(ff-a): define memory security state attribute\n" }, { "commit": "89a46c094f9b392f146f0d41e6f1e34fd9d0a925", "tree": "5d57bc467fee1ad54c3960d1e2b43b035dd665a6", "parents": [ "2f13adbc1ac240bdee4c901cbd0e09119f17fce4", "fe69a8c4846c20c06efe945c2c6b1f9e893347fa" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Oct 16 18:36:56 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 16 18:36:56 2023 +0200" }, "message": "Merge \"fix(AArch64): Fix issue in processing dynamic relocations\"" }, { "commit": "fe69a8c4846c20c06efe945c2c6b1f9e893347fa", "tree": "5d57bc467fee1ad54c3960d1e2b43b035dd665a6", "parents": [ "2f13adbc1ac240bdee4c901cbd0e09119f17fce4" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Aug 21 11:49:32 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 16 18:36:39 2023 +0200" }, "message": "fix(AArch64): Fix issue in processing dynamic relocations\n\nFixes issue in processing dynamic relocations, when\nrelocation entries not matching R_AARCH64_RELATIVE type are found.\nLinker might generate entries of relocation type R_AARCH64_NONE\n(code 0), which should be ignored to make the code boot.\nSimilar fix done in TF-A (db9736e3d86d7098f9785a9db834746a8b2ed335)\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ibc769efa322618f59c05a6b1596555fc1b00b57b\n" }, { "commit": "04fc4f2f642b0edad8f1a0fa61d132e9cf35e370", "tree": "e2b57b929eef7a2f3e195bc744a83c1fd1ce24c9", "parents": [ "dbd5ac26d8c10ec32a546b9d4f6c96b20b62091d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 11 17:04:52 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Oct 16 15:03:20 2023 +0100" }, "message": "test(spm): clear memory flag with two constituents\n\nAdd another constituent to the test using the clear memory flags\non retrieve request.\nThis is relevant as there was a bug in the SPM implemention\nthat was not clearing correctly multiple constituents in a fragment.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I17cf3f32b111771ca913e84e3e10e5b6f669933e\n" }, { "commit": "dbd5ac26d8c10ec32a546b9d4f6c96b20b62091d", "tree": "5bf81cbf117fb9f66a5ce386ef69412f5a6068b1", "parents": [ "2e58e73b961f336099e521a8ec160b851b26b437" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 19:47:24 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Oct 16 15:01:03 2023 +0100" }, "message": "fix(memory share): reclaim and check memory\n\nIf the test relates with FFA_MEM_DONATE do not reclaim or check memory.\nThe memory is owned by the receiver, and is not accessible to sender.\n\nIf operation is lend/share, TFTF should reclaim memory contents first,\nand then validate that the SP\u0027s access to memory. This is to avoid\nfault on lend, as lender doesn\u0027t have access to memory until after\nthe reclaim.\n\nChange-Id: I548b5cf2ac5c2774123f438a02565723470b4d85\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "9e267a0f899d699cb840572eb8fc12936ac49d03", "tree": "869431e9ca81b7a20027416704453766d7c10f56", "parents": [ "2f13adbc1ac240bdee4c901cbd0e09119f17fce4" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 11 21:25:26 2022 -0700" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 13 12:04:15 2023 -0500" }, "message": "test: exercise secure espi interrupt handling\n\nHafnium/SPMC added support for enabling interrupts in the extended SPI\nrange. With the help of an SiP SMC call that can pend an interrupt,\nthis patch adds a test to trigger an espi interrupt when cactus is\nrunning and ensure it is handled.\n\nAdditionally, a dummy device region node representing a fake\nperipheral has been added to the Cactus SP manifest. It is used to\nspecify properties of the interrupt in the extended SPI range used\nfor the above test scenario.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ief932c40e3abd33d619f2b144e61cae449147b27\n" }, { "commit": "2e58e73b961f336099e521a8ec160b851b26b437", "tree": "7b075e9baaa4d4f827f88b9723f0729d32c1e881", "parents": [ "5e07e7eb18d5b21e1e356b1d040fc9008b8ad221" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 11:57:48 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:10:50 2023 +0100" }, "message": "test: normal world can\u0027t share root memory\n\nIn [1] the invalid access test was removed from the respective\ntests xml file, as it was leveraging a security vulnerability in\nour SPM implementation.\n\nAs part of the same patchstack, we have harnessed and limited the\nmemory that an SP can use via manifest, or memory sharing operations.\nThis patch reestablishes the invalid access that was discarded,\nthis time however only validating that the memory sharing of root\nmemory fails, which should be indicative that the SP can\u0027t access it.\n\nAlso set missing dependency to the source file: spm_test_helpers.c\nto make file tests-invalid-access.mk.\n\nFuture patches will include tests to the GPC.\n\n[1] https://review.trustedfirmware.org/q/topic:%22ja%252Fmem_region_fix%22+(status:open%20OR%20status:merged)\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I6ee21586a2e94810fb4656054b26b2a51c97a544\n" }, { "commit": "2f13adbc1ac240bdee4c901cbd0e09119f17fce4", "tree": "96e756d3146e35c2e90045989174f2052b84f139", "parents": [ "7043e2a82e3b271552744b46fd180c4bc011ccc3", "568cc46ee1584eaf5f388d17bcc43597651060ae" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 13 15:10:41 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 13 15:10:41 2023 +0200" }, "message": "Merge \"fix(spm_common): fix comparison that is always true\"" }, { "commit": "5e07e7eb18d5b21e1e356b1d040fc9008b8ad221", "tree": "2340fad9f8c4ec95fc92dd649b1896f70241ffba", "parents": [ "d13d760570e9d0f640e8bd83bcfbc21240949156" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 14:36:09 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:08:49 2023 +0100" }, "message": "feat(cactus): use security state attribute\n\nCactus uses security attribute from memory transaction\ndescriptor in the shared memory related tests.\n\nChange-Id: I7c4f3ef2c72e36236d23e5a061e27a2ea60fa2d6\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "d13d760570e9d0f640e8bd83bcfbc21240949156", "tree": "a0b70191908599e7242033b0629d97c14c6ce5b6", "parents": [ "7043e2a82e3b271552744b46fd180c4bc011ccc3" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 14:19:03 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:08:49 2023 +0100" }, "message": "feat(ff-a): define memory security state attribute\n\nFF-A v1.1rel0 defines the security state attribute for the\nmemory transaction descriptor. Add respective definition\nto ffa_helpers.h.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Iefb510f5272587bc9faa96731af0159e2379576b\n" }, { "commit": "7043e2a82e3b271552744b46fd180c4bc011ccc3", "tree": "c819ffa35f4e270d06bf7727c1780688b7f125e9", "parents": [ "99243ddd194fb1ee4022a941518d6ddf672692a1", "c28a8dbfb2cda1e4f7f54b1aae51b77990b79ad8" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Oct 13 01:21:34 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 13 01:21:34 2023 +0200" }, "message": "Merge \"Add test for Errata management firmware interface.\"" }, { "commit": "568cc46ee1584eaf5f388d17bcc43597651060ae", "tree": "729ccdba8f947b05fa5057e392df0ea80d21c365", "parents": [ "99243ddd194fb1ee4022a941518d6ddf672692a1" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Oct 12 16:39:30 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Oct 12 16:39:30 2023 +0100" }, "message": "fix(spm_common): fix comparison that is always true\n\nThis comparison always evaluates to true. I assume it was a typo when\ncopy and pasting a line.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I90d8a33b3a9b4ac0aabc9cafa11b5b705ef1aab0\n" }, { "commit": "99243ddd194fb1ee4022a941518d6ddf672692a1", "tree": "512fb996d19060098a9a52772dc70f217192dd02", "parents": [ "c6f3fe090bd72738101d20046cf310ac84bdfbe4", "6e5c99643b199e064f1e8090d963671965ced1d7" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Oct 11 11:03:27 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 11 11:03:27 2023 +0200" }, "message": "Merge changes Iead2dc62,Icf326cf4\n\n* changes:\n fix(rme): append realm.bin at end of tftf.bin\n test(xlat) : fix testcase xlat v2: Stress test\n" }, { "commit": "c28a8dbfb2cda1e4f7f54b1aae51b77990b79ad8", "tree": "a4a7970ae95f9c5ed7e0ee170fcb4303add53337", "parents": [ "c6f3fe090bd72738101d20046cf310ac84bdfbe4" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Sep 28 23:21:54 2023 -0500" }, "committer": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Tue Oct 10 09:59:17 2023 -0500" }, "message": "Add test for Errata management firmware interface.\n\nAdd test to check the em_cpu_erratum_features for\na multiprocessor system.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: Id09fdb837f44fff63c5ca4249accbca046cc06ef\n" }, { "commit": "6e5c99643b199e064f1e8090d963671965ced1d7", "tree": "c5079b4d7de61ed810e5241021b5005d35990ba7", "parents": [ "92b99ee435ebafa5e503b19dce753079ad35218d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Oct 06 16:38:13 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 10 14:31:18 2023 +0100" }, "message": "fix(rme): append realm.bin at end of tftf.bin\n\nCurrently realm.bin is appended to tftf.bin at offset of 10 MB.\nThis patch removes this dependency by reserving empty sections\nfor realm image and dependencies, in tftf binary after\nall loadable sections (end of binary),\nand append realm.bin at end of tftf.bin later in build process.\n\nThe patch removes the need for TFTF to map memory corresponding\nto Realm payload dynamically at runtime.\n\nChange-Id: Iead2dc62ff2965cf7bb03e61c93e76df218da973\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "92b99ee435ebafa5e503b19dce753079ad35218d", "tree": "e55b21ab9abcabcd02b80883a1191a141d0a4ce9", "parents": [ "afffe3a45076fa46a8cd73b0923e06874c8ab135" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 10 14:23:48 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 10 14:30:53 2023 +0100" }, "message": "test(xlat) : fix testcase xlat v2: Stress test\n\nTestcase fails when test tries to unmap memory region\nwith size\u003d0, mapping region with size\u003d0 was success,\nadded workaround to skip mapping if size\u003d0,\nWill need to be fixed in xlat library later.\n\nChange-Id: Icf326cf4889b833e1bd9e064eeeb1f309ae147c6\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "c6f3fe090bd72738101d20046cf310ac84bdfbe4", "tree": "f42a7bc9eaa25c2a9bc697fbfd159b9509b42f13", "parents": [ "fb790e66d7304441434d700987f89c9a07ca8444", "226f4a742e8c0232a34baefac2a7946ae33d4c83" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Oct 09 15:19:12 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 09 15:19:12 2023 +0200" }, "message": "Merge \"docs: update toolchain requirements documentation\"" }, { "commit": "226f4a742e8c0232a34baefac2a7946ae33d4c83", "tree": "f42a7bc9eaa25c2a9bc697fbfd159b9509b42f13", "parents": [ "fb790e66d7304441434d700987f89c9a07ca8444" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Sep 07 11:23:46 2023 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 04 17:35:01 2023 +0100" }, "message": "docs: update toolchain requirements documentation\n\nTF-A tests have been verified with the latest toolchain verison\n12.3.Rel1. Henceforth the requirements are updated.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I4c4c996862f0ca11805002128097c3d1c91d0809\n" }, { "commit": "fb790e66d7304441434d700987f89c9a07ca8444", "tree": "d751b1c0856b93b8e7730c825c614c64b444bad4", "parents": [ "6d8721db1753e0b9fc4252308186d5eb152252a8", "afffe3a45076fa46a8cd73b0923e06874c8ab135" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Oct 03 22:01:07 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 03 22:01:07 2023 +0200" }, "message": "Merge \"fix(spm): instruction permissions on memory sharing\"" }, { "commit": "afffe3a45076fa46a8cd73b0923e06874c8ab135", "tree": "d751b1c0856b93b8e7730c825c614c64b444bad4", "parents": [ "6d8721db1753e0b9fc4252308186d5eb152252a8" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Sep 22 17:14:52 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Sep 28 15:15:38 2023 +0100" }, "message": "fix(spm): instruction permissions on memory sharing\n\n- FFA_MEM_SHARE the instruction access to be used shall be NX,\nhowever both sender and the borrower should leave it not specified.\n- FFA_MEM_LEND/FFA_MEM_DONATE the lender must specify the instruction\npermissions it wishes to receive on the retrieve request.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I0c6e49c30cbbca513644b592695f853bbdf1994b\n" }, { "commit": "6d8721db1753e0b9fc4252308186d5eb152252a8", "tree": "4464d81a42505c45e15b29820533bbf2ea0f894a", "parents": [ "e3c73d226e7a0edafdc49f4be9f5621f5d286454", "30b8bc2aadb82281da999c7264f399d2b7775c42" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Sep 19 14:49:16 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 19 14:49:16 2023 +0200" }, "message": "Merge changes from topic \"xlnx_versal_net_intro\"\n\n* changes:\n docs(versal-net): add Versal NET documentation\n chore(xilinx): reorganize timer code into common path\n feat(versal-net): introduce platform support\n" }, { "commit": "e3c73d226e7a0edafdc49f4be9f5621f5d286454", "tree": "040deae47b58fde8636d6e6b2e0d350eaaa8545f", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41", "4550b49db8ddf98e4445fdd121d3e2bed466b034" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Sep 14 12:46:54 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 14 12:46:54 2023 +0200" }, "message": "Merge changes from topic \"eac2\"\n\n* changes:\n fix(rme): remove RIPAS_UNDEFINED definition\n feat(rme): use RIPAS/HIPAS EAC 2 definitions\n feat(rme): support for PMU as per RMM Specification 1.0-eac2\n feat(rme): add Realm SVE tests for EAC1\n feat(rme): modify API of RMI_RTT_*_RIPAS\n feat(rme): changes in handling RMI_RTT_UNMAP_UNPROTECTED\n feat(rme): update API of data/rtt functions\n feat(rme): remove RMI_VALID_NS status\n feat(rme): remove RMI_ERROR_IN_USE error code\n feat(rme):set size of RsiHostCall.gprs[] to 31\n feat(rme): pass RD pointer in arg0 register X1\n feat(rmm): modify rmi_realm_params structure\n" }, { "commit": "4550b49db8ddf98e4445fdd121d3e2bed466b034", "tree": "040deae47b58fde8636d6e6b2e0d350eaaa8545f", "parents": [ "35b0fa999146f9b1fe12abb237f9eecec42030c8" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Jul 14 12:07:56 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:50:15 2023 +0100" }, "message": "fix(rme): remove RIPAS_UNDEFINED definition\n\nThis patch removes RIPAS_UNDEFINED definition\nand matches RMM-TF patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21987\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I26d6c5e6f7c1053d1b2a7688118e6175985be029\n" }, { "commit": "35b0fa999146f9b1fe12abb237f9eecec42030c8", "tree": "39051ad40d5b1f3415349f9c8a5998c7525380e9", "parents": [ "4067f8610d0d9e89bac0499f09bcbd89d904ff36" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Jul 04 16:24:14 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:50:00 2023 +0100" }, "message": "feat(rme): use RIPAS/HIPAS EAC 2 definitions\n\nThis patch:\n- Modifies HIPAS/RIPAS definitions\n as per RMM Specification 1.0-eac2. It matches\n the changes introdiced by TF-A RMM code patch\n https://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21822\n- Return value of host_realm_destroy_undelegate_range()\n changed from void to u_register_t to report errors in\n the code flow.\n- In \u0027struct rtt_entry\u0027 types of \u0027state\u0027 and \u0027ripas\u0027 fields\n changed from \u0027unsigned int\u0027 to \u0027u_register_t\u0027 to match\n the size of values returned by RMI_RTT_READ_ENTRY command.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ied80fb6e1cd4b2da392514ace33201ffd9fc1da9\n" }, { "commit": "4067f8610d0d9e89bac0499f09bcbd89d904ff36", "tree": "e8f75c7f51dbd6d4237c327a63641df9920b5eaa", "parents": [ "f81345ce2cd13d59cb6efa5847ec02baf54cd489" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Jun 12 12:22:37 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:49:49 2023 +0100" }, "message": "feat(rme): support for PMU as per RMM Specification 1.0-eac2\n\nThis patch introduces PMU changes as per RMM\nSpecification 1.0-eac2:\n- pmu_ovf, pmu_intr_en and pmu_cntr_en fields in RmiRecExit\nare replaced with a synthetic single-bit field pmu_ovf_status\nwhich reports the level of the virtual PMU input to the GIC.\nThis field also includes the state of PMU Enable bit PMCR_EL0.E.\nThese changes match RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21434\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I4135c62927e8156931af9a43a665a19d0e90b342\n" }, { "commit": "f81345ce2cd13d59cb6efa5847ec02baf54cd489", "tree": "ca115e7029fc8f338a96f41ce044583aafa3bc2f", "parents": [ "cd04e41b418decee80a03d25eb7598e7a6b8da95" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 07 17:30:10 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:49:37 2023 +0100" }, "message": "feat(rme): add Realm SVE tests for EAC1\n\nThis patch adds SVE tests for RMM EAC1.\nThe \u0027feature_flag\u0027 parameter passed to\n\u0027host_create_realm_payload()\u0027 function is modified\nto contain \u0027sve_vl\u0027, \u0027num_bps\u0027, \u0027num_wps\u0027 and\n\u0027pmu_num_ctrs entries\u0027. This allows to pass values\nwhich can exceed these fields in feature_register_0\nfor testing. It makes possible to pass\n\u0027Create SVE Realm with invalid VL\u0027 which was\nskipped originally, when SVE was configured with\nthe maximum supported vector length value.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Icd5e57c1bb0cb8dee27b7ace5643aec597e036c1\n" }, { "commit": "cd04e41b418decee80a03d25eb7598e7a6b8da95", "tree": "57050d8f27e3eba6f4a3e5483f6ae0ee2013f630", "parents": [ "ef46c0460838d515f906f3a05aff313729596a51" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Apr 25 14:14:47 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:47:30 2023 +0100" }, "message": "feat(rme): modify API of RMI_RTT_*_RIPAS\n\nThis patch modifies API of RMI_RTT_INIT_RIPAS\nand RMI_RTT_SET_RIPAS commands\u0027 handlers\nas per RMM Specification 1.0-eac1.\nIt matches RMM patches\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20710\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20715\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Id594ca751a1c9ce18607cc8e17bef0bc6214d3ad\n" }, { "commit": "ef46c0460838d515f906f3a05aff313729596a51", "tree": "f02ba79f053da0a5f8f1bdbbcc0aa8ef27ae9842", "parents": [ "1e44db50fb7d1f04c072865e879e7cd5b44a02b8" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Apr 24 12:38:19 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:46:18 2023 +0100" }, "message": "feat(rme): changes in handling RMI_RTT_UNMAP_UNPROTECTED\n\nMake changes in handling RMI_RTT_UNMAP_UNPROTECTED\ncommand as per RMM Specification 1.0-eac1, which now returns\nthe top IPA of non-live RTT entries.\nThis patch matches RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20685\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I5b640db01784c7f9fbd4835d2f4187246443d967\n" }, { "commit": "1e44db50fb7d1f04c072865e879e7cd5b44a02b8", "tree": "456759fe83f4c0f99e90697dc3af29a52a4576ee", "parents": [ "81025b4c9789e0721db8efcacb7632946d2d108c" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Apr 19 17:26:51 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:45:23 2023 +0100" }, "message": "feat(rme): update API of data/rtt functions\n\nThis patch modifies API of host functions calling\nRMI_DATA_DESTROY, RMI_RTT_DESTROY and RMI_RTT_FOLD\ncommands according to RMM Specification 1.0-eac1.\nIt matches changes in RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20604\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I4410ea1cdbc093359b22a0a9495167efbe443c85\n" }, { "commit": "81025b4c9789e0721db8efcacb7632946d2d108c", "tree": "3f27881f023ff485cd6c90d81741565aad4fad86", "parents": [ "ac174ab64b45ee0d943c1e9c60edae5a0e294c77" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Apr 18 11:55:04 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:43:33 2023 +0100" }, "message": "feat(rme): remove RMI_VALID_NS status\n\nThis patch removes RMI_VALID_NS s2tte status as per\nRMM Specification 1.0-eac1, it matches RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20581\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Idcf4f421ec8d4d89d441986f50694c82877b3755\n" }, { "commit": "ac174ab64b45ee0d943c1e9c60edae5a0e294c77", "tree": "f4f637dfcea9bf6c14cfb9de626a4abef8f85963", "parents": [ "3d3dea2c3712b9b3f6b69b1690a6c73aeefc9a3e" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 16:35:22 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:43:21 2023 +0100" }, "message": "feat(rme): remove RMI_ERROR_IN_USE error code\n\nThis patch removes RMI_ERROR_IN_USE error code,\nas per RMM Specification 1.0-eac1, no functional\nmodifications are made.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ia911f9ba07b69d384bbd910f4b4dd3b68646c98a\n" }, { "commit": "3d3dea2c3712b9b3f6b69b1690a6c73aeefc9a3e", "tree": "e94fa3ce32d2f1f956059797fee04ee9a51cb095", "parents": [ "44927c3293c656b878ef1c93e1c8cc4dc92944af" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 15:36:27 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:42:51 2023 +0100" }, "message": "feat(rme):set size of RsiHostCall.gprs[] to 31\n\nThis patch sets the size of gprs[] array in RsiHostCall\nstructure to 31, as per RMM Specification 1.0-eac1.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I81417009b34fca435dd070c94d8e064b8f8bfd9b\n" }, { "commit": "44927c3293c656b878ef1c93e1c8cc4dc92944af", "tree": "1bc325c1ab0b86418f58b3c5159a66066709e719", "parents": [ "b69eae0e22dde3487cc0edcf0c8d2e092f54cf13" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 15:17:13 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Sep 12 16:55:14 2023 +0100" }, "message": "feat(rme): pass RD pointer in arg0 register X1\n\nThis patch makes changes according to RMM Specification\n1.0-eac1 for passing RD pointer in arg0 for RMI_DATA_CREATE,\nRMI_DATA_CREATE_UNKNOWN, RMI_REC_CREATE and RMI_RTT_CREATE\ncommands.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ia19baaf59209b2de06d63cd392c53e3ee19e3ec9\n" }, { "commit": "b69eae0e22dde3487cc0edcf0c8d2e092f54cf13", "tree": "19a9dc33bef7c68b8de1efe361bbd1f7b30434ef", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 10:27:58 2023 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Sep 08 12:24:42 2023 +0200" }, "message": "feat(rmm): modify rmi_realm_params structure\n\nThis patch modifies rmi_realm_params structure\naccording to definition of RmiRealmParams in\nRMM Specification 1.0-eac1.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I63c3097290004de90cd2222b24419aef517d9b49\n" }, { "commit": "30b8bc2aadb82281da999c7264f399d2b7775c42", "tree": "d8204dc54938f125c9510cd79c8f5ff7a62e2972", "parents": [ "1d8f2222855d4bf5c6dac48c43d66560324a04b0" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Aug 25 13:08:01 2023 +0530" }, "committer": { "name": "Michal Šimek", "email": "monstr@monstr.eu", "time": "Fri Sep 08 08:13:10 2023 +0100" }, "message": "docs(versal-net): add Versal NET documentation\n\nAdd information about Versal NET platform for TF-A Tests and provide\nthe build commands.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: If136b0d5d1f8cab12089243750096b18097c6444\n" }, { "commit": "1d8f2222855d4bf5c6dac48c43d66560324a04b0", "tree": "eab8162b1127b3dd6caee080a2808e86dcc0d4a9", "parents": [ "56f41cda007f73b997b687498b7f09fc72d262c6" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Aug 25 12:02:33 2023 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Tue Sep 05 10:29:01 2023 +0530" }, "message": "chore(xilinx): reorganize timer code into common path\n\nReorganized timer code into common folder, updated paths in\nplatform.mk and Versal/Versal NET ttc timer irq in platform_def.h for\nXilinx project.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I504727f55099decf07a208fc95254597e6e24902\n" }, { "commit": "56f41cda007f73b997b687498b7f09fc72d262c6", "tree": "7fe3036ca8fc2943663ed1d5f7389804d28f119c", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Fri Aug 25 11:59:30 2023 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Mon Sep 04 12:01:34 2023 +0530" }, "message": "feat(versal-net): introduce platform support\n\nIntroduce platform support for AMD-Xilinx Versal NET, an adaptive\ncompute acceleration platform (ACAP). The Versal NET is designed to\noffer a wide range of compute, acceleration, and connectivity\noptions, including high-speed networking interfaces.\n\n- pl011 is used for console.\n- TTC is used for Timers.\n- NVM is not supported.\n\nFor Versal devices with 1 cluster and 2 cores, the SCNTR and SCNTRS\nregisters are not accessible from NS EL1, so we are using TTC timers\ninstead.\n\nFor Versal NET devices with 4 clusters and 4 cores per cluster, the\nSCNTR and SCNTRS registers are not accessible from NS EL1, so we\nare using TTC timers instead.\n\nsummary:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 128\nTests Passed : 34\nTests Failed : 7\nTests Crashed : 0\nTotal tests : 169\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nNOTICE: Exiting tests.\n\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I80e76d9f898f5ebca91a403ff802857ea70d7868\n" }, { "commit": "8f6d559b99acc7bb347d3f214c0812e562477a41", "tree": "e47b85a68d09cea2d4b9d29998c2893141ece874", "parents": [ "c68ba0dec2989735fa24a8ed4efcf9cd76af2b05", "507ed939b32d26244412af3f6253a7adcc22420c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Aug 30 16:19:35 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 30 16:19:35 2023 +0200" }, "message": "Merge changes from topic \"jpc/el3-initialize-hfg-el2-regs\"\n\n* changes:\n refactor(fgt): modify FEAT_FGT test to check for init values\n feat(cpufeat): add feat detection helpers\n" }, { "commit": "507ed939b32d26244412af3f6253a7adcc22420c", "tree": "e47b85a68d09cea2d4b9d29998c2893141ece874", "parents": [ "c94fb400ec40a8550a89cd484bd1137dca029336" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Jul 10 16:09:31 2023 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Thu Aug 24 11:08:53 2023 -0500" }, "message": "refactor(fgt): modify FEAT_FGT test to check for init values\n\nThe original test checked only if FEAT_FGT was enabled. This new version\nof the test also checks whether the values of registers HFG*_EL2 are the\nvalues used during initialization.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I17673b813da7f14ef03349eead2c0a47cf3a8b26\n" }, { "commit": "c94fb400ec40a8550a89cd484bd1137dca029336", "tree": "863c7398f9252136f958d03c3b6d6ce5fc781ec1", "parents": [ "c68ba0dec2989735fa24a8ed4efcf9cd76af2b05" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri Jul 21 17:19:42 2023 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Thu Aug 24 11:05:53 2023 -0500" }, "message": "feat(cpufeat): add feat detection helpers\n\nThis patch adds multiple feature detection helpers, useful for\ntests that need to check for the presence of those features.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ie6d39b9e9c8d28d0a4cd9d02350e2bedd016e45e\n" }, { "commit": "c68ba0dec2989735fa24a8ed4efcf9cd76af2b05", "tree": "e379d0c4466931f1f10e7e2de2491ea6f1650549", "parents": [ "6d0064ec03f7f54d780ec8bd5e294948e1d4c9e6", "f667cda23a83e293b0a81cc4fba94d6a005313a0" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Aug 21 16:11:29 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 21 16:11:29 2023 +0200" }, "message": "Merge changes from topic \"jc/clang_support\"\n\n* changes:\n docs: add note on building TFA-Tests using clang\n build(clang): introduce clang toolchain support\n" }, { "commit": "f667cda23a83e293b0a81cc4fba94d6a005313a0", "tree": "e379d0c4466931f1f10e7e2de2491ea6f1650549", "parents": [ "d2a6364cbe2281bcdfbadccceea995db7b63e3b9" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jun 27 15:01:52 2023 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Aug 17 14:26:21 2023 +0100" }, "message": "docs: add note on building TFA-Tests using clang\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I1e9bb7df2a7eb4977901f4ad67f9fa5f292963f6\n" }, { "commit": "d2a6364cbe2281bcdfbadccceea995db7b63e3b9", "tree": "80af05680b092d6632bc090e09eb8389656acee6", "parents": [ "6d0064ec03f7f54d780ec8bd5e294948e1d4c9e6" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jun 06 09:03:53 2023 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Aug 17 11:40:48 2023 +0100" }, "message": "build(clang): introduce clang toolchain support\n\nOnly the compiler is switched to clang. The assembler and the\nlinker are provided by the GCC toolchain.\n\nclang is used to build TFTF when the base name of the path assigned\nto \"CC\" variable contains the string \u0027clang\u0027.\n\n\u0027CROSS_COMPILE\u0027 flag is still required and must point to the\nappropriate GCC toolchain.\n\n*Note:\nCompiling TF-A tests with clang toolchain has following\nissues which are not listed/overlooked in GCC. Henceforth, few\nsections of the code have been refactored accordingly:\n\n1. error: instruction requires: wfxt\n fix : build with ARM_ARCH_MINOR\u003d7.\n\n2. error: initializer element is not a compile-time constant\n test_ffa_setup_and_discovery.c:33:11[.uuid \u003d sp_uuids[0]]\n sp_test_ffa.c:38:11:.uuid \u003d sp_uuids[0]\n\n fix: gcc overlooks this error but clang doesn\u0027t. Hence\n initializer elements are explicitly specified.\n\nThis is an introductory patch to cover the following targets.\n1. tftf\n2. ivy\n3. realm\n4. cactus\n5. cactus_mm\n6. ns_bl1u\n\nOther tf-a tests targets need to be ported and will be\nimplemented explicitly in separate patches.\n\nIn summary, with this patch, we will be able to compile\nTFTF code covering the targets with the following command:\n\n**********************************************************\n* Build TFTF Aarch64 ( Default Build ) with Clang support\n* tested with clang version: 14.0.0\n**********************************************************\nmake CC\u003d${CLANG_PATH}/clang \\\nPLAT\u003dfvp \\\nCROSS_COMPILE\u003daarch64-none-elf- \\\nARM_ARCH_MINOR\u003d7 \\\nV\u003d0 tftf ivy realm cactus cactus_mm ns_bl1u -j12\n********************************************************\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I409d11b596dfd50a3d25598679808dd9fcfc51e5\n" }, { "commit": "6d0064ec03f7f54d780ec8bd5e294948e1d4c9e6", "tree": "3c4d15bdf1c2426c1a89de8668f56727ebb8b5f3", "parents": [ "d451594043a3b5489e346109bc758794de77b297", "8627a10dcdadeaf9f0616020567e51808f80e3e6" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 14 17:13:02 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 14 17:13:02 2023 +0200" }, "message": "Merge changes from topic \"el3_direct_msg\"\n\n* changes:\n feat: use x0-x17 for ff-a calls\n test: add discovery of el3 spmd logical partitions\n feat(ff-a): partition information via registers\n" }, { "commit": "d451594043a3b5489e346109bc758794de77b297", "tree": "0feea8197594426b4937d6a55d80b3f9b042e00e", "parents": [ "78205af3cfa78b263cc94df0159bfa22a7fc8746", "e69d128de6f6e8fcc9e4c02433cea0cf0bf965cf" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Sat Aug 12 11:45:12 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Aug 12 11:45:12 2023 +0200" }, "message": "Merge changes from topic \"km/sp_layout\"\n\n* changes:\n refactor(generate_json): use multiline strings in `generate_json.sh`\n feat(sptool): add `physical-load-address` field to `sp_layout.json`\n" }, { "commit": "e69d128de6f6e8fcc9e4c02433cea0cf0bf965cf", "tree": "0feea8197594426b4937d6a55d80b3f9b042e00e", "parents": [ "657f6b26a34deef0a69eaf6406763505087abe1c" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Mar 07 17:10:07 2023 +0000" }, "committer": { "name": "Joao Alves", "email": "joao.alves@arm.com", "time": "Fri Aug 11 15:40:57 2023 +0100" }, "message": "refactor(generate_json): use multiline strings in `generate_json.sh`\n\nUsing multiline strings (delimited by `EOF` on each side) means the\ncontents of the json file can be inserted verbatim into\n`generate_json.sh`, rather than inserting escape codes (`\\t` and `\\n`)\nmanually.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I85b8287712ea4cb99e70c58482df0d886b780dde\n" }, { "commit": "657f6b26a34deef0a69eaf6406763505087abe1c", "tree": "404a4343481a2abc75dc0b17b74cd91dd80a2e5a", "parents": [ "78205af3cfa78b263cc94df0159bfa22a7fc8746" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Mar 07 16:44:24 2023 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Fri Aug 11 11:49:09 2023 +0100" }, "message": "feat(sptool): add `physical-load-address` field to `sp_layout.json`\n\n`physical-load-address` is now expected in `sp_layout.json` by\nhttps://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19589\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I8df6c9bfab004f65e6ac3bc0467ade6dc3bf5ee2\n" }, { "commit": "78205af3cfa78b263cc94df0159bfa22a7fc8746", "tree": "b4d0a76bf7a45b242e8b62612381f6151b6e36c0", "parents": [ "868c623c786b9c403df1eb57515c828e0b2e8982", "40c9e05aa321066690d8926f6e46fe1f31e3c691" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Mon Aug 07 15:37:06 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 07 15:37:06 2023 +0200" }, "message": "Merge changes from topic \"xlnx_versal_intro\"\n\n* changes:\n docs(maintainers): add maintainers for AMD-Xilinx\n docs(versal): add versal documentation\n feat(versal): add platform specific testcase\n feat(versal): introduce platform support\n" }, { "commit": "8627a10dcdadeaf9f0616020567e51808f80e3e6", "tree": "850cda6b62bacf00558505b83ade9cc32108a0cb", "parents": [ "9f864523cb2a5a3581b7f5a0b99410838b7cb9bd" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Sun Jul 09 16:42:23 2023 -0700" }, "committer": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 03 07:08:20 2023 -0700" }, "message": "feat: use x0-x17 for ff-a calls\n\nUpdate ff-a calls to use all registers from x0-x17 as input and as\noutput. Previously, only x0-x7 were being used.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nChange-Id: I52e9f4749578f5e6265dff9beb6b0520dcc72bc5\n" }, { "commit": "9f864523cb2a5a3581b7f5a0b99410838b7cb9bd", "tree": "f8c0446f05fe4e4664f375b846b3952f29473a0b", "parents": [ "ab5321a53201619be2be50b9b0d14cd2fee51299" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Sun Apr 23 16:19:10 2023 -0700" }, "committer": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 03 07:08:20 2023 -0700" }, "message": "test: add discovery of el3 spmd logical partitions\n\nThis patch adds a test to query the presence of an SPMD logical\npartition and also tests basic functionality using the\nffa_partition_info_get_regs abi. Note that the register based discovery\nreports the presence of el3 spmd logical partitions whereas the memory\nbased discovery interface does not report the el3 spmd logical\npartitions. To that end, the patch adds helper functions to use the\nregister based discovery, and also refactors code that can be shared\nbetween the register and memory based interfaces.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nChange-Id: I755ffe4098c635de2c6aeb0ebe73eb16c3acd206\n" }, { "commit": "ab5321a53201619be2be50b9b0d14cd2fee51299", "tree": "2b15c3c77a8dac037f83b588ce4c9680ac5c7abc", "parents": [ "868c623c786b9c403df1eb57515c828e0b2e8982" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Sun Apr 23 16:14:28 2023 -0700" }, "committer": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 03 07:08:20 2023 -0700" }, "message": "feat(ff-a): partition information via registers\n\nThis patch enables basic support for getting partition information via\nthe ffa_partition_info_get_regs abi. This interface can be used to query\npartition information in the absence of rx/tx buffer or when using\nmemory is inconvenient (such as early boot loaders etc). The patch adds\nthe required calls, a few helper functions and enables the use of x8-x17\nas return values, that is required for this abi to work.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nChange-Id: I70ed78e809a5bf77d77a49e5bc122c1989303ebb\n" }, { "commit": "868c623c786b9c403df1eb57515c828e0b2e8982", "tree": "2d79e9005a7be2dfa1c73c5b495da9207a3cf42e", "parents": [ "9945bef6b68914e6f412fc91cac6be938ce3dcf3", "85b20404d4bbeb72475c451f4137e6f9f53a60c5" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Wed Aug 02 18:55:52 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 02 18:55:52 2023 +0200" }, "message": "Merge \"fix: build dependency in test-realms-payload\"" }, { "commit": "9945bef6b68914e6f412fc91cac6be938ce3dcf3", "tree": "4077f539db6348bbe57d3e7c0c562711189ed391", "parents": [ "13a116c321ffe34c32d4349ac7892b61d8f589d9", "c973b2a60d860775d945b1186b8ca0dfaf29286a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Aug 02 14:26:28 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 02 14:26:28 2023 +0200" }, "message": "Merge \"feat(rme) : introduce new build flag for RME stack\"" }, { "commit": "c973b2a60d860775d945b1186b8ca0dfaf29286a", "tree": "630753887c069f9f5d1eac2539153f84911eb648", "parents": [ "9d0cfe88aedc34f1b61a51ff18013743c56e2fbc" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Jul 12 12:10:54 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Aug 02 11:17:52 2023 +0100" }, "message": "feat(rme) : introduce new build flag for RME stack\n\n* Introduce new build flag ENABLE_REALM_PAYLOAD_TESTS to build\n Realm Payload Tests and pack realm image to tftf.bin.\n* Also enable PAuth for TFTF and Realm Payload by default\n for RME stack.\n* This commit deprecates the use of `pack_realm` build target.\n* The patch also modifies the user guide instructions to build\n and pack realm payload tests.\n\nNOTE: The `pack_realm` build target, even though deprecated,\nis still available for compatibility reasons. It will be\nremoved in a future commit.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Iaa83651c2f41152a5a2bf4d0b9caa550f302da6b\n" }, { "commit": "85b20404d4bbeb72475c451f4137e6f9f53a60c5", "tree": "40de38427094e6721b6dba242ed5d2f92667c3cb", "parents": [ "13a116c321ffe34c32d4349ac7892b61d8f589d9" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Aug 01 16:54:06 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Aug 01 17:03:46 2023 +0100" }, "message": "fix: build dependency in test-realms-payload\n\nThe patch [1] refactored the SPM testing code to\nreorganise the build for aarch32 of SPM test code.\n\nThis broke a dependency of host_realm_spm.c.\nThis patch uses the source file that was created in [1]\nto provide the necessary dependency.\n\n[1] https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/22272\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I07885cbfee18810610bd2c42d399de77ef2352c1\n" }, { "commit": "13a116c321ffe34c32d4349ac7892b61d8f589d9", "tree": "5360407a2804a6c5c0f0c0ad97dc2c5652e6d7b7", "parents": [ "229d8a4c5d118db288325e3390278bc17d2f25ef", "60de7acf24476f976ce6a9e712148990b42cb544" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 01 17:34:02 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 01 17:34:02 2023 +0200" }, "message": "Merge \"fix(spm): FFA_VERSION to return error\"" }, { "commit": "229d8a4c5d118db288325e3390278bc17d2f25ef", "tree": "74b83622d50166d19c842b0db9eaab4f64782b43", "parents": [ "84986d5d9f95d6a300339f94e05003267a743e02", "82bf339c9e178e8200f763146f2f21abee9410ea" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 01 15:54:46 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 01 15:54:46 2023 +0200" }, "message": "Merge \"fix(spm): stop spm from being built for in aarch32\"" }, { "commit": "60de7acf24476f976ce6a9e712148990b42cb544", "tree": "4820fe8ee979f9afefbdb717fb71f2368c059a17", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 31 14:02:08 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 31 17:25:50 2023 +0100" }, "message": "fix(spm): FFA_VERSION to return error\n\nSPM is expected to return error when the version provided by the caller\nis not compliant with that of the SPMC.\nBefore the assumption was that the SPMC would always return its own\nversion.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I590c858bf73c059772193d994becbb8f7a2b170e\n" }, { "commit": "84986d5d9f95d6a300339f94e05003267a743e02", "tree": "b5b65d1a477d3d46aacfb69bd3dff348a2136ce4", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669", "9d0cfe88aedc34f1b61a51ff18013743c56e2fbc" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jul 31 18:04:40 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 31 18:04:40 2023 +0200" }, "message": "Merge \"test(tftf): test PAuth in Realm\"" }, { "commit": "82bf339c9e178e8200f763146f2f21abee9410ea", "tree": "d37718c9f321f866fbe0480ea758fb5175a5c032", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jul 28 18:32:27 2023 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Mon Jul 31 16:59:23 2023 +0100" }, "message": "fix(spm): stop spm from being built for in aarch32\n\nHafnium does not support Aarch32 therefore we do not want to build\nin this case. Move spm related test helpers into their own file\nand add FF-A tests to the aarch32_tests_to_skip.txt file\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ic5a83ddf4aae2b7dd4b1c30e4cc76b0447e5b405\n" }, { "commit": "40c9e05aa321066690d8926f6e46fe1f31e3c691", "tree": "968a52ba7a54f76c910bc90ac87a9fe343f6b1d9", "parents": [ "e52f311919f3e64563c054fa2b7760d0b2a92fc6" ], "author": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Mon Jul 17 12:27:46 2023 +0530" }, "committer": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Thu Jul 27 23:02:04 2023 +0530" }, "message": "docs(maintainers): add maintainers for AMD-Xilinx\n\nAdd following as maintainers for AMD Xilinx Platform ports\nfor TF-A Tests\n- Michal Simek\n- Amit Nagal\n- Akshay Belsare\n\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nChange-Id: I796fde094544c53d2fc6e6b6083b0687a152f276\n" }, { "commit": "e52f311919f3e64563c054fa2b7760d0b2a92fc6", "tree": "552817196c317a881bef317faf4ff3ff5b7b5188", "parents": [ "53538e2cc4bd5faf0fced533d5407a214298f3cb" ], "author": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Fri Jun 30 15:46:34 2023 +0530" }, "committer": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Thu Jul 27 23:02:04 2023 +0530" }, "message": "docs(versal): add versal documentation\n\nAdd information about Versal platform for TF-A Tests and\nprovide the build commands.\n\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nChange-Id: I127842889c6bbeda5a4462c43deb6dbcb4f5e2bc\n" }, { "commit": "53538e2cc4bd5faf0fced533d5407a214298f3cb", "tree": "652f9a4b6627d97c40f48752ee099956f64bb6c0", "parents": [ "52aefd94f5b047e40c6c7902415cc6ae48688d8e" ], "author": { "name": "Akshay Belsare", "email": "Akshay.Belsare@amd.com", "time": "Thu Jul 28 14:54:22 2022 +0530" }, "committer": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Thu Jul 27 23:01:25 2023 +0530" }, "message": "feat(versal): add platform specific testcase\n\nAdd common platform test to read the PM-API version and Chip ID.\nSpecify TESTS\u003dversal in make command. This will append the versal specific\ntests to standard tests\n\n--\nRunning test suite \u0027AMD-Xilinx tests\u0027\nDescription: AMD-Xilinx common platform tests\n\n\u003e Executing \u0027Read PM API Version\u0027\n TEST COMPLETE Passed\ntest_pmapi_version PM-API Version : 1.0\n\n\u003e Executing \u0027Get Platform Chip ID\u0027\n TEST COMPLETE Passed\ntest_get_chipid Idcode \u003d 0x14ca8093 Version \u003d 0x302020\n\n--\n\nSigned-off-by: Akshay Belsare \u003cAkshay.Belsare@amd.com\u003e\nChange-Id: I33fbdd42427fd0913001b83990e98b8ecbcc2282\n" }, { "commit": "52aefd94f5b047e40c6c7902415cc6ae48688d8e", "tree": "a769e8e2eeed65f0261fb6e8a674e03c55d28e4e", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Tue Apr 04 10:26:40 2023 +0530" }, "committer": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Thu Jul 27 22:57:37 2023 +0530" }, "message": "feat(versal): introduce platform support\n\nIntroduce platform support for AMD-Xilinx Versal, an adaptive compute\nacceleration platform (ACAP).\n- pl011 is used for console.\n- TTC is used for Timers.\n- NVM is not supported.\n\nWatchdog timer support to come in another change\n\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 172\nTests Passed : 38\nTests Failed : 5\nTests Crashed : 0\nTotal tests : 215\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nSigned-off-by: Michal Simek \u003cmichal.simek@amd.com\u003e\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nChange-Id: If358a8018f4106d2267b6bed8eadbfdbaa48ad39\n" }, { "commit": "9d0cfe88aedc34f1b61a51ff18013743c56e2fbc", "tree": "b5b65d1a477d3d46aacfb69bd3dff348a2136ce4", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Apr 17 10:57:26 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Jul 25 17:00:33 2023 +0100" }, "message": "test(tftf): test PAuth in Realm\n\n- Enable PAuth in Realm RL1 by default.\n- Check if PAuth keys are accessible in Realm RL1.\n- Check if Realm PAuth keys are preserved across RMM entry/exit.\n- Check if NS PAuth keys are preserved across RMM entry/exit.\n- Generate PAuth fault by cloberring LR.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I85d8e03ec604c96117555e7aa866453cb2745cfe\n" }, { "commit": "85d58f31f121445225c2b9e6ee94c8589cc36669", "tree": "d3fb20a81e2b42cccab1aa507d167965f7a5098c", "parents": [ "e29164adb371ac6431cd25998c89cc8f93d9bc89", "0199b6aa571686cc5d2473c64c94214fbbe63896" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 04 09:20:14 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 04 09:20:14 2023 +0200" }, "message": "Merge \"fix(docs): make generate_test_list backward compatible\"" }, { "commit": "0199b6aa571686cc5d2473c64c94214fbbe63896", "tree": "d3fb20a81e2b42cccab1aa507d167965f7a5098c", "parents": [ "e29164adb371ac6431cd25998c89cc8f93d9bc89" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Jul 03 11:24:41 2023 +0100" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Jul 03 17:52:49 2023 +0100" }, "message": "fix(docs): make generate_test_list backward compatible\n\nThe recently introduced script generate_test_list.py [1] relies on\nfeatures from Python 3.9. This breaks the build for users using earlier\npython versions e.g. python 3.8 deployed in Ubuntu 20.04 LTS. Bump the\nminimum version requirements and make the script backward compatible\nwith older versions of Python.\n\n[1] https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/21135\n\nChange-Id: I07fd47af0309787b08cd0f77aaeb7d50b9cae144\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "e29164adb371ac6431cd25998c89cc8f93d9bc89", "tree": "82662ebb6fb15997a05596fa2f4851d48a0644c2", "parents": [ "47b2cb2f314a4d1e0d43c90f65edb66a4b4f9475", "7ba27bf9b56fe5981317b4434525633a678329b8" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jul 03 09:27:33 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 03 09:27:33 2023 +0200" }, "message": "Merge \"refactor(build): python generate_test_list script\"" }, { "commit": "7ba27bf9b56fe5981317b4434525633a678329b8", "tree": "7081d09eb082edf72601449154f9162ff0b8fd54", "parents": [ "677c2b895f41b5cbe8a3b14c149871ce07381476" ], "author": { "name": "Jim Ray", "email": "jimray@google.com", "time": "Thu May 25 14:11:51 2023 -0700" }, "committer": { "name": "Jim Ray", "email": "jimray@google.com", "time": "Thu Jun 29 23:47:34 2023 -0700" }, "message": "refactor(build): python generate_test_list script\n\nThis change introduces generate_test_list.py which is exactly like\ngenerate_test_list.pl except written in python. This helps remove a\ndependency on perl as well as a dependency on perl\u0027s libxml bindings.\nThe only required dependency is python3 and its standard library.\n\nTested by generating tests_list.c/h for each xml file and each platform\nand comparing it against the output from the original script.\n\nSigned-off-by: Jim Ray \u003cjimray@google.com\u003e\nChange-Id: If0fa8d0e45bf58ce35081aaeb7a9320dfcefdbf9\n" }, { "commit": "47b2cb2f314a4d1e0d43c90f65edb66a4b4f9475", "tree": "0d4e9ed3ed84f39507d658f3e75305b715ebbcd1", "parents": [ "677c2b895f41b5cbe8a3b14c149871ce07381476", "c19215adf93502c19c766f5b621051b3398fac05" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Jun 28 15:44:38 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 28 15:44:38 2023 +0200" }, "message": "Merge \"refactor(tc): Make tc0 tftf code generic to tc.\"" }, { "commit": "677c2b895f41b5cbe8a3b14c149871ce07381476", "tree": "673285b503346bbf3a88b3806f6d9d16ec982277", "parents": [ "35d5fe4ad5242d69d8911b57a842a77ec69f0dfa", "eb29954598e54549a45d15eeee06b7213022c277" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 23 12:28:57 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 23 12:28:57 2023 +0200" }, "message": "Merge \"fix(fpu): write random value to fpsr/fpcr instead of read\"" }, { "commit": "c19215adf93502c19c766f5b621051b3398fac05", "tree": "3f8d7037f4b9636ee16f9b7139a8b3e5dc9a7ac1", "parents": [ "35d5fe4ad5242d69d8911b57a842a77ec69f0dfa" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed May 17 13:50:36 2023 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Thu Jun 22 15:10:20 2023 +0100" }, "message": "refactor(tc): Make tc0 tftf code generic to tc.\n\nThis code can be used for tc0, tc1 and tc2 testing so change from\ntc0 naming to tc.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ied011db0cd688936d6ba20e48c5206de4891e732\n" }, { "commit": "eb29954598e54549a45d15eeee06b7213022c277", "tree": "673285b503346bbf3a88b3806f6d9d16ec982277", "parents": [ "35d5fe4ad5242d69d8911b57a842a77ec69f0dfa" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 19 10:59:58 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 20 21:52:56 2023 +0100" }, "message": "fix(fpu): write random value to fpsr/fpcr instead of read\n\nThe inline assembly code to write random values to FPSR and FPCR,\nactually does a read. This zero out the random value that is used as a\ntemplate to fill FPU [Q0-Q31] registers.\n\nWhen this helper routine is used by Non-secure, SP or Realm context\nthe FPU state written to the registers is always zero. The test cases\nthat verifies whether the FPU state is preserved across the world switch\nmight PASS always as it works with an empty FPU state.\n\nThis fix also changes fpu_state_print() to print the content of Q0-Q31\nregisters instead of the address.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7bc2deba034b9bb4b6c1b15fe91f4562fd64d8f0\n" }, { "commit": "35d5fe4ad5242d69d8911b57a842a77ec69f0dfa", "tree": "46d470e8b6adf18465b291e16d9e2b0c38459784", "parents": [ "b5a2b1386ab6eab08a759b9ef21e9ffe686fe7dc", "e62b67b7d9fb2b97d4a03b83584c1c39aa162b27" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jun 16 10:33:55 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 16 10:33:55 2023 +0200" }, "message": "Merge \"feat(ras): introduce RAS KFH support test\"" }, { "commit": "b5a2b1386ab6eab08a759b9ef21e9ffe686fe7dc", "tree": "72a8b441bbd98420bffe6579e4548437c55afcdc", "parents": [ "490086cc103920d67ada288d0d7d48ada375796e", "a61927e67946cb8b67866ebfe77fa62653d4bebf" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Jun 16 10:30:15 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 16 10:30:15 2023 +0200" }, "message": "Merge \"fix(sme): align SME test vector arrays to 16 bytes\"" }, { "commit": "a61927e67946cb8b67866ebfe77fa62653d4bebf", "tree": "72a8b441bbd98420bffe6579e4548437c55afcdc", "parents": [ "490086cc103920d67ada288d0d7d48ada375796e" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jun 01 17:16:00 2023 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Jun 16 09:19:41 2023 +0200" }, "message": "fix(sme): align SME test vector arrays to 16 bytes\n\nSME test vectors need 16 bytes alignment for the related\ninstructions to work properly.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ifd5db7a3536d4b26f9922d1a0bfb09351c4fa6ab\n" }, { "commit": "e62b67b7d9fb2b97d4a03b83584c1c39aa162b27", "tree": "fb24fc1edd46fefff023ad7cba875e8a58104362", "parents": [ "2b47c60206a6d33784c334956d5e6e72432fcc8f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Feb 27 15:21:26 2023 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jun 15 09:10:29 2023 +0100" }, "message": "feat(ras): introduce RAS KFH support test\n\nIntroduce a test to verify Kernel first handling of RAS errors.\nError is injected and handled in tftf, there is no EL3 involvement.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Iaf93247647bf8b749cba5ea42fd819dee675b04b\n" }, { "commit": "490086cc103920d67ada288d0d7d48ada375796e", "tree": "fab6ee4b328549592dd173d729569011b67fe9ab", "parents": [ "2b47c60206a6d33784c334956d5e6e72432fcc8f", "6a9ac6f600325d3d8fa7b9ac41272f67c130b4ad" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Jun 14 14:48:23 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 14 14:48:23 2023 +0200" }, "message": "Merge \"fix(cactus): assign unique boot orders to SPs\"" }, { "commit": "2b47c60206a6d33784c334956d5e6e72432fcc8f", "tree": "b2307d260395753bd714732500f51cd1f307f1ff", "parents": [ "baed8dd3577633768837048cb71351fb135d59ee", "d648077f8284ada21b03871ce06bf568a2333bbd" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jun 14 10:39:03 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 14 10:39:03 2023 +0200" }, "message": "Merge \"feat: introduce SError exception handler\"" }, { "commit": "d648077f8284ada21b03871ce06bf568a2333bbd", "tree": "b2307d260395753bd714732500f51cd1f307f1ff", "parents": [ "baed8dd3577633768837048cb71351fb135d59ee" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Feb 27 13:23:06 2023 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 13 13:58:31 2023 +0200" }, "message": "feat: introduce SError exception handler\n\nIntroduce SError exception handler along with support to register a\ncustom handler. The default behaviour is same as before if no handler\nis registered.\nThis patch will allow tests to do a graceful exit after handling an\nSError.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Idbe37d3690e3a8e08fa3b0dff496d18d3022a8fc\n" }, { "commit": "baed8dd3577633768837048cb71351fb135d59ee", "tree": "b140a1dc8523728a9c551a129b0f7abadf977934", "parents": [ "0e9169e423910d180ac49116ac60975d7222cca8", "9cb6f51b7ed267865a13b5e3cc9c73542bad51b1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 13 12:39:13 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 13 12:39:13 2023 +0200" }, "message": "Merge changes from topic \"mp/serror_refactor\"\n\n* changes:\n feat(ras): move wait logic from assembley to C\n refactor(ras): rename sdei related functions/events\n" }, { "commit": "9cb6f51b7ed267865a13b5e3cc9c73542bad51b1", "tree": "b140a1dc8523728a9c551a129b0f7abadf977934", "parents": [ "0674e41d0c422f85af5257423d605e33fa6a676c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Mar 06 10:14:50 2023 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 13 11:13:14 2023 +0100" }, "message": "feat(ras): move wait logic from assembley to C\n\nSDEI test uses a flag to be updated through SDEI handler to ensure that\ntest has passed, this logic was implemented in assembly, move this logic\nin C to make it easily readable.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I4c92aa7a6fbeb5fcdb4c67b0166627a539609f18\n" }, { "commit": "0674e41d0c422f85af5257423d605e33fa6a676c", "tree": "05e3e3956234d0e05083a9a7c082cc80f91fc867", "parents": [ "0e9169e423910d180ac49116ac60975d7222cca8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Feb 21 13:05:07 2023 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 13 11:11:04 2023 +0100" }, "message": "refactor(ras): rename sdei related functions/events\n\nFunction to report sdei event was named on the basis of serror which has\ncaused that error. SError can be used in many cases and SDEI is one of\nits usecases.\nMake SDEI related names explicit.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I451008a7e5bfa34d8c4e8fb3c0c59b90c4bb7e5f\n" }, { "commit": "0e9169e423910d180ac49116ac60975d7222cca8", "tree": "041037f8c7b3126163c8988fd8041712da8447ff", "parents": [ "c6a7da1d61f58875e4c85922a62f145d19c1467c", "2a32ff7161ef8711f9e7420c499a246e3d055f42" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Jun 06 17:04:57 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 06 17:04:57 2023 +0200" }, "message": "Merge changes from topic \"lpa2-support\"\n\n* changes:\n feat(xlat): add support for 52 bit PA size with 4KB granularity\n fix(tftf): disable RMI tests when building for aarch32 architecture\n" }, { "commit": "2a32ff7161ef8711f9e7420c499a246e3d055f42", "tree": "041037f8c7b3126163c8988fd8041712da8447ff", "parents": [ "ec59c59afc953c306a4b83e919a787694ee6a88f" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu May 25 17:51:48 2023 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Jun 06 11:00:21 2023 +0100" }, "message": "feat(xlat): add support for 52 bit PA size with 4KB granularity\n\nThis patch adds support to the xlat library to for 52Bits of\nPA size with 4KB granularity (FEAT_LPA2). The patch only reports\nthe right granularity when it supports FEAT_LPA2 and it does\nnot enable the feature.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Iee0cab8e1f8844a6af135771d8f940ec7e1dce84\n" }, { "commit": "ec59c59afc953c306a4b83e919a787694ee6a88f", "tree": "22407000f18ce6453dc5a10c8bf3d28f740f0e03", "parents": [ "c6a7da1d61f58875e4c85922a62f145d19c1467c" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu May 25 17:51:48 2023 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Jun 06 11:00:15 2023 +0100" }, "message": "fix(tftf): disable RMI tests when building for aarch32 architecture\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6fa83808f7101de50141c89c044425ea355c8f6d\n" }, { "commit": "c6a7da1d61f58875e4c85922a62f145d19c1467c", "tree": "3a192f12127f5c2f7c5a323dac343c5c4caa5ff8", "parents": [ "64c351e42dc5b384bb200725c32e66ad67fea760", "fb98ffd60a30c8d2b67b49bf7482fff8be7c6488" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jun 05 15:47:42 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 05 15:47:42 2023 +0200" }, "message": "Merge \"fix(realm): align realm stack\"" }, { "commit": "64c351e42dc5b384bb200725c32e66ad67fea760", "tree": "5dd128bc21f399ec872ecb9d8b969d29784ef78e", "parents": [ "8ebb89cae65a199e80894775b80a202f50e94cec", "9af432e408b3e66f3e4cd00cbc98486c7bd9be03" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jun 05 15:47:34 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 05 15:47:34 2023 +0200" }, "message": "Merge \"fix(tftf): command id passed to realm to compare FPU registers\"" }, { "commit": "fb98ffd60a30c8d2b67b49bf7482fff8be7c6488", "tree": "3a192f12127f5c2f7c5a323dac343c5c4caa5ff8", "parents": [ "9af432e408b3e66f3e4cd00cbc98486c7bd9be03" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 05 11:33:33 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 05 13:53:56 2023 +0100" }, "message": "fix(realm): align realm stack\n\nrealm_entrypoint fails while accessing unaligned stack base. This\nissue happens when a newly added global variable shifts the end of\nstack to be unaligned.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I75901a2ead41adc0a19f92896be9e75b1fc882c6\n" }, { "commit": "9af432e408b3e66f3e4cd00cbc98486c7bd9be03", "tree": "5dd128bc21f399ec872ecb9d8b969d29784ef78e", "parents": [ "8ebb89cae65a199e80894775b80a202f50e94cec" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Fri Jun 02 17:18:23 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 05 11:52:21 2023 +0100" }, "message": "fix(tftf): command id passed to realm to compare FPU registers\n\nThis fixes the command id passed to Realm to compare FPU/SIMD regs.\nAnd also adds a missing break statement in Realm payload main entry\nfunction for command REALM_REQ_FPU_CMP_CMD.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Iaf7073475291785990a55675746968b291fdf507\n" }, { "commit": "8ebb89cae65a199e80894775b80a202f50e94cec", "tree": "ad7ab2a893df09875a82f0071b49d4020e19e098", "parents": [ "9493aad1236f938d6bb696219b38d1848cecbe6c", "64ef286d90c1bc7906b93fc4d433b674e9278c5f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jun 05 12:10:24 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 05 12:10:24 2023 +0200" }, "message": "Merge \"Update test_psci_stat.c to support more pwr levels\"" }, { "commit": "64ef286d90c1bc7906b93fc4d433b674e9278c5f", "tree": "ad7ab2a893df09875a82f0071b49d4020e19e098", "parents": [ "9493aad1236f938d6bb696219b38d1848cecbe6c" ], "author": { "name": "Jim Ray", "email": "jimray@google.com", "time": "Fri May 26 14:49:19 2023 -0700" }, "committer": { "name": "Jim Ray", "email": "jimray@google.com", "time": "Wed May 31 01:00:57 2023 -0700" }, "message": "Update test_psci_stat.c to support more pwr levels\n\nThis change updates some hardcoded constants to reflect the fact that\nadditional power levels are supported.\n\nSigned-off-by: Jim Ray \u003cjimray@google.com\u003e\nChange-Id: I97399ee0cf74fe28ae1a3e5fbfc2b00c8dfe7d67\n" }, { "commit": "9493aad1236f938d6bb696219b38d1848cecbe6c", "tree": "2f6cca85a222bc14e090170109ded090535ef5b2", "parents": [ "2e179ff207dd8afb9c1fded635e90250dc433445", "5270d01e968b1b0a8b853a9263e767a467e541b9" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed May 24 15:21:56 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 24 15:21:56 2023 +0200" }, "message": "Merge changes from topic \"realm-sve\"\n\n* changes:\n tftf(rme): check if RMM doesn\u0027t leak Realm contents in SVE registers\n tftf(rme): intermittently switch to Realm while doing NS SVE ops\n refactor(sve): move sve operations to a lib routine\n feat(rme): add SVE Realm tests\n" }, { "commit": "5270d01e968b1b0a8b853a9263e767a467e541b9", "tree": "ac67959df7b5d536b4c662ed1f0a0e2f19970980", "parents": [ "c1136a849fc21470313e4e852a22ae4b9db50440" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 19 14:53:42 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed May 24 13:40:42 2023 +0100" }, "message": "tftf(rme): check if RMM doesn\u0027t leak Realm contents in SVE registers\n\nThis test verifies that the Realm contents in SVE registers are not\nseen by NS world once the Realm returns back to the host. This test\nperforms the below steps:\n\n1. Set NS world SVE VQ to max and write a known pattern.\n2. Set NS world ZCR_EL2 with VQ as 0 (128 bits).\n3. Create Realm with max SVE VQ\n4. Call Realm to fill in Z registers\n5. Once Realm returns, NS sets ZCR_EL2 with max VQ and reads the\n Z registers.\n6. The upper bits of Z registers must be either 0 or the old values\n filled by NS world at step 1.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I8205190d1ce9c37b99d35cf5b15df21ca9b838c3\n" }, { "commit": "c1136a849fc21470313e4e852a22ae4b9db50440", "tree": "b6b5e8854589497f4e2d2c159f0bd2e590dcd8c5", "parents": [ "d179ddcc64cac3b319b301cfe6c1bc32c1ea0eaf" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 12 15:24:44 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed May 24 13:40:42 2023 +0100" }, "message": "tftf(rme): intermittently switch to Realm while doing NS SVE ops\n\nInterleave NS SVE operations with Realm SVE operations and check whether\nSVE vectors are not affected.\n\nThis test also configures SVE op array and SVE vector length with random\nvalue in NS and Realm for test each iteration.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7a9ba4bd0d298f187baa3048ec622eb97ec3d99f\n" } ], "next": "d179ddcc64cac3b319b301cfe6c1bc32c1ea0eaf" }