)]}' { "log": [ { "commit": "055adff8d7e5431174672c7aac0bc530c4e7a778", "tree": "2968cec4c85ea200c4838a268ccd13dba9a5c7ad", "parents": [ "6d144db95cd1ee317bf66efade0fd5d4e0909c3c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:34:12 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "refactor(gic): defer IRQ handler management to the GIC driver\n\nInterrupt groups are not generic between GIC versions. SGIs and eSPIs\ndisappear, while SPIs and LPIs subtly change function. So abstract all\nof this away and hide it behind each individual GIC driver.\n\nChange-Id: Iaa55014b2940969508b290736c43134688e8c422\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "6d144db95cd1ee317bf66efade0fd5d4e0909c3c", "tree": "0b57d1214fe208e82a5b56ba03b06cec0074700f", "parents": [ "e5629bd4c6ab6088e21e7f4e2f4a27495945e21a" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:04:53 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "refactor(gic): make the concept of SGI generic\n\nSoftware generated interrupts (SGIs) are a GICv2/3/4 concept. However,\nthey are deeply embedded in how TFTF handles wake ups. This patch\npromotes the SGI to an abstract concept that can be performed\nindependently of the interrupt controller, largely the same as it is\nused today. To do that the interrupt interface for an SGI is separated\nfrom the general IRQ and each SGI is assigned a linear index from 0\nonwards. Translating from SGI to IRQ is done via a hook in arm_gic.c\nthat will be multiplexed to the appropriate driver. For GIC \u003c\u003d v3 this\nis a thin wrapper around the identity mapping as SGIs map to INTIDs from\n0 through 15. For GICv5 the mapping is different and an SGI is an LPI\nand calculated as recommended by chapter 2.5 in the spec.\n\nAdditionally, the definitions of SGI numbers are made generic as no\nplatform has utilised the difference.\n\nChange-Id: I7e6a5fbe655098c5e235b98f6dda8a14619a5904\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "dcf9d6f994ef8b803fe6ea270a8c06634c97f8fc", "tree": "cc760f3bae7d7fec7fc8c1c1faee06af4ee53a65", "parents": [ "6cc4372c4036066a940a2bb82debf2ce311070e7", "595bd11a476e81d2bdc22095cac74db51c717a6b" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Sep 25 14:28:37 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 25 14:28:37 2025 +0000" }, "message": "Merge changes from topic \"rfa-related-fixes\"\n\n* changes:\n fix: remove dependency on fixed PSCI version in smc32_fast\n fix: ignore errors on optional General service queries\n fix(psci): mask MBZ bits in PSCI target_cpu arguments\n" }, { "commit": "1dfffbafd2f71cda49f298c08fe8901c9af566f9", "tree": "f33516764de57dd4acc8d31c1516e3ef964ee70e", "parents": [ "d84996abcc2ba42292f223fe880d572b8cea58ef", "04315990a63abb68da3ea135c96b5b1390bf063f" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Sep 17 11:23:15 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 17 11:23:15 2025 +0000" }, "message": "Merge changes from topic \"hm/evlog\"\n\n* changes:\n build(measured-boot)!: move to ext event log lib\n feat(libtl): bump version to get event log funcs\n" }, { "commit": "b1467682a26053428c34eb363ba06391dcbf77eb", "tree": "af2c57fb047817f280270ffa4bb4c275064359b3", "parents": [ "6e191237b069712f613e42592fd08fe326da1ffc" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Thu Aug 28 14:38:36 2025 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Tue Sep 16 14:57:48 2025 +0200" }, "message": "fix(psci): mask MBZ bits in PSCI target_cpu arguments\n\nThe PSCI specification defines the target_cpu values almost the same as\nthe MPIDR_EL1 register value, however it only contains the Aff0-3 fields\nand the rest is declared as MBZ. Mask the MBZ bits to follow the PSCI\nspecification.\n\nChange-Id: I4196b5039aa774b357cb6932d3c2c24060f1f228\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "2fb7522d68553139a45c418bbe74b376b10e8d78", "tree": "687c2b7fa3f9148809d14ac2d0bdf9c38238a5fe", "parents": [ "939c19ed3944643e4caf27c843f086aff1f071c6" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Wed Aug 06 16:26:23 2025 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Tue Sep 16 14:56:38 2025 +0200" }, "message": "feat(psci): accept v1.2 and v1.3 PSCI versions\n\nAdd PSCI version 1.2 and 1.3 to the allowed version list.\n\nChange-Id: I84a3e46112397d4b75ff3a8614a0bfc5f2682f31\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "04315990a63abb68da3ea135c96b5b1390bf063f", "tree": "48d235d6d7cc4f6af7e5d27894dadccbb94649d8", "parents": [ "95a7af102c04cc9cea69fd7b0e6297b63064853a" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Aug 26 13:55:51 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Sep 16 11:38:33 2025 +0000" }, "message": "build(measured-boot)!: move to ext event log lib\n\nRemoves in-tree Event Log library implementation and updates all\nreferences to use the external submodule. Updates include paths,\nMakefile macros, and platform integration logic to link with lib as a\nstatic library. Some of the event log utilities related to firmware\nhandoff have been moved into that library, accordingly bump the version\nof LibTL.\n\nIf you cloned TFTF without the `--recurse-submodules` flag, you can\nensure that this submodule is present by running:\n\n git submodule update --init --recursive\n\nBREAKING-CHANGE: LibEventLog is now included in TFTF as a submodule.\n Please run `git submodule update --init --recursive` if you encounter\n issues after migrating to the latest version of TFTF.\n\nChange-Id: I5c681ab7621c8bcdfc06793a81781af3439964a6\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "95a7af102c04cc9cea69fd7b0e6297b63064853a", "tree": "28a5c49ae404720de4dca11b7f57be13be375057", "parents": [ "6a010a32ac092ff392c34b80179b21e8036731f4" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Aug 28 13:02:44 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Sep 16 11:37:42 2025 +0000" }, "message": "feat(libtl): bump version to get event log funcs\n\nLibTL now provides APIs for handling event logs from a transfer list.\nBump to that version and get rid of existing functions that duplicate\nthat behaviour.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: I4967144657765741b390cf6cda56e08a2da0eadf\n" }, { "commit": "794b0ac8cdb01aa8c5ad630d4592b3743f6782cd", "tree": "9d4bda7de5f2c1640670949c0aa8fb382bc31fee", "parents": [ "aa48358ef9270417897780230bdedb635cc4af56" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Jun 20 13:13:29 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:37:05 2025 +0100" }, "message": "refactor(gic): unify SGI exception data\n\nThe information we pass to exception handlers for SGIs, PPIs, and SPIs\ndoes not differer materially. Unify the handling to use the same types.\n\nSince SGIs are normal IRQs, we can put the last remaining function in\nirq.h to simplify a bit.\n\nChange-Id: I1cf6f8a2a832797a9ce54eeb025a94120f115cf6\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "f41d8eeb88a4759bd463ccbb2e5eac3e6ee7eb2c", "tree": "56b3830820758d600ddb6d138590c4c6aeb60ee4", "parents": [ "735050f270024e5443f1e9bf45e98a4d3954c9d5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Jul 10 16:41:28 2025 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Aug 20 20:01:47 2025 +0000" }, "message": "test(fuzzing): adding variable coverage\n\nAdding the capability to produce coverage of the arguments of the\nSMC calls as generated by the fuzzer. The output from the FVP will\nbe routed to UART3 where a python flow will read the data to create\ntables of each SMC call with its fields shown and values given. The\noption is enabled by adding SMC_FUZZ_VARIABLE_COVERAGE\u003d1 to the\ncorresponding TFTF config.\n\nChange-Id: I2d4d310976aa2c0447efbd8ec0676bb9f8699828\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "aa22f41c438313fe23d42656c1dff8ca56d77524", "tree": "a50ccb99f9389255d0dc158df40e5a0ace067451", "parents": [ "32815d30b1d4b2126cdff5ef9908446e1880d44e" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Wed May 21 13:25:40 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jul 22 10:22:52 2025 +0100" }, "message": "fix(sme): update smcr_el2 after hcr_el2 has taken effect\n\nIf HCR_EL2.E2H resets to 1 and its write to 0 is delayed by the lack of\nisb, then the SMCR_EL2 access will trap as CPTR_EL2.SMEN will dictate\nthe trapping behaviour and we leave it at 0.\n\nWrite hcr_el2 with the other registers so there\u0027s an isb between its\nwrite and the access to smcr_el2.\n\nChange-Id: Ia4f546a070d7f9d5e3cd330979e6587606fffcdf\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "73005a60253c98274a4a1104af0bf75ccca4d205", "tree": "4b377917909b3aeada9b6a23598112b2b63fd145", "parents": [ "b0833d26dacc0fef45e4d695f9e7028a8d20825e" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 10:37:15 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Jul 09 09:08:51 2025 +0000" }, "message": "refactor(lib/pcie): rename macro CHECK_DA_SUPPORT_IN_RMI\n\nRename macro CHECK_DA_SUPPORT_IN_RMI to SKIP_DA_TEST_IF_PREREQS_NOT_MET\nand move it to host_da_helper.h\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ie955e1dcb2edefa0f41edfc36b4b2587cb465a29\n" }, { "commit": "b0833d26dacc0fef45e4d695f9e7028a8d20825e", "tree": "f0902ea53de0d53d4ff4fb3464ea78910ee0ef61", "parents": [ "bbb1305abc89d5b88a4cefe374e05052f27d165c" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jun 26 11:05:51 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:39 2025 +0100" }, "message": "feat(lib/pcie): init pcie device capabilities\n\nAdd additional fields in pcie_dev structure that will be later\nused by DA testcases.\n\nFind and initialize devices extended capabilities.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I32042393dc023d8ac948aa9f4ea921de22ec0b98\n" }, { "commit": "bbb1305abc89d5b88a4cefe374e05052f27d165c", "tree": "914c12b61f6f91da1982b906aa3dd180b911583c", "parents": [ "503b89a6b2d6ecd039401bd7f6f08f0d3cbb69a6" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 24 14:00:06 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:39 2025 +0100" }, "message": "feat(lib/pcie): add dvsec helpers\n\nAdd DVSEC RME DA support and helpers based on RME System\nArchitecture [1].\n\n[1] https://developer.arm.com/documentation/den0129/latest\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I29c2dc3c94fa295c9948f63f57f88e2763326291\n" }, { "commit": "503b89a6b2d6ecd039401bd7f6f08f0d3cbb69a6", "tree": "bf4b3f02eabecec15b63e2c5247eb6085b7c5ce8", "parents": [ "20c2d74e687556c462b49eb1f8a5e3afc21698cb" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jun 19 10:34:11 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:36 2025 +0100" }, "message": "fix(lib/pcie): import pcie enumeration helpers from rmm-acs\n\nImport PCIe enumeration helpers from rmm-acs[1] at tag v1.0_REL0_12.24.\n\nThis patch adds the missing device enumeration logic added as part of\nthe initial commit.\n\nThis change is verified with FVP default PCI topology. The helper\npcie_init() might need some enhancements for other platforms with\ndifferent PCI topology.\n\n[1] https://github.com/ARM-software/cca-rmm-acs\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I46724c458fe0071272fc7bca73d51e27181bb1b4\n" }, { "commit": "51f0333e24e6c4aff44ace871c6042b507476b5e", "tree": "4e7a4c0d34ab7cb3c0039bbd3b59431f646c531c", "parents": [ "cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jun 27 13:47:23 2025 +0000" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jun 27 13:57:23 2025 +0000" }, "message": "revert: replace in-tree Event Log Lib w/ submodule\n\nThis reverts commit cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849.\n\nReason for revert: Causing CI failures\n\nChange-Id: Iad32fb9ba1d32044ef647f01e3091e9b0ee0d9e2\n" }, { "commit": "cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849", "tree": "8be9469773b3f15614ee27ae9539cc29f8692c3c", "parents": [ "68ecce15bcd5db2449700d122f4e8f32cce91ae9" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu May 22 11:08:46 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 24 15:58:15 2025 +0000" }, "message": "refactor: replace in-tree Event Log Lib w/ submodule\n\nThe Event Log Library has been relocated to a separate repository and is\nnow integrated as a submodule, eliminating the need for in-tree files\nand reducing maintenance efforts for TFTF.\n\nChange-Id: I29694f8b3b08bb1d57dd685f6e42dc9f69d241bb\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "68ecce15bcd5db2449700d122f4e8f32cce91ae9", "tree": "4e7a4c0d34ab7cb3c0039bbd3b59431f646c531c", "parents": [ "550d5104ffe85f2f6994ef04a7172627cd76770e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon May 12 12:38:24 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 24 15:58:13 2025 +0000" }, "message": "feat(libtl): integrate Transfer List Library as submodule\n\nReplaces in-tree transfer_list implementation with LibTL submodule.\nRemoves legacy source and headers, updates includes and makefiles\nto use the standalone library. Adds architecture-specific inttypes\nheaders for compatibility.\n\nChange-Id: Iff8272a6417983b9fb8e7f6bde6db44c2a6020f5\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "550d5104ffe85f2f6994ef04a7172627cd76770e", "tree": "f6b0848eb24c2ee151dea1aaf859bf8de038a4e0", "parents": [ "e1a53a699649c263860560a5ac784599c3b289ca" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu May 22 13:09:27 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 24 15:58:13 2025 +0000" }, "message": "refactor: remove dead make command\n\nLibFDT sources are built directly and not via the `MAKE_LIB` utility\nwhich isn\u0027t actually defined in TFTF.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: Ieed18abeade617e741743187fcffa65481b73ed1\n" }, { "commit": "089c9ad705c1f393d95dd911c76a6772af45d1fd", "tree": "1842ee9a2fabfe773b56c98a76bb7e831b26b5a0", "parents": [ "b674809e4d937d44f85ef53aa2bdbb9f74b569b2" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:54 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:37 2025 +0000" }, "message": "feat(handoff): add event log test\n\nAdds a new TFTF test to validate presence and correctness of the TPM\nevent log in the transfer list received from EL3. Uses event_log_dump to\nparse and output log data.\n\nChange-Id: I0b1f782429e4bfe3d1760fce52d40a9836dc27a2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "b674809e4d937d44f85ef53aa2bdbb9f74b569b2", "tree": "3192a0624448d4503cb3679f0d939cb7c169ac22", "parents": [ "19620adc7cbcae26cc432a28a9c3b0944957cf13" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:03 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:25 2025 +0000" }, "message": "feat(measured-boot): add measured boot drivers\n\nIntroduces core measured boot support, including TPM event log handling,\nhashing infrastructure, and event formatting per TCG spec. The driver is\nimported from the existing implementation in TF-A.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: Ib2e6a88c86f110f9a6907c3e6dbb0dc736486de9\n" }, { "commit": "a1709e0063b271f723790ce9f74a6b2afd2760c4", "tree": "a695a04db22a4bbf49be39a4ba665f893d73f3ad", "parents": [ "6d9e106780746a3248901b93f9a334d28eef4e5e" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Apr 07 09:41:26 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Apr 07 16:00:17 2025 +0100" }, "message": "fix(sme): synchronize context before using it\n\nWe need to wait for the write to cptr_el2 to take effect to consider SME\nenabled. Otherwise, the write to smcr_el2 may fault. Add an isb() to\nsynchronize this.\n\nChange-Id: Ib1fb1803bad2d4fb9e89bc4861e2e611b9882b2e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "8808a945590fbc4138c0961717da75ddc383ede0", "tree": "992e6e95734b14bddb4dddc924c19122fccc6f69", "parents": [ "8ac4dd8ce81ba17121c62b4d39925ae6b62d7998" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Jan 07 15:45:39 2025 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 23:05:15 2025 -0600" }, "message": "feat(hob): add boot-time prints for cactus-stmm HOB list\n\nAt boot time, print HOB headers and contents.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ic634f045cacdbc8e318836eba85982a93f55fc0f\n" }, { "commit": "bde3eab2e68bc0059b5ccfc83a13759287eb9cf4", "tree": "90acb838f69c8c620e7790409df205077a8fe65b", "parents": [ "e8a17a905ca1c20acb1b9248ac725ab847bddc42" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Dec 09 14:04:43 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 13:51:36 2025 -0600" }, "message": "feat(hob): add HOB definitions to TFTF\n\nAdd necessary HOB structure definitions and HOB library to TFTF.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I1a81cd99df52436a077a71030244ca642122497a\n" }, { "commit": "c8943ba881807922cb84e357461f5482475a47c3", "tree": "a951dd70d63e29f3616dc48935890f96c8b52fab", "parents": [ "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "message": "Merge changes from topic \"fuzzinit\"\n\n* changes:\n test(fuzz) adding fuzzing for vendor-el3 smccc calls\n test(fuzz) adding fuzzing for all SDEI calls\n test(fuzz): Capability for random inputs\n" }, { "commit": "0fa7d21bf97d14283ebf8c3df866cd05afaff91e", "tree": "b1927aea547dcd718dccc20301cbc301d986faec", "parents": [ "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jun 18 11:17:01 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 14:03:27 2025 -0600" }, "message": "test(fuzz) adding fuzzing for all SDEI calls\n\nadded constraints for all calls\nadded fuzzer feature to start at arbitrary call number\nadded fuzzer features for function exclusion, fuzzer starting/ending call\nworked on additional fuzzing for event_register\n\nChange-Id: I9814b8387ea9e0fb00b53adbdbe0f8429845924e\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "tree": "05125c5f936c21bd2d9cc5915bf9544333182bd9", "parents": [ "079c37c7aaf219182d7061427e22c65aaa416b37", "ff2f1150099940a2767381df1701c9007eec8e68" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "message": "Merge changes from topic \"qemu_tests\"\n\n* changes:\n fix(test): compile error in test_irq_spurious_gicv2.c\n feat(timer): support PPI timer interrupts\n" }, { "commit": "6681b7a6fc142f8b1ba0f97d41d239fe6e874c37", "tree": "ce9e06d8cf11d20bfe42b02034bd2a7a2255f053", "parents": [ "3e9115dc182c6240f9289912b6f528853b510e10" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Nov 01 16:27:44 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jan 27 07:38:50 2025 -0600" }, "message": "fix: skip CPU cycle allocation for SP vCPU to reach message loop\n\nWith the support added in Hafnium SPMC for secondary CPU cold boot,\nsecondary execution contexts of SPs dont need a round of CPU cycles\nthrough ffa_run to reach the message loop.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ib02f51abb31d30329d43f0937ba30d721504bc53\n" }, { "commit": "4e282424143dbd73cd0248d470d03cccb9005f42", "tree": "b5da9ecc48fe84d374c9e04de6a0d3e2c7f8aa0d", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 14:34:13 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:16 2025 +0000" }, "message": "feat: add register definitions needed for SMCCC_ARCH_FEATURE_AVAILABILITY\n\nAlso slightly optimised some redundant feature functions\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I6dcc11060a2f3697a8aa41443e9cfc665b2b7c74\n" }, { "commit": "a4d7972176c2fdc3c66e6ba3347d24f65bac670c", "tree": "ca528cadd776c98afa91e1be5bd5b728b0c51b3c", "parents": [ "963872ed94fc063dc8597dc034ce7e45362e348f", "d1a7f4d2bd6b4867a71366b58b00759724ef99d1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Dec 20 10:03:31 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 20 10:03:31 2024 +0100" }, "message": "Merge \"feat: add tests to check SCTLR2, THE and D128 sysregs\"" }, { "commit": "d1a7f4d2bd6b4867a71366b58b00759724ef99d1", "tree": "7439900358c0026fe7c781e725e6ba0b1c3fd37b", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Tue Nov 26 12:50:47 2024 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 19 14:51:47 2024 +0000" }, "message": "feat: add tests to check SCTLR2, THE and D128 sysregs\n\nThis patch adds test cases for verifying that the system registers of\nFEAT_SCTLR2, FEAT_THE and FEAT_D128 (FEAT_SYSREG128) are working\ncorrectly by performing a series of reads and writes to the registers.\n\nChange-Id: I5c102daa358a7ec5d1801395bc875e9850e83939\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "97dd9c3fe59af613c6dd7404a1f349abce3ec3d2", "tree": "c012e0e20c412bfb51f078c119f30017b7bca277", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Dec 18 10:53:25 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Dec 18 11:00:21 2024 +0100" }, "message": "fix: omit printing an error on mbedtls not cloned\n\nUsing Makefile\u0027s wildcard statement in place of a shell find command to\nprevent the error message below when mbedtls submodule is not cloned:\n\n find: ‘ext/mbedtls/include’: No such file or directory\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I9677aa4e97485b597e00ba0bdf76967f9093afe9\n" }, { "commit": "5929bfe75a40577efa77cf23a2fc4057ced92e7e", "tree": "054341aebc883a57faab006f4d700d596c323203", "parents": [ "67a3ffba147f4a5d996fa5e307fd59389925434e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:28:00 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 18:10:28 2024 +0000" }, "message": "refactor(realm): define PCIe helpers\n\nThis patch refactors the existing PCIe and DOE\nhelpers to define generic helpers to make them\nreusable across more tests.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I56a9f5c59715c7916f3f737ed6d3af94b0e3679f\n" }, { "commit": "23788fa84220f873a21f8bca53d973e240ae8740", "tree": "dd9321d639bd4bc727e416fb15a6ebecf316fd96", "parents": [ "c5f75b914824a6c3cb992596b44f1c2a116eb7d3" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 12:19:32 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 17:11:28 2024 +0200" }, "message": "feat(lib): add mbedtls support\n\nAdd support for compiling Mbed TLS from external source.\n\nThe Mbed TLS library is compiled from source pointed by MBEDTLS_DIR\nenvironment variable. Any TFTF test that includes mbedtls.mk will have\nsupport for mbedtls library. Note that by default the MBEDTLS_DIR will\npoint to the default submodule directory (ext/mbedtls).\n\nThis support is added for testing RMM capabilities related to\nDevice Assignment in RMM.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I0e386334078812e5ff5bdcffd4143732e0478b64\n" }, { "commit": "2c2810f79e57e78d77899084b5439cbdd1aaa464", "tree": "5d5644927acc2f4a212ba18558c7ed57f3d1e07c", "parents": [ "ea43ac0daef913576cf214454cf81482d8cf109a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 15 17:11:24 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 05:21:39 2024 +0200" }, "message": "fix(realm): make PCIe tests default for testing\n\nThis patch moves the PCIe DOE test to the default realm world\ntestsuite.\n\nAlso fixes some build issues and hardens the PCIe functions.\n\nNote that FVP_Base_RevC model needs to have the following\noptions enabled for the PCIe tests to work :\n\n -C pci.pcie_rc.ahci0.endpoint.doe_supported\u003d1\n -C pci.pcie_rc.ahci0.endpoint.ide_supported\u003d1\n\n\nChange-Id: Icfd6b68799b0bacb44299c6a3cf99a3c425f833d\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "c79338af9a3e9cb24b90afd79491c85b7ef11d72", "tree": "bcf79e2a50a9e49bdfbae09e71fd4176c717bc7d", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Oct 28 18:48:25 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Tue Nov 19 09:06:55 2024 -0600" }, "message": "feat(smc): support SMC calls with no ret vals in x8\n\nThe current implementation of the SMC library assumes that x8\ncontains the address of an smc_ret_values structure. Although\nthis can be convenient, it prevents from using registers x8-x17\nas arguments, since it assumes there is an address in x8.\n\nThis patch implements an alternative API for SMC calls, allowing\nthe use of registers x1-x17 as input arguments and the use of\nregisters x0-x17 as output arguments without assuming a pointer\nin x8.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I0016116b8d2ee4ef5aac9473f31e38434cda4943\n" }, { "commit": "46d0228e2a1a17c57be8f5011f183ea28e6ba518", "tree": "ce322be37116651bf3ab1d681632c176f8105233", "parents": [ "7c78f7b4a74e58512ff6998f7a5438520e58c343" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Nov 18 16:58:37 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Nov 19 11:22:08 2024 +0100" }, "message": "fix(serror): use custom argument for incrementing elr_elx\n\nAdd a custom argument to increment the elr_elx after handling SError.\nIn some cases, to prevent re-triggering the instruction, ELR needs\nto be incremented by 4. In other cases, it may not be necessary.\n\nThis argument is passed to the handler, which then decides whether\nto increment elr_elx by setting the passed argument accordingly after\nhandling the SError.\n\nChange-Id: I404f3c5e24f894502a8d00c73649be0b2dd540fa\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "7c78f7b4a74e58512ff6998f7a5438520e58c343", "tree": "ea7bd3a6363d1bf5686e5cfbd2a92cabec7a3df6", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Oct 25 11:44:32 2024 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Nov 19 10:10:16 2024 +0000" }, "message": "feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n\nWhen FEAT_DoubleFault2 is supported, TF-RMM must take into\naccount bit SCTLR2_EL1.EASE in order to decide whether to inject\na SEA into the sync exception vector or into the serror one.\n\nThe test on this patch verifies that TF-RMM injects the SEA\nto the right vector depending on SCTLR2.EASE bit.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c976fecb04d123e3efb96c5973b1466e241097f\n" }, { "commit": "5a44078f017c581c9def5cfd697f0579fc6ff89c", "tree": "4d63ddf377e00735bcbb1d5fdacc1885f8401377", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Tue Jun 25 12:36:20 2024 +0200" }, "committer": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Fri Nov 15 09:06:21 2024 +0100" }, "message": "feat(timer): support PPI timer interrupts\n\nAdd support for timers that use a PPI as timer interrupt. A new\nfunction, tftf_initialise_timer_secondary_core(), is added to initialize\nthe PPI on the secondary CPUs from tftf_warm_boot_main().\n\nChange-Id: Ia343ce10b0b51e72b9e520b1fab0ea7ba0a43f2c\nSigned-off-by: Jens Wiklander \u003cjens.wiklander@linaro.org\u003e\n" }, { "commit": "4b67210c4ae32e723fc5805f3b7e8c48fb8ec962", "tree": "b5d66c48a39a422a902364d694a41521c35de431", "parents": [ "0db4a3cdde090a94721a8a598cbbbf857f7cf47f" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Sep 23 13:06:15 2024 +0200" }, "committer": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Fri Nov 08 17:48:28 2024 +0100" }, "message": "feat(cm): add test to validate EL2 regs during context switch\n\nVerify that EL2 system registers are preserved when switching\nfrom Normal world to Secure world and vice versa. Do this by\nmodifying the live EL2 register state and dumping it to memory,\nthen performing an FF-A Cactus call and checking whether the\nstate matches the previously saved context.\n\nChange-Id: I0537b4d671c72c0a2fd29ac7e218bf69e1c66001\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "86e5e5d500a839920edcf71783f31b7e4fc20c42", "tree": "c9b96514811730ade3be4cd5449254025502fb07", "parents": [ "af49307617a6861c13008371a1e5397b278bb4c7" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Aug 05 19:52:29 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 16:52:38 2024 +0000" }, "message": "feat(cm): add tests to validate EL1 regs during context switch\n\n* This patch adds a test to verify the integrity of the el1_context\n registers across world-switch.\n\n* It aims at testing the save and restore functionality provided\n by the EL3 context management library.\n\n* It validates the EL1 ctx register entries after interaction with\n TSP (S-EL1) software.\n\nChange-Id: Id435d9d7699231d66e9e7acdbb3459ec439d2aef\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "9f2de630d5d2472e8ec7348507e343738934940d", "tree": "4905c2ec19086fbdecde033abd1f2f766d98f692", "parents": [ "36ed009a073c64a422c769b46eede6538fa42667" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 11:48:22 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 13 18:20:18 2024 +0200" }, "message": "feat(doe): add PCIe DOE tests\n\nThis patch adds PCIe DOE tests for\n- DOE discovery protocol\n- SPDM get version\nTo build this test suite use \u0027TEST\u003dpcie-doe\u0027\noption.\n\nThe spdm.h is imported from https://github.com/DMTF/libspdm\nproject.\n\nChange-Id: I8db1048d01b4f8061d8a4ddccc198159ed61e6b7\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "9f0dc01f4d4f6f1800e86c4c6f1e8377e119a713", "tree": "119dc2ce7fa5fe4807fc535ea0dfc1275af2fedb", "parents": [ "31a6f6499c5e558a9ef13ff53922f031d18a48b9" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:22:06 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Sep 10 10:22:06 2024 +0100" }, "message": "feat(pcie): add PCIe DOE library\n\nThis patch adds PCIe DOE library source files.\n\nChange-Id: Ic2ab11afa0438d74c53cb157a63caada7457d77e\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "6043eaf8e2aad4727f6e3f7199e88b59787d3ad4", "tree": "0bef58a1a1ac541c6d73fe59773d8f9701f87f93", "parents": [ "277925bbfc6bd1caf47f573dd17569b9a30d7844" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Mar 08 14:14:12 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:22:31 2024 +0200" }, "message": "feat(spm): probe SVL for SME related tests\n\nFor world switch SPM tests checking the SME context, probe the possible\nSVL values in streaming SVE and run tests with each possible SVL.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I5157fc896168f7ea2df131a86acdb1d1f1bb795e\n" }, { "commit": "c3cf2daed819a9d01feba31832544309c9da8d70", "tree": "d47120e316a97ea94409e1a61594ec6da1f5a71b", "parents": [ "caff038b3f0b261b1fcc14f7918a80fa515202c1" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Apr 01 13:57:19 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri May 10 13:40:04 2024 -0500" }, "message": "feat(amu): test AMU counter restriction (RAZ)\n\nWhen using AMU counters, there is risk of exposing information to\nlower exception levels. In order to prevent this, counters are\nrestricted, so they are read as zero (RAZ) at a lower EL. This\ntest verifies that counters are read as zero after forcing counting\nthrough instructions that trigger MPMM \"gear shifting\" (e.g.: by\nexecuting SVE instructions).\n\nNote: This test applies to TC2 only, as it is the only platform that\n supports MPMM currently.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ic32ba19fa489cf479947d4467ddb84e6abd1b454\n" }, { "commit": "e538be68f9635e3919184b0ed307d40c7a00362e", "tree": "0523e57e331f29106a8e78149674fe9a6979d562", "parents": [ "dfc4d7f46fb95441443066f60d1b855f7ef9c364" ], "author": { "name": "Jing Han", "email": "jing.han@arm.com", "time": "Wed Apr 17 13:39:10 2024 +0000" }, "committer": { "name": "Jing Han", "email": "jing.han@arm.com", "time": "Tue May 07 12:54:19 2024 +0000" }, "message": "fix(lib): save and restore smcr_el2 when cpu suspend and resume\n\nChange-Id: I0c0f054e025eaafeebbe0adb5d0699def5c4fc60\nSigned-off-by: Jing Han \u003cjing.han@arm.com\u003e\n" }, { "commit": "21a30ed1ae35a8b32d23e96cdc143702a27bda90", "tree": "bd1d61a86ff59e96c33a98a036e542f43ce185df", "parents": [ "a8deec5c0b51719b1f268e4f106c3a095a387074" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Sat Jan 13 23:07:43 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Feb 14 12:51:31 2024 +0100" }, "message": "test(realm): test realm pauth state is preserved\n\nModify Pauth lib to work for multiple CPU\nTest if Realm pauth state is preserved for all RECs\non context switch to RMM/NS.\n\nChange-Id: Ibb393b415bab27066289b560be49e02d0c8f58ba\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "417edcad3eb332eca5d7ed70de51cac489a2dca4", "tree": "520dcd978d3d12003560fd56a66e1c0117521514", "parents": [ "bbf08c50aca569e517a52d2216c42e7244769a5e" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Sep 05 17:44:24 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Nov 30 16:27:24 2023 +0000" }, "message": "feat(smc): add SMCCCv1.3 sve hint bit support in tftf framework\n\nTFTF smc library uses SVE field in trap register to represent SVE\nhint flag.\n\nTestcase has to explicitly set this bit using the helper routine\ntftf_smc_set_sve_hint(). When set to true, denotes absence of SVE\nspecific live state on the CPU that implements SVE. Once set to true,\nSVE will be disabled in trap register and any SMC made using tftf_smc()\nwill set FUNCID_SVE_HINT in the SMC function ID.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I13055fe4102cc4e35af1d7091e88327a21778835\n" }, { "commit": "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581", "tree": "3e0552b2dae1f333abe34bddd7a4ea63c40f985f", "parents": [ "47b702c49a622e895d70104d78a20bb979dae229" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 06 16:31:19 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "feat(sme): add sme helper routines and add streaming sve support\n\nThis patch adds a few helper routines to set the Streaming SVE vector\nlength (SVL) in the SMCR_EL2 register, to enable/disable FEAT_SME_FA64\nand to get CPU\u0027s Streaming SVE mode status.\n\nThis patch also makes SVE compare routines compatible for both normal\nSVE and streaming SVE mode.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7294bb17a85de395a321e99241704066662c90e8\n" }, { "commit": "47b702c49a622e895d70104d78a20bb979dae229", "tree": "0d8eb64935c78a960998a4163c996f418c0fd96b", "parents": [ "92f1868013792ac13497d1045078b7e8a12d4f02" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 06 13:31:46 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "fix(sme): use rdsvl instead of rdvl\n\nUse rdsvl instruction to get Streaming SVE vector length instead of rdvl\ninstruction. When the CPU is in Streaming SVE mode both rdvl and rdsvl\ninstruction returns the same value but that is not true when the CPU is\nin Normal SVE mode. So it\u0027s preferred to use rdsvl to get SVL.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ieb6226f4fc275ee8a81eb359af465c26e307bc75\n" }, { "commit": "92f1868013792ac13497d1045078b7e8a12d4f02", "tree": "c94edb176be497ef790dfeaf98bb7b1e49cef824", "parents": [ "3dc2d746aa4bc44174a9981fa082c1473d0006a4" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Sat Sep 02 01:41:28 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "fix(sme): enable SME/SME2 during arch init\n\nThis change enables SME/SME2 for nonsecure use at EL2 for TFTF cases\nduring arch_setup. This removes dependency on testcases to explicitly\ncall sme_enable or sme2_enable to access SME or SME2 functionality.\n\nThis change also adds CPTR_EL2 register in suspend context. CPTR_EL2\nregister is saved/restored in CPU suspend entry/exit path.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2c99fd49c48c1a9ff2110747714db858a78d3a32\n" }, { "commit": "ab2fe6b01abef3c4b17ffb2c6ee4759f6801e095", "tree": "8285b1a38265e0fa5dd691874d8bf0cdd58aa93f", "parents": [ "406e19135f9fe88bb7794c60012759ca3fb3bdc8", "6e011646ae828f789fc8643e0e6a0c225130cd0c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 27 15:46:09 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 27 15:46:09 2023 +0200" }, "message": "Merge \"feat(handoff): add basic firmware handoff tests\"" }, { "commit": "6e011646ae828f789fc8643e0e6a0c225130cd0c", "tree": "d82ffdaee70f155372aac8519e8244d37f510a6f", "parents": [ "cdf525212326f8b453f22122dddc9d8bf0725981" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Sep 22 17:17:35 2023 +0100" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Oct 27 11:00:34 2023 +0100" }, "message": "feat(handoff): add basic firmware handoff tests\n\nAdd tests to sanity check information shared between BL31 and NS world\nusing the firmware handoff framework.\n\nChange-Id: I9d00292db7732157d0815e6159438c0db08551ad\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "fa05bd9ea226541e860789443b8f68f8d8846390", "tree": "e63b0399f570e205112b27f7fd92b3d26cbb1a74", "parents": [ "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 14:36:53 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 15:07:14 2023 +0100" }, "message": "feat(sve): add helper routines to read, write, compare SVE registers\n\nAdd helper routines to read, write, write_rand and compare SVE\nZ, P, FFR registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to configure SVE vector length and\nhas to pass memory to read/write SVE registers.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I3fa064c76a498ee2348d92cba2544a6e50331e15\n" }, { "commit": "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045", "tree": "68f9b32383bb80a3542368ebe9ffc15e4bba1c43", "parents": [ "035899729133080ffff3ed691ba65664c34f75ca" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 13:27:36 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:24:42 2023 +0100" }, "message": "feat(fpu): add helper routines to read, write, compare FPU registers\n\nAdd helper routines to read, write, write_rand and compare FPU state\nand FPU control/status registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to pass memory to read/write FPU\nregisters.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I10ae5487c9f58e46434c1bd5b42fd458ec755045\n" }, { "commit": "035899729133080ffff3ed691ba65664c34f75ca", "tree": "02a0b07c127329297d5c28e0683352357c8c0d8a", "parents": [ "73949a20b61def813b3265c2a6a330656bd001af" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 11:04:51 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:15:59 2023 +0100" }, "message": "fix(sve): represent sve Z0-31 registers as array of bytes\n\nCurrently each Z register is type defined as sve_vector_t but the helper\nroutine to write or read Z registers works based on current vector\nlength.\n\nIf test case defines \u0027sve_vector_t zregs[32]\u0027 and reads all Z registers\nusing sve_read_vector_regs() then zregs[n] might not corresponds to Zn\nregister unless the vector length is set to max value.\n\nThis patch also renames sve_vector_length_get() to sve_rdvl_1()\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I42955f8009bdd7f40d74c5a8d21d7c16ce6d761e\n" }, { "commit": "fe69a8c4846c20c06efe945c2c6b1f9e893347fa", "tree": "5d57bc467fee1ad54c3960d1e2b43b035dd665a6", "parents": [ "2f13adbc1ac240bdee4c901cbd0e09119f17fce4" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Aug 21 11:49:32 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 16 18:36:39 2023 +0200" }, "message": "fix(AArch64): Fix issue in processing dynamic relocations\n\nFixes issue in processing dynamic relocations, when\nrelocation entries not matching R_AARCH64_RELATIVE type are found.\nLinker might generate entries of relocation type R_AARCH64_NONE\n(code 0), which should be ignored to make the code boot.\nSimilar fix done in TF-A (db9736e3d86d7098f9785a9db834746a8b2ed335)\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ibc769efa322618f59c05a6b1596555fc1b00b57b\n" }, { "commit": "9d0cfe88aedc34f1b61a51ff18013743c56e2fbc", "tree": "b5b65d1a477d3d46aacfb69bd3dff348a2136ce4", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Apr 17 10:57:26 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Jul 25 17:00:33 2023 +0100" }, "message": "test(tftf): test PAuth in Realm\n\n- Enable PAuth in Realm RL1 by default.\n- Check if PAuth keys are accessible in Realm RL1.\n- Check if Realm PAuth keys are preserved across RMM entry/exit.\n- Check if NS PAuth keys are preserved across RMM entry/exit.\n- Generate PAuth fault by cloberring LR.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I85d8e03ec604c96117555e7aa866453cb2745cfe\n" }, { "commit": "eb29954598e54549a45d15eeee06b7213022c277", "tree": "673285b503346bbf3a88b3806f6d9d16ec982277", "parents": [ "35d5fe4ad5242d69d8911b57a842a77ec69f0dfa" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 19 10:59:58 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 20 21:52:56 2023 +0100" }, "message": "fix(fpu): write random value to fpsr/fpcr instead of read\n\nThe inline assembly code to write random values to FPSR and FPCR,\nactually does a read. This zero out the random value that is used as a\ntemplate to fill FPU [Q0-Q31] registers.\n\nWhen this helper routine is used by Non-secure, SP or Realm context\nthe FPU state written to the registers is always zero. The test cases\nthat verifies whether the FPU state is preserved across the world switch\nmight PASS always as it works with an empty FPU state.\n\nThis fix also changes fpu_state_print() to print the content of Q0-Q31\nregisters instead of the address.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7bc2deba034b9bb4b6c1b15fe91f4562fd64d8f0\n" }, { "commit": "d648077f8284ada21b03871ce06bf568a2333bbd", "tree": "b2307d260395753bd714732500f51cd1f307f1ff", "parents": [ "baed8dd3577633768837048cb71351fb135d59ee" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Feb 27 13:23:06 2023 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 13 13:58:31 2023 +0200" }, "message": "feat: introduce SError exception handler\n\nIntroduce SError exception handler along with support to register a\ncustom handler. The default behaviour is same as before if no handler\nis registered.\nThis patch will allow tests to do a graceful exit after handling an\nSError.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Idbe37d3690e3a8e08fa3b0dff496d18d3022a8fc\n" }, { "commit": "2a32ff7161ef8711f9e7420c499a246e3d055f42", "tree": "041037f8c7b3126163c8988fd8041712da8447ff", "parents": [ "ec59c59afc953c306a4b83e919a787694ee6a88f" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu May 25 17:51:48 2023 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Jun 06 11:00:21 2023 +0100" }, "message": "feat(xlat): add support for 52 bit PA size with 4KB granularity\n\nThis patch adds support to the xlat library to for 52Bits of\nPA size with 4KB granularity (FEAT_LPA2). The patch only reports\nthe right granularity when it supports FEAT_LPA2 and it does\nnot enable the feature.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Iee0cab8e1f8844a6af135771d8f940ec7e1dce84\n" }, { "commit": "d179ddcc64cac3b319b301cfe6c1bc32c1ea0eaf", "tree": "f7ff4f156a0bf64c0f186e057dea7243ecc3ab8c", "parents": [ "0bbdc2dff449036aa65e4c53cd351d01484e0d23" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 12 10:41:42 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed May 24 13:40:39 2023 +0100" }, "message": "refactor(sve): move sve operations to a lib routine\n\nThis patch moves the SVE subtract operation to a common sve library\nroutine and takes a callback function that does the world switch while\nSVE operations are done in a loop.\n\nThe callback is invoked after z0, z1 vectors are loaded and before\nthe calculated results are stored back in the vector registers.\n\nThis refactoring later helps to use this function to do context switch\nfrom NS to Secure world or from NS to Realm world based on the\ncallback type.\n\nThis patch also moves the SVE fill vector registers, read vector\nregisters to a common sve library routine.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Iceb34b96fa85597be63a50c429ae0eb29f8fcaf8\n" }, { "commit": "0bbdc2dff449036aa65e4c53cd351d01484e0d23", "tree": "60f35abe7f72ade6409b3ffcd46262502a9b6885", "parents": [ "ed7cdc8b28137ab15d9f263825674d156b3c2b30" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 05 15:30:18 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu May 18 16:08:39 2023 +0100" }, "message": "feat(rme): add SVE Realm tests\n\nVerifies Realm with SVE support. Below tests are added\n- Check whether RMI features reports proper SVE VL\n- Create SVE Realm and check rdvl result\n- Create SVE Realm with invalid VL and check if it fails\n- Create SVE Realm and test ID registers\n- Create non SVE Realm and test ID registers\n- Create SVE Realm and probe all supported VLs\n- Check RMM preserves NS ZCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I98a20f34ce72c7c1a353ed13678870168fa27c48\n" }, { "commit": "073842171ae9d91b3bdc2031905faafabc7abe57", "tree": "d1b64e32752d2bd8ca31004cb2ee7955f4b7d6ad", "parents": [ "83fe74900c440b2728c458efd8b1c57be20ba039" ], "author": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Mon Nov 28 13:19:11 2022 -0600" }, "committer": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Mon May 08 18:19:04 2023 -0500" }, "message": "Add tests for Errata management firmware interface.\n\nAdd tests to confirm that the em_version, em_features and\nem_cpu_erratum_features calls conform to the errata abi spec.\n\nSigned-off-by: Sona Mathew \u003cSonaRebecca.Mathew@arm.com\u003e\nChange-Id: I8395026acc004a10d8c2c17ec689f4e0752143d8\n" }, { "commit": "38133fa69bfefab6e3d1d7461b42c806d36ae33b", "tree": "3a4ff89fad7a2c24f9d61c1cf28e0d073310ea05", "parents": [ "27479ee85d80268db99f77eea033a691a0bfda56" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Apr 19 17:00:38 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri May 05 13:55:50 2023 +0100" }, "message": "refactor(tftf): move SIMD/FPU save/restore routine to common lib\n\n- Move FPU routines to common lib\n- FPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers\n- Test that FPU/SIMD state are preserved during a context switch\n between secure/non-secure.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I88f0a9f716aafdd634c4eae5b885f839bb3deb00\n" }, { "commit": "95d5d2764c2f44b06af709dd093e9ff0f17ced14", "tree": "b0d3d8d67c94521b107522dac8631e13bc90b9f8", "parents": [ "b3ffd3c17ea83c48a90d7165ab5c5140540bc81f" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Jan 16 17:58:47 2023 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Apr 28 00:51:01 2023 +0100" }, "message": "feat(sme): add basic SME2 tests\n\nFEAT_SME2 introduces an architectural register ZT0 to support\nlookup table feature. This patch ensures that EL3 has\nproperly enabled the SME2 for use at lower exception levels,\nthereby disabling the traps execution at lower exception levels,\nwhen instructions access ZT0 register to EL3.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I46d51184b74c1e82c88344530601f2a3c1aee8ea\n" }, { "commit": "b3ffd3c17ea83c48a90d7165ab5c5140540bc81f", "tree": "ae9e356822c85c2d410e761150dcc5fdce6ddb09", "parents": [ "d6325a6dee06c281d90e875bc5df2ca4fba9d7f5" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Feb 13 12:15:11 2023 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Apr 28 00:50:50 2023 +0100" }, "message": "feat(sme): update sme/mortlach tests\n\nFEAT_SME is an optional architectural extension from v9.2.\nPreviously due to the lack of support in toolchain, testing\nSME instructions were overlooked and minimal tests were added.\n\nThis patch addresses them, with additional tests to test\nthe SME instructions. In order to avoid toolchain requirements\nwe manually encode the instructions for accessing ZA array.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: Ia9edd2711d548757b96495498bf9d47b9db68a09\n" }, { "commit": "cb88add07daff59486f850be6b4cd4750f94d97c", "tree": "3737ad2a8a2aa4c4d9e8d4eea54720009ca4e94a", "parents": [ "e0400c6d2b0372d742cd2cda9aaa7c5cf4741c4a" ], "author": { "name": "Wing Li", "email": "wingers@google.com", "time": "Sat Oct 29 02:32:06 2022 +0100" }, "committer": { "name": "Wing Li", "email": "wingers@google.com", "time": "Thu Mar 23 19:37:52 2023 -0700" }, "message": "test(psci): add tests for OS-initiated mode\n\nChange-Id: I33e135f659aea600f71e053ac3db57eb0172e22b\nSigned-off-by: Wing Li \u003cwingers@google.com\u003e\n" }, { "commit": "40777f82efb1854ab815f501059ac58430cba888", "tree": "349cef469973eb41ef7a58e914baeb57a67d5284", "parents": [ "f7b3be91ab954c495912fc7bc48383cd83bfec2d" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Nov 09 10:15:28 2022 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Nov 22 13:36:28 2022 +0100" }, "message": "refactor: remove deprecated spm libs and test code\n\nRemove references to former SPCI/SPRT implementation pre-dating now\nreleased FF-A specification.\nRemove the sample quark partition image based on those deprecated\nspecifications.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I5b4e51457307c4ff5befd46132fd26d4ef21cdfa\n" }, { "commit": "002e569021f2e219456d02dfe239218eba5c7cfa", "tree": "4c2ea2d7cce38d168ce5e03849498161d537f1c2", "parents": [ "0fcfd47a5936180b754819ee928e8d5af173c5d2" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Mon Oct 10 12:36:46 2022 +0100" }, "committer": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Tue Nov 08 16:34:01 2022 +0000" }, "message": "feat: tftf realm extension\n\nThis patch adds Realm payload management capabilities to TFTF\nto act as a NS Host, it includes creation and destruction of a Realm,\nmapping of protected data and creation of all needed RTT levels,\nsharing of NS memory buffer from Host to Realm by mapping of\nunprotected IPA, create REC and auxiliary granules, exit Realm\nusing RSI_HOST_CALL ABI.\n\nOlder realm_payload name is used now for only R-EL1 test cases,\nRMI and SPM test cases have been moved to new file tests-rmi-spm.\n\nNew TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk,\nas an offset from where R-EL1 payload memory resources start.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7\n" }, { "commit": "d3749b08d49a6cb4fd69e66da1e405dbbd3de57f", "tree": "ba6fa7fa5bbf622dd54281668f885ceaa9091f53", "parents": [ "0091af97592d9cd036a4b70433b70ac9c0ed22b0" ], "author": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Fri Jan 14 15:44:45 2022 +0100" }, "committer": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Fri Mar 25 10:54:00 2022 +0100" }, "message": "fix(plat/arm/fvp): make address space configurable\n\nMake FVP physical/virtual address space sizes configurable, with\ndefault at 34-bit (previously hard-coded value).\nMaximum tested value is 48-bit, FVP interconnect doesn\u0027t yet support\n52-bit PA.\nIncrease MAX_XLAT_TABLE and consequently NS_BL1U_RW_SIZE and\nNS_BLU2_LIMIT to accommodate the increased translation tables (based\non 48-bit max PA size).\n\nCustom PA size is passed to build system through the PA_SIZE define.\n\nFVP needs to be configured in a compatible way through the parameters:\n* cluster0.PA_SIZE, for each cluster;\n* bp.dram_size, setting a memory limit corresponding at least to\n PA_SIZE;\n* cci550.addr_width, interconnect address width should match PA_SIZE;\n* pci.pci_smmuv3.mmu.SMMU_IDR5, SMMU has to be configured as well if\n present.\n\nChange-Id: I57bc898fb2c9696c01fc8e20d00b4a3d09e22326\nSigned-off-by: Federico Recanati \u003cfederico.recanati@arm.com\u003e\n" }, { "commit": "c8f6a6769694c1aed3ba01d649126168f4385eec", "tree": "5ed7b4995dde50cf2f1808598832ae1bb57f89ae", "parents": [ "a7ccb402229b3b9419ec17f311576ffdf1e037b7" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 13 13:44:53 2022 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 09 15:34:05 2022 +0000" }, "message": "feat(tftf): introduce handler for synchronous exceptions\n\nIntroduce a handler for synchronous exceptions (for aarch64) which\ncurrently is treated as unhandled exception.\n\nAlso, added the capability to allow registering a custom handler by tftf\nframework to allow graceful exit while doing negative tests.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I4d8d1f5af9951edfe8f068ce85f7d434b2ec070f\n" }, { "commit": "50ccb55f7782e2b5c3c551abc8a5e26e05e5bc36", "tree": "f1add8aaa13d17471448bcc888551783ee31140b", "parents": [ "2e861262afc341212f2b208ff2da2137a810056e" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Tue Nov 10 19:22:13 2020 -0600" }, "committer": { "name": "John", "email": "john.powell@arm.com", "time": "Fri Dec 10 01:15:27 2021 +0100" }, "message": "feat(sme): add basic SME tests\n\nThis test enters streaming mode and iterates through supported SME\nvector lengths to ensure that EL3 has properly enabled SME for use at\nlower non-secure ELs. If FA64 is present, it attempts to execute an\nillegal instruction.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Ic80a1e5652a88261524778329d3bc99901a799d8\n" }, { "commit": "9f1952c9b7fe5b3f422e53bd7c1038fcd5764b2d", "tree": "bcfddb9641c785d3a5e00703e2cf586ab775619c", "parents": [ "08798acfce407339bc4433c095c6b3a5da31e12a" ], "author": { "name": "Ruari Phipps", "email": "ruari.phipps@arm.com", "time": "Mon Aug 24 11:32:32 2020 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jun 18 16:34:56 2021 +0100" }, "message": "SPM: Add shim layer to Ivy partition and enable PIE\n\nAdd a shim layer that runs at S-EL1 to the Ivy partition.\nAlso enable Ivy to be built with PIE.\n\nSigned-off-by: Ruari Phipps \u003cruari.phipps@arm.com\u003e\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: I821a8ac99d07200aec93ca29d182f8ab6716616c\n" }, { "commit": "08798acfce407339bc4433c095c6b3a5da31e12a", "tree": "8d3eea3f3022762780dc1f5def7375a3669a8cb3", "parents": [ "e3cfd6df27e46c17f514baab275f0a6209aecb44" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Apr 06 14:30:19 2021 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jun 18 16:34:56 2021 +0100" }, "message": "Change vector_entry names to match tftf code style\n\nChange the exception vector names from CamelCase to lowercase with\nunderscores to better match the tftf code style.\n\nChange-Id: Ieffc54edc12cf960af8bca1de36848e7e607d4a2\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\n" }, { "commit": "c4f3eee9634e214eb95a98c829a7617328ce02e5", "tree": "a0cfd90091ba48e8fe4e8c2548d6aa2812c9f3c7", "parents": [ "e30228aebedda69f3de8d43a9f2afdec4c384e3e" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Tue Jun 23 15:25:05 2020 -0500" }, "committer": { "name": "Zelalem", "email": "zelalem.aweke@arm.com", "time": "Mon Mar 08 15:47:11 2021 -0600" }, "message": "Add tests for TRNG SMCs\n\nThis adds some tests that are valid for all TRNG implemenations.\nSpecifically, it tests that the Version, Features, and RND calls conform\nto the spec. Note that UUID is omitted from testing as there is not a\nvalue that it can return that\u0027s outside of the spec.\n\nChange-Id: I68aa2673538f64d2a9401415b8d0de1fdedc3ad4\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\nSigned-off-by: Zelalem Aweke \u003czelalem.aweke@arm.com\u003e\n" }, { "commit": "b7d752a1006a6f7965023cb22b271ab161ca7e83", "tree": "166fdc121f32f595bf247c6e3659f789634b8719", "parents": [ "c078faa139387484a5edaa67b40e61114aac8cf1" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Thu Oct 08 17:29:11 2020 -0500" }, "committer": { "name": "John", "email": "john.powell@arm.com", "time": "Tue Mar 02 21:14:59 2021 +0100" }, "message": "TFTF tests for v8.6 AMU enhancements (FEAT_AMUv1p1)\n\nNot much can be done with the new AMU offsets running at EL2 (virtual\noffsets apply at EL0 and EL1) but we can make sure they are being saved\nand restored properly, so that\u0027s what this patch does.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I5aef85021e875be2109bb9bd7cdbdbe31580394e\n" }, { "commit": "e7810b57c8e671f3b10f7dc901ac3712109564e9", "tree": "971eaeeae533ac6d4605bb26948c1d641e8a7a06", "parents": [ "12c20464817a98348b06069c75a3cfe4dbc6f85d" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Jun 03 15:46:55 2020 -0500" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Oct 19 11:22:34 2020 +0000" }, "message": "SMC fuzzing module integration.\n\nThis includes one test with one seed as\nthe initial implementation. A future upgrade will include an enhanced\nseeding strategy. The patch includes an example device tree file with\nthe actual test (sdei.dts) leveraging the SDEI functions that can be called\nwithout reference to system state. Platform CI will have a single\nTFTF config to be used in all future testing. Once both branches\nof TFA tests and platform CI are checked in a user can invoke the\ntesting with:\n\nworkspace\u003d\u003cworkspace location\u003e test_groups\u003dfvp-aarch64-sdei,fvp-smcfuzzing:fvp-tftf-fip.tftf-aemv8a test_run\u003d1 bin_mode\u003ddebug retain_paths\u003d1 ./platform-ci/script/run_local_ci.sh\n\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\nChange-Id: Ic290e7255bcfd845c0d22037e0b670a6691541df\n" }, { "commit": "953ec59b3ed74380c690e550c85eefe19b07716f", "tree": "2293a7fcfa63ed11dd88b4bb65e1249f9052c79b", "parents": [ "56c3942b4eaa2ad85749b11d5895fad6bfb5b61c", "7fac162cd9439783ef60aaf266d22ad454445ace" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 18 14:55:16 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 18 14:55:16 2020 +0000" }, "message": "Merge changes from topic \"af/add_branch_protection_makefiles\"\n\n* changes:\n TFTF: Add ARMv8.5 BTI support in makefiles\n TFTF: Add ARMv8.5 BTI support in xlat_tables_v2 library\n TFTF: Add ARMv8.5 BTI support in assembler files\n TFTF: Add ARMv8.5 BTI-related definitions\n" }, { "commit": "d6fdb6b10147038d99643a7547821c3cff76ce76", "tree": "dd15b765586801ebfaefd26a9c3883343f16a93b", "parents": [ "45ada40c895b1087de08c05d6d6a311cb0f47c79" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 17 19:13:42 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Aug 18 14:52:44 2020 +0000" }, "message": "TFTF: Add ARMv8.5 BTI support in xlat_tables_v2 library\n\nThis patch adds BTI-related changes in xlat_tables_v2 library\nwhich fully correspond to those in TF-A source tree.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I77f3ae7e9a365406ebb3edd500dbc71d3f07ecad\n" }, { "commit": "45ada40c895b1087de08c05d6d6a311cb0f47c79", "tree": "65a33e6efec3a2a0bb62d548bb76b876a9653cb1", "parents": [ "9cd75024bf2d3abb4e620f308d26876ee75c1c01" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 17 19:07:11 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Aug 18 14:52:39 2020 +0000" }, "message": "TFTF: Add ARMv8.5 BTI support in assembler files\n\nThis patch adds BTI support in assembler files\nwhich fully correspond to those in TF-A source tree.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ie6a7b248c967684c6b2b86b915f0499fe095bba3\n" }, { "commit": "86c3e442ab0a53ed10f433153f68f93830687bc6", "tree": "1e8456f80c2b0a5db69abd07284418085bbb4ca7", "parents": [ "ec87d759429e9496947aa917e012f85e98d9d5fa" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Jul 17 17:03:25 2020 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jul 23 12:57:40 2020 +0100" }, "message": "TFTF: Fix Aarch32 zeromem() function\n\nThis patch fixes the following bugs in zeromem() Aarch32 variant:\n- Removed ASM_ASSERT for length parameter passed in R1 register.\n This is causing assertion in tftf_entrypoint() code\n \tldr\tr0, \u003d__BSS_START__\n\tldr\tr1, \u003d__BSS_SIZE__\n\tbl\tzeromem\n when __BSS_SIZE__ is not 4-byte aligned:\n 0x000000000000cced __BSS_SIZE__ \u003d SIZEOF (.bss)\n- With ENABLE_ASSERTIONS \u003d 0 for RELEASE builds and R1 not 4-bytes\n aligned zeromem() was writing 0 into all the memory in infinite\n z_loop, because of the code:\n z_loop:\n\tcmp\tr2, r0\n\tbeq\tz_end\n\tstr\tr1, [r0], #4\n\tb\tz_loop\n with R0 being increased by 4 on each step and R2 \u003d R0 condition\n would never be met.\n- BLT instruction was used for \u0027unsigned int length\u0027 value in R1\n changed to BLO.\nThis patch also fixes BLO instruction bug in \u0027memcpy4()\u0027 and function\nitself is optimised.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I8128399681def8ba80241882e355c3ca2778605f\n" }, { "commit": "986de72ace2591794f20ecce499593c6149c328e", "tree": "39d20b7fa667cb25499839fba56cfe69afcc1fe7", "parents": [ "fd7c7978cfee3138a645a2014b02562f94aef141" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Sat Jul 04 01:23:50 2020 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Sat Jul 04 01:27:38 2020 -0500" }, "message": "Add explicit barrier before sev() in tftf_send_event_common API\n\nConsider the following scenario: If sev() gets reordered above the\nevent-\u003ecnt+\u003dinc operation in tftf_send_event_common() on core 0, and lets\nsay core 1 is in wfe in tftf_wait_for_event, core 1 receives the event\nbefore the write to event-\u003ecnt from core 0 propagates to core 1. Later,\ncore 1 wakes up, reads event-\u003ecnt, sees that it is 0 and goes back to\nwfe, thereby leading to hang.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I2e8a5ab7c220b02d5b637dc7cdf3562ca73dbfdc\n" }, { "commit": "1d2b88d430aa98961865f8be296a1b61b9ce0813", "tree": "c3586961194fd2b0334787f6eed4abe997935c65", "parents": [ "231115da2736e7e36627a02497815f33f022cc57" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Mar 06 17:17:56 2020 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Mar 23 10:19:59 2020 +0100" }, "message": "cactus: add symbols relocation fixup\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ibde8aadecf6ae6c320d01ee2acab9c3c8db3859d\n" }, { "commit": "3e1a295f14be82c58d582e1f05a8b46fd068a8bd", "tree": "4b9d4094bfa149db9d30808dcd594da06b730d88", "parents": [ "837c8385669d9493794ff79b0ee894d878ac4b04" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Mar 12 15:44:17 2020 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Mar 19 17:54:23 2020 +0100" }, "message": "tftf: provide hvc conduit facility\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I3ad6e6767c2ca915f4a4fe8c5accc07e3e255387\n" }, { "commit": "c249d5e5cfbf2aa0f584001543c1d39953e1d6aa", "tree": "bae825efb76949c451188bb0e96de2ea1b120514", "parents": [ "1b5952a79ca1a6feb7b23372420285e886497852" ], "author": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Thu Feb 06 16:29:45 2020 -0600" }, "committer": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Tue Feb 11 09:22:12 2020 -0600" }, "message": "Switch AARCH32/AARCH64 to __aarch64__\n\nNOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.\n\nAll common C compilers pre-define the same macros to signal which\narchitecture the code is being compiled for: __arm__ for AArch32 (or\nearlier versions) and __aarch64__ for AArch64. There\u0027s no need for TF-A\nto define its own custom macros for this. In order to unify code with\nthe export headers (which use __aarch64__ to avoid another dependency),\nlet\u0027s deprecate the AARCH32 and AARCH64 macros and switch the code base\nover to the pre-defined standard macro. (Since it is somewhat\nunintuitive that __arm__ only means AArch32, let\u0027s standardize on only\nusing __aarch64__.)\n\nNOTE: This change is based on below TFA commit\nhttps://github.com/ARM-software/arm-trusted-firmware/commit/402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c\n\nSigned-off-by: Deepika Bhavnani \u003cdeepika.bhavnani@arm.com\u003e\nChange-Id: If2c3dbaeb01d4a9d8cfd95d906e5eaf4ae94417f\n" }, { "commit": "5c4da6500d9a3207d7bdcff07a293f0e48030e6c", "tree": "2957a50f4a75bbebdc9df4e2e740937469c01c92", "parents": [ "24756b8bcdef7c905d01d53795e5b04ee7ee3b2b", "35d824e362df862215f987fdf844ccfb8d9ccd92" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jan 13 16:09:40 2020 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 13 16:09:40 2020 +0000" }, "message": "Merge \"Make TFTF RFC 4122 compliant\"" }, { "commit": "35d824e362df862215f987fdf844ccfb8d9ccd92", "tree": "e7f4d50abc003472cf6e2f8fb6cdc72232b6e45f", "parents": [ "584b3cb3aba5423c31496a4f46ea6a58e44dd7d9" ], "author": { "name": "Oliver Swede", "email": "oli.swede@arm.com", "time": "Tue Oct 01 13:50:36 2019 +0100" }, "committer": { "name": "Oliver Swede", "email": "oli.swede@arm.com", "time": "Mon Jan 13 16:04:58 2020 +0000" }, "message": "Make TFTF RFC 4122 compliant\n\nThis is a TFTF backport of a change that makes TF RFC 4122-compliant\nby converting the stored format of UUIDs from machine order (little\nendian) to network order (big endian).\n\nThis patch changes the data structure used to store the values in the\nsame way as in the related change in TF:\n033648652f2d66abe2454a75ded891a47cb13446.\n\nSigned-off-by: Oliver Swede \u003coli.swede@arm.com\u003e\nChange-Id: I052e570b80de61f87a049a08e347a2e5da7f841b\n" }, { "commit": "52fd7337cde13d945dfb2f5b90b89bd76772fe9c", "tree": "d97d286bf69bb900dfffd886fc7b827de65fa16e", "parents": [ "584b3cb3aba5423c31496a4f46ea6a58e44dd7d9" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jan 08 14:02:18 2020 +0000" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jan 08 14:02:18 2020 +0000" }, "message": "TFTF: Enable ARMv8.3-PAuth in FWU tests.\n\nThis patch adds ARMv8.3-PAuth support for FWU tests.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I36a0a2a3870db51cda0a09bd8fd8004e2d01d2bc\n" }, { "commit": "c783c0b82c4803fd666c3e02c1250d8aeca9e378", "tree": "97fe58cabb4ee3ab15363d1663f2fca69fe45b72", "parents": [ "a78c8203e8ce7b901c13ae9fb25d8863c1bcd5bc" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 14 23:52:37 2019 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 21 19:45:07 2019 -0600" }, "message": "Support for extended register usage in SMCCC v1.2 spec\n\nThe new version of SMC Calling Convention spec makes X0-X7/W0-W7/R0-R7\nregisters available for returning results and X1-X7/W1-W7/R1-R7 for\npassing arguments during SMC calls.\n\nThis patch makes necessary changes to support the update in register\nusage and also enhances existing test case to check for expected\nbehavior across SMC call.\n\nLink to the SMCCC spec:\nhttps://developer.arm.com/docs/den0028/c\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I9e5a3e4f9de388cb9a7426b0eae1c0fa1229292a\n" }, { "commit": "719714f1895399e6d64049bed3b03c2597d95402", "tree": "eb40c8e9ffd2dae7a99f42a8a72254c6152a85f3", "parents": [ "e73248e004d971adb6259000d463c929f756a345" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 10:57:53 2019 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Oct 04 14:20:21 2019 +0100" }, "message": "TF-A Tests: Enable PAuth on warm boot path\n\nThis patch provides the following features and makes\nmodifications listed below:\n- `plat_init_apiakey()` function is replaced with `init_apkey()`\n which returns 128-bit value and uses Generic timer physical counter\n value to increase the randomness of the generated key.\n The new function can be used for generation of all ARMv8.3-PAuth keys.\n- Source file `pauth.c` moved from `plat/common/aarch64`\n to `lib/extensions/pauth/aarch64` folder which contains PAuth specific\n code.\n- Individual APIAKey key generation for each CPU on every warm boot.\n- Per-CPU storage of APIAKey added in `tftf_suspend_context` structure.\n- APIAKey key is saved/restored in arch context on entry/exit from\n suspended state.\n- Added `pauth_init_enable()` function which generates, programs\n and enables APIAKey in EL1/EL2.\n- Changes in documentation related to ARMv8.3-PAuth support.\n\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I964b8f964bb541cbb0b2f772cb0b07aed055fe36\n" }, { "commit": "8051274dfc4dae689ba53bc3e56d320780cbd5a4", "tree": "ee8e82f936f3008e99b80f97c487d369437f51f8", "parents": [ "11c53c86d4828b12ffa61ce180b0c4e694348ae3" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Thu Jun 20 10:03:17 2019 +0100" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Thu Jun 20 10:03:17 2019 +0100" }, "message": "libc: fix memchr implementation\n\nThe previous implementation could behave incorrectly because of the sign\nextension of the char when compared to the int.\n\nChange-Id: Id1e40ca9cfb1c271cb391e26698862726b833c8b\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "49180a8496b41f77bbf89b4d3db3830e135ea405", "tree": "0605865a1da94d6ce883a749d0b9195c9ff4d3d7", "parents": [ "c9ab1fd3b32cc3adce83b76a5a801ae492c175ff" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Mar 07 16:35:48 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jun 06 13:31:56 2019 +0200" }, "message": "Cosmetic changes to suspend_private.h\n\nReword some comments, express offsets relative to one another, move the\ncompile-time assertions closer to the structure they depend on.\n\nChange-Id: Id3d61ca704321844d12c9bb25e2e6eb303a7a579\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "29ef1dd13dfb989008fc98f7f7c17f163e0479bf", "tree": "8037437c8156f8fb43e26b1da5996223ed15014c", "parents": [ "cc0239947d60902a114247277523943fcf537e1d" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Apr 04 11:18:49 2019 +0100" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Thu Apr 04 11:19:25 2019 +0100" }, "message": "xlat v2: Synchronize with TF-A\n\nChange-Id: Ibd277c918088cf2afdd262689fa1e1c4ad369619\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "602b7f58dd7668411c8a4032652b4552bd7fe934", "tree": "675e0939d19e306e01703359d7b8661d4f312d32", "parents": [ "8a573de8dda42258b747e56f19190311ea090d29" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 14:13:43 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Mar 04 12:20:38 2019 +0000" }, "message": "libc: Update includes\n\nReflect the changes in the structure of libc.\n\nNB: the include of stdarg.h in nvm_results_helpers.c is not in alphabetical\norder because it needs to be included before stdio.h. Fixing this would require\nfurther changes.\n\nChange-Id: I07f62a3450802833408ff3e1f950fd3b643e5e33\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "8a573de8dda42258b747e56f19190311ea090d29", "tree": "f1243b67c7cdecaa271e0d137c20788b01b1c237", "parents": [ "892ce40b6fe172a76d3bf88bf5de0a441dc48734" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 13:54:30 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Mar 04 12:19:43 2019 +0000" }, "message": "libc: Adapt to TFTF\n\nAdd support for functions used in TFTF but not in TF-A.\n\nReplaced calls to plat_panic_handler with calls to panic, since there is no\nimplementation of the former in TFTF.\n\nChange-Id: Ic10de2c6e749db97b932cd7ffbb6067b5befe914\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "892ce40b6fe172a76d3bf88bf5de0a441dc48734", "tree": "b3f39b7552d1eee41e2344124e843285b5d1b187", "parents": [ "4128f9f887ed0ef0c511d2299c75ca71335b3cf1" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 13:42:38 2019 +0000" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Mar 04 11:17:40 2019 +0000" }, "message": "libc: Delete stdlib files\n\nKeep uuid, rand and strncpy for compatibility reasons\n\nChange-Id: Iefd82a5c9df48f6159732027e40a58f7d6afc09f\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "4128f9f887ed0ef0c511d2299c75ca71335b3cf1", "tree": "9c1624075ae2a7af810df40d527d46195d55ee26", "parents": [ "2eafdf2c74cf00b9bc3dbeccac794a433acc0c16" ], "author": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Feb 11 13:34:41 2019 +0000" }, "committer": { "name": "Ambroise Vincent", "email": "ambroise.vincent@arm.com", "time": "Mon Mar 04 11:17:40 2019 +0000" }, "message": "libc: Import from TF-A\n\nBased on arm-trusted-firware commit 873e394b3bf93214a441f9f98237b58fbbea55aa\n\nChange-Id: I510e092f2b9ff333e9461bdde8d80ed1fab1460c\nSigned-off-by: Ambroise Vincent \u003cambroise.vincent@arm.com\u003e\n" }, { "commit": "ffdfd16fd8cdedeec558749a416759cc58208b37", "tree": "723e7d461bd8d164d2ad708c054fb63f44c1eeb7", "parents": [ "418ca0c3505885eeca960fdf91f51cdd507c8764" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Mon Feb 11 15:34:32 2019 +0000" }, "committer": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Mon Feb 11 15:34:32 2019 +0000" }, "message": "Synchronize files with TF-A repository\n\nChange-Id: Ieb56d0639efd29c2695751b2b36cc98ce2c90dab\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" }, { "commit": "09a00ef98c6108fec75dafcc7dbdddacb2ee2e91", "tree": "77b585708a4fd850f0dac3a3f0fcaf34576fa8c9", "parents": [ "9e550b6f75f064b53d74a4ad3c8672332d87451c" ], "author": { "name": "Antonio Nino Diaz", "email": "antonio.ninodiaz@arm.com", "time": "Fri Jan 11 13:12:58 2019 +0000" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 25 08:23:20 2019 +0000" }, "message": "Sanitise includes of include/drivers across codebase\n\nEnforce full include path for includes.\n\nThe reason for this change is that having a global namespace for\nincludes isn\u0027t a good idea. It defeats one of the advantages of having\nfolders and it introduces problems that are sometimes subtle (because\nyou may not know the header you are actually including if there are two\nof them with the same name).\n\nChange-Id: I45e912b16c9fff81f50840dad7e7f90ed6637b2a\nSigned-off-by: Antonio Nino Diaz \u003cantonio.ninodiaz@arm.com\u003e\n" } ], "next": "971545c399ec0e79718132bcf7883111842b76e8" }