)]}' { "log": [ { "commit": "7f7ffe503bdb05a9135e5685689931914fdbcbc9", "tree": "9a874d0eafa72b5fdd70e757c08e2b5fbd19c530", "parents": [ "c48cf81af362d9b2d96e0ab4d00b56f4ec6648bf" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Mon Nov 03 15:50:11 2025 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Sun Nov 09 12:22:52 2025 -0600" }, "message": "feat(idte3): add support to detect and test FEAT_IDTE3\n\nAdd new defines for ID_AA64MMFR2_EL1.IDS and SCR_EL3.TID3/TID5\nto support FEAT_IDTE3 detection. A helper function is added to\ncheck for this feature, and the SMCCC feature availability test\nis updated to verify IDTE3 presence.\n\nChange-Id: Ib9471a838381439214a61feeed96796e406a9cb7\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "3bef40952bbb4a006a952948c2d71f5711133fbb", "tree": "9a64b37522e048e095d81c421ccb1f5e6352f599", "parents": [ "fd0680e77da168991bc78fe9b316c1a15bf66a74" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jan 28 10:51:05 2025 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Nov 07 11:26:13 2025 +0000" }, "message": "test(realm): perform LFA of RMM with Realm Payload\n\nAdd a test to execute the Realm payload with the existing RMM,\nthen perform LFA of RMM, and finally execute the Realm payload\nagain to ensure it runs with the newly activated RMM.\n\nChange-Id: Ifbba462506c6b1c0c86aba1ac22a19cd414f54d9\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "0be9d87528948d1e3c659f674c93ee40bccaeb7b", "tree": "5193b6ee09b54984a420de1465438c9ff0c2274d", "parents": [ "80b143f91f178b4b3e62015aba2a9b510f0af20c" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Aug 16 09:13:28 2024 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Nov 07 11:23:24 2025 +0000" }, "message": "feat(lfa): add LFA SMCs tests using a single CPU\n\nAdd a LFA tests for single CPU without the Activate SMC.\nAlso, include a negative test case where the firmware\nis unavailable for activation during the Prime phase,\nresulting in a failure.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I9fff281f77de87580f5b3c1fecd69fbf0f5d1f2d\n" }, { "commit": "0860f29e52eaf265cf824c1bd5104ca8197c4d54", "tree": "01c334accfb4b579553d628632229284b74594a9", "parents": [ "062073104f71dde3054755add4b76519b7526811" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Nov 04 10:14:31 2025 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Nov 04 13:21:06 2025 +0000" }, "message": "feat(smccc): add FEAT_EBEP to FEATURE_AVAILABILITY\n\nChange-Id: Ia545d5c226d3504cd821c704e765542b7d2b838c\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "055adff8d7e5431174672c7aac0bc530c4e7a778", "tree": "2968cec4c85ea200c4838a268ccd13dba9a5c7ad", "parents": [ "6d144db95cd1ee317bf66efade0fd5d4e0909c3c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:34:12 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "refactor(gic): defer IRQ handler management to the GIC driver\n\nInterrupt groups are not generic between GIC versions. SGIs and eSPIs\ndisappear, while SPIs and LPIs subtly change function. So abstract all\nof this away and hide it behind each individual GIC driver.\n\nChange-Id: Iaa55014b2940969508b290736c43134688e8c422\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "6d144db95cd1ee317bf66efade0fd5d4e0909c3c", "tree": "0b57d1214fe208e82a5b56ba03b06cec0074700f", "parents": [ "e5629bd4c6ab6088e21e7f4e2f4a27495945e21a" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 23 15:04:53 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "refactor(gic): make the concept of SGI generic\n\nSoftware generated interrupts (SGIs) are a GICv2/3/4 concept. However,\nthey are deeply embedded in how TFTF handles wake ups. This patch\npromotes the SGI to an abstract concept that can be performed\nindependently of the interrupt controller, largely the same as it is\nused today. To do that the interrupt interface for an SGI is separated\nfrom the general IRQ and each SGI is assigned a linear index from 0\nonwards. Translating from SGI to IRQ is done via a hook in arm_gic.c\nthat will be multiplexed to the appropriate driver. For GIC \u003c\u003d v3 this\nis a thin wrapper around the identity mapping as SGIs map to INTIDs from\n0 through 15. For GICv5 the mapping is different and an SGI is an LPI\nand calculated as recommended by chapter 2.5 in the spec.\n\nAdditionally, the definitions of SGI numbers are made generic as no\nplatform has utilised the difference.\n\nChange-Id: I7e6a5fbe655098c5e235b98f6dda8a14619a5904\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "e5629bd4c6ab6088e21e7f4e2f4a27495945e21a", "tree": "4034af170e7cd7109f9e4fdf2ba91d8438f2f495", "parents": [ "b731b11b6ad6db96ff34fc2a430cbeef56ed14e5" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 16 11:45:34 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "feat(gicv5): add a GICv5 driver\n\nChange-Id: I10e125c3866e50ed5adde2e4944245f47e50f2e6\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "b731b11b6ad6db96ff34fc2a430cbeef56ed14e5", "tree": "7d4c7a173bb10d0338ad1a38f38592c8db8ca9e5", "parents": [ "355710eb888e89fb739c5492639ddbdc7c0e9897" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jun 26 12:25:35 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Nov 03 14:53:32 2025 +0000" }, "message": "feat(gicv5): add GICv5 instructions and register accessors\n\nChange-Id: I1960b6f0a3bf00ae31c0baadd6202e5d3c894600\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "355710eb888e89fb739c5492639ddbdc7c0e9897", "tree": "1e3ffddb7a8bc8e05494121fcba4ad4435255db1", "parents": [ "49e1706dd57ffc22494a3a47e05e5a28e984675d", "fe1c9b82b5ecc91778eada953135051a180b5237" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Nov 03 11:45:37 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 03 11:45:37 2025 +0000" }, "message": "Merge \"feat(planes): test SIMD access from plane N\"" }, { "commit": "6a1ffac35e88673635a124c2a100696d51b8bea9", "tree": "12edd4aed8d7989463e1c0226f1aaa91dd195504", "parents": [ "bedd612ed9bc80d60dda50bddeb3823eb62bde21" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Oct 29 15:32:26 2025 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Oct 30 20:14:36 2025 -0500" }, "message": "fix(debugv8p9): fix access to mdselr_el1\n\nWhen 16 or fewer breakpoints are implemented, MDSELR_EL1 is\nimplemented as RAZ/WI, it is IMPLEMENTATION DEFINED whether\nthe trap controls have any effect on accesses to MDSELR_EL1.\n\nRef: https://developer.arm.com/documentation/111107/2025-09/AArch64-Registers/MDSELR-EL1--Breakpoint-and-Watchpoint-Selection-Register?lang\u003den\n\nChange-Id: I40215ca074e01d5e5dfb184c6aba656fc9077018\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "fe1c9b82b5ecc91778eada953135051a180b5237", "tree": "5c9df9ece7049e83dd728aa62d96de6c7a2122b2", "parents": [ "bedd612ed9bc80d60dda50bddeb3823eb62bde21" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Oct 02 18:07:49 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Oct 30 13:02:11 2025 +0000" }, "message": "feat(planes): test SIMD access from plane N\n\nAdd tests to exercise access to SIMD functinality from Plane N.\nThe tests alternate execution of \u0027rdvl\u0027 instruction from Plane 0 and\nPlane N in different sequences and combinations of TRAP_SIMD values.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I55b9bf55b43b72419e8244f228c505a58c2a819c\n" }, { "commit": "fa0259bf3db29c31d853ea1c0b1824e28719162f", "tree": "b5f90cc65be3aa63bebaaeda7bb4c5919dc55e48", "parents": [ "f543e954e2887cf5927b05ae19759c35710c4e4d" ], "author": { "name": "Slava Andrianov", "email": "slava.andrianov@arm.com", "time": "Thu Oct 16 14:32:48 2025 -0500" }, "committer": { "name": "Slava Andrianov", "email": "slava.andrianov@arm.com", "time": "Tue Oct 21 16:32:48 2025 -0500" }, "message": "feat(mbedtls): update mbedtls 3.6.5\n\nChange-Id: Iad177d211b86b3b92f7f3c8c3738f63132895441\nSigned-off-by: Slava Andrianov \u003cslava.andrianov@arm.com\u003e\n" }, { "commit": "f02375764dad0e5f1531fbdb2a17370497b27858", "tree": "48babcccbde99dc320ebe8d051ea344cc6af9723", "parents": [ "0fe74ee1f2b40f416d5e5945441f1dada67c6ec0" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Oct 07 15:08:17 2025 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Oct 13 15:18:59 2025 +0100" }, "message": "feat(smccc): availability test: add FEAT_AIE and FEAT_PFAR checks\n\nARMv8.8 introduced FEAT_PFAR and FEAT_AIE, which each have a trap bit\nin SCR_EL3.\n\nAdd the respective ID register fields and check for those two features\nin the SMCCC feature availability test, to verify that EL3 has enabled\nthe right bits in the SCR_EL3 availability value.\n\nFix some whitespace damage in the MEC field definitions on the way.\n\nChange-Id: I5a64f51ba6bcc04c271ddf1e7456ed584da6a1af\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "caca5cc7406eea453bcd93df1639ba2407ae80ef", "tree": "7e9b0f4b3da745f79e108e0c947de96ce504ad9f", "parents": [ "dcf9d6f994ef8b803fe6ea270a8c06634c97f8fc" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Jul 10 14:28:24 2025 -0500" }, "committer": { "name": "Slava Andrianov", "email": "slava.andrianov@arm.com", "time": "Fri Sep 26 09:27:48 2025 -0500" }, "message": "feat(mbedtls): update mbedtls to version 3.6.4\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I3ed56c27d7c67f5386d9c9a69b45b90a4a5f4b60\n" }, { "commit": "dcf9d6f994ef8b803fe6ea270a8c06634c97f8fc", "tree": "cc760f3bae7d7fec7fc8c1c1faee06af4ee53a65", "parents": [ "6cc4372c4036066a940a2bb82debf2ce311070e7", "595bd11a476e81d2bdc22095cac74db51c717a6b" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Sep 25 14:28:37 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 25 14:28:37 2025 +0000" }, "message": "Merge changes from topic \"rfa-related-fixes\"\n\n* changes:\n fix: remove dependency on fixed PSCI version in smc32_fast\n fix: ignore errors on optional General service queries\n fix(psci): mask MBZ bits in PSCI target_cpu arguments\n" }, { "commit": "1cb7d971ed9c81d00a041bffebe65280b137cfa0", "tree": "3cf614b280f33173a2c4edeef9edd6919b83bd46", "parents": [ "e32ac3b57ce89c30d0ff77fffeee4e8e85d4a45c", "3225df9d6bdf3f70ca4b45206a79b45e9f1b3cdb" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Sep 22 12:37:30 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 22 12:37:30 2025 +0000" }, "message": "Merge changes from topic \"ja/ffa_v1_3\"\n\n* changes:\n test(spm): bump partitions to FF-A v1.3\n fix: the FF-A version compatibility check\n chore: drop unused FF-A version macros\n test(ff-a): bump FF-A version to v1.3\n" }, { "commit": "b1467682a26053428c34eb363ba06391dcbf77eb", "tree": "af2c57fb047817f280270ffa4bb4c275064359b3", "parents": [ "6e191237b069712f613e42592fd08fe326da1ffc" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Thu Aug 28 14:38:36 2025 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Tue Sep 16 14:57:48 2025 +0200" }, "message": "fix(psci): mask MBZ bits in PSCI target_cpu arguments\n\nThe PSCI specification defines the target_cpu values almost the same as\nthe MPIDR_EL1 register value, however it only contains the Aff0-3 fields\nand the rest is declared as MBZ. Mask the MBZ bits to follow the PSCI\nspecification.\n\nChange-Id: I4196b5039aa774b357cb6932d3c2c24060f1f228\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "04315990a63abb68da3ea135c96b5b1390bf063f", "tree": "48d235d6d7cc4f6af7e5d27894dadccbb94649d8", "parents": [ "95a7af102c04cc9cea69fd7b0e6297b63064853a" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Aug 26 13:55:51 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Sep 16 11:38:33 2025 +0000" }, "message": "build(measured-boot)!: move to ext event log lib\n\nRemoves in-tree Event Log library implementation and updates all\nreferences to use the external submodule. Updates include paths,\nMakefile macros, and platform integration logic to link with lib as a\nstatic library. Some of the event log utilities related to firmware\nhandoff have been moved into that library, accordingly bump the version\nof LibTL.\n\nIf you cloned TFTF without the `--recurse-submodules` flag, you can\nensure that this submodule is present by running:\n\n git submodule update --init --recursive\n\nBREAKING-CHANGE: LibEventLog is now included in TFTF as a submodule.\n Please run `git submodule update --init --recursive` if you encounter\n issues after migrating to the latest version of TFTF.\n\nChange-Id: I5c681ab7621c8bcdfc06793a81781af3439964a6\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "95a7af102c04cc9cea69fd7b0e6297b63064853a", "tree": "28a5c49ae404720de4dca11b7f57be13be375057", "parents": [ "6a010a32ac092ff392c34b80179b21e8036731f4" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Aug 28 13:02:44 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Sep 16 11:37:42 2025 +0000" }, "message": "feat(libtl): bump version to get event log funcs\n\nLibTL now provides APIs for handling event logs from a transfer list.\nBump to that version and get rid of existing functions that duplicate\nthat behaviour.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: I4967144657765741b390cf6cda56e08a2da0eadf\n" }, { "commit": "6a010a32ac092ff392c34b80179b21e8036731f4", "tree": "dd6f31da6a94933db431d633e815002c92bbe08c", "parents": [ "2338ffcc695072c9ba1883b40473b1bb358a967f", "31f6f653bbc0eb6f2df84eb1fdb4574170bfba16" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Sep 15 12:07:44 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 15 12:07:44 2025 +0000" }, "message": "Merge changes from topic \"rmm-planes\"\n\n* changes:\n fix(rme): RMM is not taking PSTATE into account on PN entry/exit\n feat(rme): update tests to alp14\n feat(rme): uplift RSI_SYSREG_READ/WRITE tests to alp13\n" }, { "commit": "31f6f653bbc0eb6f2df84eb1fdb4574170bfba16", "tree": "0f58b61fa0d5a182ce062c876d70f8f385051b97", "parents": [ "049b469008f0901d9aa75444f10f1c5bc195cc78" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Aug 05 18:20:55 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Sep 12 17:58:28 2025 +0100" }, "message": "fix(rme): RMM is not taking PSTATE into account on PN entry/exit\n\nPlane 0 is notified, through RsiPlaneExit.pstate field of RMM PSTATE\nupon plane N exit. Also, plane 0 needs to provide RMM PSTATE value upon\ncalling RsiPlaneEnter through RsiPlaneEnter.pstate value.\n\nThis patch implements that behavior on the existing tests for planes\nas it was not implemented before.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I45af6c5863af2d2b7cc92005e16b80b895639f07\n" }, { "commit": "79aff977ca65c6344d1c04ac3391afd001845863", "tree": "5a0615fd0d4c03e2130c41b59cecb37bdba2ae66", "parents": [ "0b9f575377a7bdfdb1319eb2af60cbb668b127aa", "c609e4b7a08c3e32b10e0bac1e14201520ed99dc" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Sep 12 12:35:36 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 12 12:35:36 2025 +0000" }, "message": "Merge \"test: FFA_ABORT ABI not supported at Nwd interface\"" }, { "commit": "049b469008f0901d9aa75444f10f1c5bc195cc78", "tree": "e564191843668b2c2f96f9fb71b31885884af317", "parents": [ "4a9ffd52277103082ea78d7873e5f5732ed6fdcc" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Jun 02 20:01:02 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Wed Sep 10 13:19:20 2025 +0100" }, "message": "feat(rme): update tests to alp14\n\nRMI_RTT_AUX_{MAP, UNMAP}_UNPROTECTED have been modified on alp14.\nThis patch updates the RME tests to align with the new spec.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Icefb26de4fb66b1199a19d99496fa800f6abc2bc\n" }, { "commit": "4a9ffd52277103082ea78d7873e5f5732ed6fdcc", "tree": "7465ab700d8557cd0027ccbfce37a9637ed1bcf8", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu May 22 14:45:48 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Wed Sep 10 13:18:57 2025 +0100" }, "message": "feat(rme): uplift RSI_SYSREG_READ/WRITE tests to alp13\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Ia06872776d06655e0c0ceb6a48fca0e5aefac0b8\n" }, { "commit": "c609e4b7a08c3e32b10e0bac1e14201520ed99dc", "tree": "3c1470e09f20fbbdf3f4df56420d04347f25d315", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Aug 20 22:00:22 2025 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Sep 09 14:03:20 2025 -0500" }, "message": "test: FFA_ABORT ABI not supported at Nwd interface\n\nFFA_ABORT is supported only at secure FF-A interfaces. It is not\nexposed to NWd callers.\n\nThis patch enhances an existing test to ensure FFA_ABORT ABIs are\nnot supported when invoked in normal world.\n\nChange-Id: I2bfd2abd8db182aad4d9491b210b384e79059291\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "9324a5fce9c601405bccd35dbcc373d4f8887915", "tree": "fd6bbfdd5ad66d10bbb9ed2b996c557c52610b19", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Aug 28 12:11:45 2025 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Sep 09 18:14:58 2025 +0100" }, "message": "test(ff-a): bump FF-A version to v1.3\n\nFollowing Hafnium FF-A version bump, increase the\nexpected version in the tests to FF-A v1.3.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I82ce437834d3d711059b0a74b15bcf4757c547a5\n" }, { "commit": "794b0ac8cdb01aa8c5ad630d4592b3743f6782cd", "tree": "9d4bda7de5f2c1640670949c0aa8fb382bc31fee", "parents": [ "aa48358ef9270417897780230bdedb635cc4af56" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Jun 20 13:13:29 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:37:05 2025 +0100" }, "message": "refactor(gic): unify SGI exception data\n\nThe information we pass to exception handlers for SGIs, PPIs, and SPIs\ndoes not differer materially. Unify the handling to use the same types.\n\nSince SGIs are normal IRQs, we can put the last remaining function in\nirq.h to simplify a bit.\n\nChange-Id: I1cf6f8a2a832797a9ce54eeb025a94120f115cf6\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "5f2468444daafa55f72a976c856d7f941a83ca51", "tree": "89d59590ff79f1bb8ab1b7924c47611cb1fbd245", "parents": [ "44de1232dca506a997adef7eae08b2570892262b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jun 16 11:42:30 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:37:04 2025 +0100" }, "message": "refactor(gic): add a is_feat_gic_supported() standard helper\n\nFEAT_GIC is a CPU feature like any other, add an arch_features.h helper\nfor it.\n\nChange-Id: I762b6333907f5f3dd3352544c1f2fb211a794b3e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "a4b3334f21fb994e96549bfc968fa0086c3f9d77", "tree": "f4871f7a364074a59e8496102f3f8d56bfd29500", "parents": [ "63ea05bd16fceb7048ee625cae12394a3be5f15b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jun 19 16:24:29 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 09 06:36:24 2025 +0100" }, "message": "refactor(gic): prepare for a new GIC revision\n\nThe top level interrupt functions that common code calls are generic\nenough to become tftf\u0027s interrupt API, so rename the file to better\nreflect this. Conversely, gic_common.c is quite specific to GICv2 and\nGICv3 so also rename it to reflect this.\n\nChange-Id: I7becd74fae526a3bc5a9ef9501f0db75b1b086fb\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "9b1afa7fdeaa7a57900c3aa606626a9c9bf9e405", "tree": "b63bf8e845ab5ff2bc70f711e4ef19b012ccca01", "parents": [ "e0b75ac177b9b3e7d703948387f429a665615c23" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 15 10:58:13 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 29 11:24:36 2025 -0500" }, "message": "feat(mpam): test FEAT_MPAM_PE_BW_CTRL register access\n\nThis patch introduces FEAT_MPAM_PE_BW_CTRL testing to cpu feats.\nWe check the presence of registers MPAMBW2_EL2, MPAMBW1_EL1\nand MPAMBWIDR_EL1 to verify FEAT_MPAM_PE_BW_CTRL\nis supported.\n\nChange-Id: I5f89402e8aa0ce3320f3e120f4c0c9dbed6f8c5f\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "f41d8eeb88a4759bd463ccbb2e5eac3e6ee7eb2c", "tree": "56b3830820758d600ddb6d138590c4c6aeb60ee4", "parents": [ "735050f270024e5443f1e9bf45e98a4d3954c9d5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Jul 10 16:41:28 2025 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Aug 20 20:01:47 2025 +0000" }, "message": "test(fuzzing): adding variable coverage\n\nAdding the capability to produce coverage of the arguments of the\nSMC calls as generated by the fuzzer. The output from the FVP will\nbe routed to UART3 where a python flow will read the data to create\ntables of each SMC call with its fields shown and values given. The\noption is enabled by adding SMC_FUZZ_VARIABLE_COVERAGE\u003d1 to the\ncorresponding TFTF config.\n\nChange-Id: I2d4d310976aa2c0447efbd8ec0676bb9f8699828\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "5cbf1492282685e1cc5e0d2154c3fc48458a3e91", "tree": "999a63f4388deff1c033cd9253ff2ca0ca3addc6", "parents": [ "2a93d283f113d3971d2247090f8235c3c1d722ac", "5d7869ffd342e999e946dfd191bf90ab29c1461f" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Aug 11 16:58:34 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 11 16:58:34 2025 +0000" }, "message": "Merge changes I02b70986,I9de84f1b,I89bf0801\n\n* changes:\n feat(realm): Remove hardcoded MECID\n feat(realm): add tests for FEAT_MEC\n feat(realm): assign MECID when creating realms\n" }, { "commit": "5d7869ffd342e999e946dfd191bf90ab29c1461f", "tree": "6026aedac90e5fa9a8b6f4e4c6447b2373bedb73", "parents": [ "7288f9283f5fe302dcbf8eb67d49fc6e5df46639" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jul 21 00:02:52 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Aug 11 17:26:43 2025 +0100" }, "message": "feat(realm): Remove hardcoded MECID\n\nThis patch removes the hardcoded fixed MECID with a number which\nis continually incremented based on MAX_MECID support.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I02b70986d7eef58248abd9c8db0eda20ea32eda0\n" }, { "commit": "dc23fcdec28d9c315c741710aba76c2145b73e91", "tree": "e54af256a0e4ef90b75f627ac6fe2217d6c1bb0b", "parents": [ "1bc61da619b0b375459ae221bd13bb25dcbf0bc2" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Sat Apr 05 14:26:13 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Aug 11 16:22:35 2025 +0000" }, "message": "feat(realm): assign MECID when creating realms\n\nThis change allows TFTF to assign a MECID to every realm that is\ncreated by passing an extra parameter to the Realm creation helpers.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I89bf08011eb005d949a195b406b073955f23f5ad\n" }, { "commit": "bdb61f3c2c4de04b71d5c9b05794c3c6c4e0a14d", "tree": "4e276403352e3549e0b346a6b5c7ae3a7c4f08f2", "parents": [ "5431ac521fcedb2993160a622fa0303a620b09d0" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Jul 16 16:16:26 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Jul 25 14:04:31 2025 -0500" }, "message": "test(smccc): add SoC Name test support to SMCCC_ARCH_SOC_ID\n\nThis patch tests the SoC Name functionality of SMCCC_ARCH_SOC_ID\nas part of SMCCC 1.6 update.\n\nReference: https://developer.arm.com/documentation/den0028/latest/\n\nChange-Id: Ic3be2bdf4e7268b28d392c338533f0603f0716e8\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "afc7a0c1bc6b9c1e3bdbf6fb6f49ce13ffc575da", "tree": "1a26aacfee38c0f7108d35dc007ff4c4143cf373", "parents": [ "bbb1e4b382b0ea2aa36f4aa1f5f8c8409f4adb03" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 09 14:51:52 2025 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 09 14:51:52 2025 +0100" }, "message": "fix(smc): update vendor el3 minor version\n\nWith addition of TPM Start service to TF-A vendor el3 minor version\nwas updated.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I68a9238673d1be9c4421fe88067499c00672a545\n" }, { "commit": "aedca160ea2d648b6f46535a2cce9e4354d30e12", "tree": "3045a9a21bcaa2ca396fa7895796dcf5e295ecd8", "parents": [ "73005a60253c98274a4a1104af0bf75ccca4d205" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Apr 21 16:39:06 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Jul 09 09:08:58 2025 +0000" }, "message": "feat(realm_host_mgmt): support multiple devices in DA test\n\nConnect all off-chip pcie devices with TSM. This setup secure session,\nIDE and programs DVSEC RMEDA.\n\nHost assigns all devices that are connected with TSM to a Realm. And\nRealm locks and accepts the assigned device.\n\nThis patch adds host_da_workflow_on_all_offchip_devices testcase.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Id8ea54f9c9aad45787a0aac106a9260f68a63ec5\n" }, { "commit": "73005a60253c98274a4a1104af0bf75ccca4d205", "tree": "4b377917909b3aeada9b6a23598112b2b63fd145", "parents": [ "b0833d26dacc0fef45e4d695f9e7028a8d20825e" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 10:37:15 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Jul 09 09:08:51 2025 +0000" }, "message": "refactor(lib/pcie): rename macro CHECK_DA_SUPPORT_IN_RMI\n\nRename macro CHECK_DA_SUPPORT_IN_RMI to SKIP_DA_TEST_IF_PREREQS_NOT_MET\nand move it to host_da_helper.h\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ie955e1dcb2edefa0f41edfc36b4b2587cb465a29\n" }, { "commit": "b0833d26dacc0fef45e4d695f9e7028a8d20825e", "tree": "f0902ea53de0d53d4ff4fb3464ea78910ee0ef61", "parents": [ "bbb1305abc89d5b88a4cefe374e05052f27d165c" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jun 26 11:05:51 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:39 2025 +0100" }, "message": "feat(lib/pcie): init pcie device capabilities\n\nAdd additional fields in pcie_dev structure that will be later\nused by DA testcases.\n\nFind and initialize devices extended capabilities.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I32042393dc023d8ac948aa9f4ea921de22ec0b98\n" }, { "commit": "bbb1305abc89d5b88a4cefe374e05052f27d165c", "tree": "914c12b61f6f91da1982b906aa3dd180b911583c", "parents": [ "503b89a6b2d6ecd039401bd7f6f08f0d3cbb69a6" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 24 14:00:06 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:39 2025 +0100" }, "message": "feat(lib/pcie): add dvsec helpers\n\nAdd DVSEC RME DA support and helpers based on RME System\nArchitecture [1].\n\n[1] https://developer.arm.com/documentation/den0129/latest\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I29c2dc3c94fa295c9948f63f57f88e2763326291\n" }, { "commit": "503b89a6b2d6ecd039401bd7f6f08f0d3cbb69a6", "tree": "bf4b3f02eabecec15b63e2c5247eb6085b7c5ce8", "parents": [ "20c2d74e687556c462b49eb1f8a5e3afc21698cb" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jun 19 10:34:11 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jul 01 17:53:36 2025 +0100" }, "message": "fix(lib/pcie): import pcie enumeration helpers from rmm-acs\n\nImport PCIe enumeration helpers from rmm-acs[1] at tag v1.0_REL0_12.24.\n\nThis patch adds the missing device enumeration logic added as part of\nthe initial commit.\n\nThis change is verified with FVP default PCI topology. The helper\npcie_init() might need some enhancements for other platforms with\ndifferent PCI topology.\n\n[1] https://github.com/ARM-software/cca-rmm-acs\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I46724c458fe0071272fc7bca73d51e27181bb1b4\n" }, { "commit": "51f0333e24e6c4aff44ace871c6042b507476b5e", "tree": "4e7a4c0d34ab7cb3c0039bbd3b59431f646c531c", "parents": [ "cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jun 27 13:47:23 2025 +0000" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jun 27 13:57:23 2025 +0000" }, "message": "revert: replace in-tree Event Log Lib w/ submodule\n\nThis reverts commit cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849.\n\nReason for revert: Causing CI failures\n\nChange-Id: Iad32fb9ba1d32044ef647f01e3091e9b0ee0d9e2\n" }, { "commit": "cc89c2fc40c74ea8d8f1a1489ea988c66c1b5849", "tree": "8be9469773b3f15614ee27ae9539cc29f8692c3c", "parents": [ "68ecce15bcd5db2449700d122f4e8f32cce91ae9" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu May 22 11:08:46 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 24 15:58:15 2025 +0000" }, "message": "refactor: replace in-tree Event Log Lib w/ submodule\n\nThe Event Log Library has been relocated to a separate repository and is\nnow integrated as a submodule, eliminating the need for in-tree files\nand reducing maintenance efforts for TFTF.\n\nChange-Id: I29694f8b3b08bb1d57dd685f6e42dc9f69d241bb\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "68ecce15bcd5db2449700d122f4e8f32cce91ae9", "tree": "4e7a4c0d34ab7cb3c0039bbd3b59431f646c531c", "parents": [ "550d5104ffe85f2f6994ef04a7172627cd76770e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon May 12 12:38:24 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 24 15:58:13 2025 +0000" }, "message": "feat(libtl): integrate Transfer List Library as submodule\n\nReplaces in-tree transfer_list implementation with LibTL submodule.\nRemoves legacy source and headers, updates includes and makefiles\nto use the standalone library. Adds architecture-specific inttypes\nheaders for compatibility.\n\nChange-Id: Iff8272a6417983b9fb8e7f6bde6db44c2a6020f5\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "19ad61740ec71f886473c3f4d125ad062ce6c9f4", "tree": "5f707d4e0cbfd1136312c33f02576745a9bf689d", "parents": [ "c58e4697c2df3d1b9d3a7d2e3da2294a13c27449" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 24 10:39:53 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 17:57:03 2025 +0100" }, "message": "chore(host_da): move host RME DA related functions\n\nMove host RME DA related functions from host_rmi_da_flow.c\nto host_da_helper.c.\n\nChange-Id: Ib5c5ba3440ba1fa26b6f25a8bfab002183252627\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "c4ef92bd075d41d7d1ae03b9c5484881547946e7", "tree": "3471ac534950b9cde8059ed320aa4a1d4d797595", "parents": [ "ec4249f483a9ca6e5d65db7ae9c65a69b1d22a96" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Fri Jan 24 11:55:02 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 16:53:06 2025 +0100" }, "message": "feat(realm_host_mgmt): added support to call RMI VDEV ABIs\n\nThis change creates a Realm witn RMI_FEAT_DA feature and assigns\na VDEV to the Realm using RMI_VDEV_CREATE and calls various VDEV\nmanagement ABIs like:\n SMC_RMI_VDEV_DESTROY\n SMC_RMI_VDEV_STOP\n SMC_RMI_VDEV_GET_STATE\n SMC_RMI_VDEV_COMMUNICATE\n\nOnce the VDEV is assigned to a Realm. A REC enter is done to invoke\nDA RSIs calls.\n\nA common dev_communicate is implemented that is used by both PDEV\nand VDEV communicate.\n\nRenamed testcase host_test_rmi_pdev_calls to host_invoke_rmi_da_flow.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Iefe6f6ee4c0810479d20319851cd8a6590c1e4d7\n" }, { "commit": "ec4249f483a9ca6e5d65db7ae9c65a69b1d22a96", "tree": "04bb12194f885577d0ddbe29aba3008dc9c84660", "parents": [ "5dac5b087067ac7c726ba6eef13538e84d330f43" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jan 07 15:13:09 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 16:52:09 2025 +0100" }, "message": "feat(host_realm_mgmt): align DA RMI ABIs RMM spec 1.1-alp12\n\nThe DA RMI ABIs related to PDEV, VDEV are aligned to RMM specification\n1.1-alp12\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I6ac86bd2d574f93c7f7b29095b242e4cbf73a071\n" }, { "commit": "5dac5b087067ac7c726ba6eef13538e84d330f43", "tree": "6e951e9d7e671c439d7fbce6bf8554b76f9124c2", "parents": [ "f54e1fea268a63b2fb6bb41b0a1be4d3f9408ffa" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jan 07 14:51:50 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 16:52:09 2025 +0100" }, "message": "chore(include/runtime_services): update SMC RMI commands\n\nThis syncs the naming of SMC RMI commands with TF-RMM. This change helps\nto update SMC RMI commands and data types easily whenever it gets\nupdated in TF-RMM.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I8acc96d5326ad0656df0f6c7822adefe87a275c3\n" }, { "commit": "8307c3367e29b068cd3e65b5bd05aa28f8fee0f8", "tree": "b19d216065c9af2c129b5e692024acc836b70662", "parents": [ "d1cf6dc75ffa489f3055b2c453ad57893214b6bc" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Jun 12 10:30:46 2025 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 15:35:48 2025 +0000" }, "message": "feat(rmm): add tests for FEAT_TCR2 on RMM\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I4dc16c5c6edcabf993ea30fe53eff5993b5af651\n" }, { "commit": "d1cf6dc75ffa489f3055b2c453ad57893214b6bc", "tree": "c3be96dc6a3cf24de7b5d778004a4e76d97dbbc5", "parents": [ "d479a125cbb07b63c85daf42a36215008168fd37", "a1fe738b1fd6212d92e20a408a0110778276732b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 13 10:53:51 2025 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 13 10:53:51 2025 +0000" }, "message": "Merge \"feat(rme): test access outside PAR from Plane N\"" }, { "commit": "1b16dc85e01ac96b02a384a307925005a471b2e2", "tree": "56be81714e31b82397012a6203f28a17bbb203d4", "parents": [ "718fd7902c015a64b49b12dcb6005d1aa50fd72e" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Jan 14 11:40:18 2025 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jun 12 23:30:01 2025 +0100" }, "message": "feat(rme): add dev mem map/unmap tests\n\n- Add tests for RMI_DEV_MEM_MAP and\nRMI_DEV_MEM_UNMAP commands as per RMM Specification 1.1-alp12.\n- Add RNDR and RNDRRS registers\u0027 definitions.\n- Redefine RNDR and RNDRRS read functions as:\nDEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)\nDEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS)\n\nChange-Id: Ieecc41dd6d3011bb63101bc38d527a8f57e0ef4a\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "718fd7902c015a64b49b12dcb6005d1aa50fd72e", "tree": "6be817fbd9b1073bdd876b527e31e06e45b8a782", "parents": [ "5032d7bc760128a07ace8c9d4d91f7c3e9011cda" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Nov 08 14:55:20 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jun 12 22:45:11 2025 +0100" }, "message": "feat(rme): add dev granules tests\n\nAdd tests for RMI_GRANULE_DELEGATE and\nRMI_GRANULE_UNDELEGATE commands using\ndevice granules.\nAdd plat_get_dev_region() function to\nretrieve platform PCIe memory region info.\n\nChange-Id: Ie59361dd28e11db348c30b033c156de044aa0ffc\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "a1fe738b1fd6212d92e20a408a0110778276732b", "tree": "ad9028b4524278c1b14628871964c46a72e564b8", "parents": [ "5032d7bc760128a07ace8c9d4d91f7c3e9011cda" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Apr 25 20:45:17 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jun 06 17:53:31 2025 +0100" }, "message": "feat(rme): test access outside PAR from Plane N\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I3c5069e14fdf27e6c36bd1e0651ceff4ee7396ef\n" }, { "commit": "ba6ef4f4426da1aa17f76a1b8f914b53aaeb6d34", "tree": "f9c5c334b18e4bc1ddd30b2d03c0053d17906103", "parents": [ "0c8bf6445cdd41d08d1b926160d2f66b3312f12b" ], "author": { "name": "Thaddeus Gonzalez-Serna", "email": "Thaddeus.Gonzalez-Serna@arm.com", "time": "Tue May 13 14:54:41 2025 -0500" }, "committer": { "name": "Thaddeus Gonzalez-Serna", "email": "Thaddeus.Gonzalez-Serna@arm.com", "time": "Mon Jun 02 09:46:51 2025 -0500" }, "message": "test(fwu): validate scenario of invalid FWU IMAGE SIZE\n\nTest to increase code coverage in bl1 directory where\nbl2 and bl2u are both corrupt with invalid image sizes\n\nbl1_fwu.c cc% improved by 10%\nbl1_main.c cc% imporved by 1%\n\nChange-Id: I4637a9e566e4edda8474da37ea4f3511fa32b6a7\nSigned-off-by: Thaddeus Gonzalez-Serna \u003cThaddeus.Gonzalez-Serna@arm.com\u003e\n" }, { "commit": "f44772a0fd26dd270f69650dc5775ca4c00da446", "tree": "bb4eeb428aeab6f88ea1aaeaa64fbc44ef28d9c9", "parents": [ "86cb7f1297450971b484db64e025ea273981371f" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed May 28 00:39:17 2025 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed May 28 01:11:30 2025 -0500" }, "message": "fix(smc): update vendor el3 minor version\n\nWith addition of acs handler to TF-A vendor el3 minor version\nwas updated.\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: Ic03e25d1a45fdf2e701b4b11db6a456435a227e5\n" }, { "commit": "5ab09e8174e1ec17d6b1c35483f268e0775a5b67", "tree": "3be81b31149a1c413293061bd39d41c94d2416e6", "parents": [ "060efe97ff6c31b7dbec96af9fde0b169db4183d", "089c9ad705c1f393d95dd911c76a6772af45d1fd" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Apr 28 17:47:34 2025 +0200" }, "message": "Merge changes from topic \"hm/handoff-mb\"\n\n* changes:\n feat(handoff): add event log test\n feat(measured-boot): add measured boot drivers\n" }, { "commit": "089c9ad705c1f393d95dd911c76a6772af45d1fd", "tree": "1842ee9a2fabfe773b56c98a76bb7e831b26b5a0", "parents": [ "b674809e4d937d44f85ef53aa2bdbb9f74b569b2" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:54 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:37 2025 +0000" }, "message": "feat(handoff): add event log test\n\nAdds a new TFTF test to validate presence and correctness of the TPM\nevent log in the transfer list received from EL3. Uses event_log_dump to\nparse and output log data.\n\nChange-Id: I0b1f782429e4bfe3d1760fce52d40a9836dc27a2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "b674809e4d937d44f85ef53aa2bdbb9f74b569b2", "tree": "3192a0624448d4503cb3679f0d939cb7c169ac22", "parents": [ "19620adc7cbcae26cc432a28a9c3b0944957cf13" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:03 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:25 2025 +0000" }, "message": "feat(measured-boot): add measured boot drivers\n\nIntroduces core measured boot support, including TPM event log handling,\nhashing infrastructure, and event formatting per TCG spec. The driver is\nimported from the existing implementation in TF-A.\n\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nChange-Id: Ib2e6a88c86f110f9a6907c3e6dbb0dc736486de9\n" }, { "commit": "060efe97ff6c31b7dbec96af9fde0b169db4183d", "tree": "bc0e18f218d5facba2ae30222dad21bc7f5f3bbd", "parents": [ "336f1c20beba190b912a83756ca91626b2860c14", "2230a5955d328b4a018e72163482690892f5ff59" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Apr 25 16:18:55 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 25 16:18:55 2025 +0200" }, "message": "Merge changes from topic \"fix_pmuv3p9_test\"\n\n* changes:\n feat(ras): add RAS system registers access test\n fix(smccc): availability test: add two features and fix TRNDR\n" }, { "commit": "6d9e106780746a3248901b93f9a334d28eef4e5e", "tree": "f94fbed4d910a3688fa888f5452a337c38b0fb3b", "parents": [ "0de678ef3e7136af91b314c893030311741a7f80", "d5bb5f6c82f7ebcf28dccbbfad058e27e207c14f" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Apr 04 20:16:58 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 04 20:16:58 2025 +0200" }, "message": "Merge \"feat(mbedtls): update mbedtls to version 3.6.3\"" }, { "commit": "0de678ef3e7136af91b314c893030311741a7f80", "tree": "03cc016c0059ab0d53ba9880a008a78634a0febe", "parents": [ "a864222f08cc068d6659fa3bedbe322578513d60", "11e574835b289bc3c9742d76ea697a53023527bc" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Apr 04 15:40:59 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 04 15:40:59 2025 +0200" }, "message": "Merge changes from topic \"mp/cpu_off_broadcast\"\n\n* changes:\n test: deny prohibited ABIs while handling CPU_OFF psci msg\n feat: add build flag to control support for CPU_OFF psci msg\n feat(cactus): receive psci msg through direct req framework msg\n" }, { "commit": "d5bb5f6c82f7ebcf28dccbbfad058e27e207c14f", "tree": "16cd4e4315d2b0f0599a93746efee17eddba924e", "parents": [ "78fb528d0e2ecb53c533f6accf0da1f90d289353" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 03 12:49:06 2025 -0500" }, "committer": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 03 14:10:06 2025 -0500" }, "message": "feat(mbedtls): update mbedtls to version 3.6.3\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I4bfb546c351c30a6fc4d22f29bc03efad316df7d\n" }, { "commit": "de873bbd54a58f751553ebd42b302a348ca342a7", "tree": "c1db5fe9b4ca52ca86fcaf77ac45c89e404187bd", "parents": [ "78fb528d0e2ecb53c533f6accf0da1f90d289353" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Apr 03 11:02:36 2025 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Apr 03 11:02:36 2025 +0100" }, "message": "fix(rme): fix position of RTT_S2AP_INDIRECT bit in RmiFeatureRegister0\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I514368fe64834324fd4ea2b98e9b175dba20288c\n" }, { "commit": "11e574835b289bc3c9742d76ea697a53023527bc", "tree": "4671e58c1aef29334f69dec38de3b4ded5aa05ed", "parents": [ "a2b6b37ed6eaf7d0f9dfc12a04499863b25cf559" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 28 11:46:16 2025 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 01 13:19:18 2025 -0500" }, "message": "test: deny prohibited ABIs while handling CPU_OFF psci msg\n\nFF-A spec states that SPs are prohibited from invoking Direct request,\nFFA_RUN and FFA_YIELD interfaces while handling power management\nframework message. Make the Cactus SP intentionally invoke prohibited\ninterfaces and attest that SPMC should deny such invocations.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I0a823bf950e3895cb4aff7320c6a0ef7fdec634b\n" }, { "commit": "611d095453cf001e436f795ac8209b27f46a2fdb", "tree": "2435b48f94395c106adc5529e5031ccd92ca3197", "parents": [ "78fb528d0e2ecb53c533f6accf0da1f90d289353" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jan 31 16:07:08 2025 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 01 13:07:09 2025 -0500" }, "message": "feat(cactus): receive psci msg through direct req framework msg\n\nCactus receives PSCI CPU_OFF power management operation message\nthrough framework direct request message and it will respond back\nwith framework direct message if all conditions are met.\n\nCactus SP1 and SP2 explicitly subscribe to CPU_OFF power management\nmessage through their respective manifests.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I790a8698d238e29847e376b4fa9447a6241ef17e\n" }, { "commit": "677708401f13bfa0c9d974aff8e3db3f67b77c5a", "tree": "9aa226627feb27c793ecb2894519550e18dadfd5", "parents": [ "41567dc5c36eb7cb0c621cc801e99543e95093b3", "8205a64846d581937e77919a9fe858db53324a84" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Mar 31 16:28:02 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 31 16:28:02 2025 +0200" }, "message": "Merge changes from topic \"km/ffa_features\"\n\n* changes:\n refactor: refactor `get_ffa_feature_test_target`\n refactor: use an enum for FF-A errors\n" }, { "commit": "8205a64846d581937e77919a9fe858db53324a84", "tree": "77b786526b95ab4219225966828b847eaf2546ab", "parents": [ "af77b16df26371cf954fd410359f55981683d1ea" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jun 19 15:05:19 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Mar 31 11:43:01 2025 +0100" }, "message": "refactor: refactor `get_ffa_feature_test_target`\n\nChange `get_ffa_feature_test_target` to return a `size_t` instead of an\n`unsigned int`, because `size_t` is the return type of operators like\n`sizeof()`.\n\nChange `get_ffa_feature_test_target` to require its argument to be\nnon-null (and assert that it is). This function is only used for getting\nthe array of features to test, so there is no use case where passing a\nnon-null pointer would make sense.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I33597f1a2f7681eda59ece08062e48c28752c111\n" }, { "commit": "af77b16df26371cf954fd410359f55981683d1ea", "tree": "620d8dae4e9d64c4001962eb05ee89b677b08ca8", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jun 19 10:44:54 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Mar 31 11:43:01 2025 +0100" }, "message": "refactor: use an enum for FF-A errors\n\nChange-Id: Id30f36840e0668daa152ab90a2559fade7883c5f\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "43ad50d798007af9d607898597d30bf215d3aa05", "tree": "1d0620e5b07b525e656d82ea22e7aefedba7f6a7", "parents": [ "8993e8ec7c66a849dad48f7b57e866cc40de3191" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Mar 28 17:37:04 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Mar 28 17:47:36 2025 +0000" }, "message": "feat(rme): update FEAT_MPAM tests on Realms\n\nCurrently, to test that accessing a FEAT_MPAM register from a Realm\ncauses an undefined abort injected back to the Realm, we only test\nby accessing a single register.\n\nThis patches updates the test by trying to access all MPAM registers\nfrom the Realm to validate that an undefined abort is taken to the\nRealm for all the registers.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I16c88d467eb2a49342694536a1c7b6358416dc34\n" }, { "commit": "9d84ad1ceb8256e942213537602c6434577b7bc0", "tree": "f1069ac2c0ef008601b2892cae5960fba6665787", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "fb96b980c85d916b55c78b7d22e5b6d8e086ca54" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "message": "Merge changes from topic \"kc/fuzz\"\n\n* changes:\n test(fuzz): add FF-A fuzzing\n test(fuzz): Fix single feature testing\n" }, { "commit": "fb96b980c85d916b55c78b7d22e5b6d8e086ca54", "tree": "2a4c319dd3761099924e160acca59d4075bf749d", "parents": [ "2b6c140b52790beebbb921dd0311efefb0bb0c5c" ], "author": { "name": "Kathleen Capella", "email": "katcap01@u203721.austin.arm.com", "time": "Thu Apr 25 17:09:33 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Mar 11 12:10:59 2025 -0500" }, "message": "test(fuzz): add FF-A fuzzing\n\nAdd necessary components for FF-A calls to be used in fuzzing framework\nincluding bias tree, `run_ffa_fuzz` helper function, makefile additions,\nand initial SMC description file with FF-A smc calls.\n\nCan use ffa_smc_calls.txt to generate necessary header files.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ib19714342d31cacd818471686a7e4c8910fed5c3\n" }, { "commit": "2230a5955d328b4a018e72163482690892f5ff59", "tree": "7ac3698bb9d614af35f74999fc42f4ffee5d7ee3", "parents": [ "37e3f3e1d237b6e8289fbc0a090b2b4dd2d4b9ec" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 17:19:34 2025 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 17:30:44 2025 +0000" }, "message": "feat(ras): add RAS system registers access test\n\nFEAT_RAS introduces EL1 system registers to query error records, those\nCPU specific parts of the RAS extension can be accessed independently of\nany FFH/KFH handling setup or any system specific RAS implementation.\n\nAdd a test to verify that those registers can be read, when the CPUID\nfield advertises the MPAM (CPU) extension.\n\nChange-Id: I7429fc815e7e0ee0cd736603966969b2cfb5f469\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "37e3f3e1d237b6e8289fbc0a090b2b4dd2d4b9ec", "tree": "43448a6e0d637e635d482b1abf2144f0d7dda046", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Mar 07 17:25:24 2025 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Mar 10 15:04:03 2025 +0000" }, "message": "fix(smccc): availability test: add two features and fix TRNDR\n\nThe SMCCC_ARCH_FEATURE_AVAILABILITY test was not up-to-date and was\nmissing two features: FEAT_TWED and FEAT_PMUV3P9. Connect the SCR_EL3\nand MDCR_EL3 bits to their corresponding ID register fields, so that\nthey can be tested.\n\nAt the same time the FEAT_RNG_TRAP test was slightly off: the SMCCC spec\nsays it should report accessibility of the RNDR and RNDRRS registers, so\nwe should look at FEAT_RNG, not FEAT_RNG_TRAP when checking the TRNDR\nbit.\n\nThis fixes the tf-a-tests run on an FVP with ARMv9.4 enabled, which was\nreporting the following issues before:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\u003e Executing \u0027SMCCC_ARCH_FEATURE_AVAILABILITY test\u0027\n TEST COMPLETE Failed\nis_feat_rng_trap_present says feature is supported but SCR_TRNDR_BIT was\n\tnot set!\nSCR_EL3 still has values set: 0x20000000. Test needs to be updated\nMDCR_EL3 still has values set: 0x80. Test needs to be updated\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nChange-Id: I73a0d240b2cd1a16e1c64d3d66ee30e658c9c946\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "tree": "a0ec5b6bff32d2fa1294f33af597c0d54558306e", "parents": [ "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "c8f5a2ee90f2b376da910f08170af4c4dc7396ae" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "message": "Merge \"test: test the save restore logic for brbcr_el1\"" }, { "commit": "3d43731d485b1405c5a224f65a7c2d381d46b093", "tree": "c8d15de87f5a5155e57a145d43cbeb18c118f33f", "parents": [ "9b63fa56b4e21ecb87d409c6a95d1d3d5ee06376", "5668f34a89dfcee72c2a8e6aa443c7436f341d61" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "message": "Merge \"fix: add split workaround check in Errata ABI test\"" }, { "commit": "9b63fa56b4e21ecb87d409c6a95d1d3d5ee06376", "tree": "7fc7ec71d57eec9732f6793a5ed15d3e2b354824", "parents": [ "90506fbda56864b578980bc2d433f2ba38207e61", "55d5db87b83b6a073ed3c954d455b862e7b2e7fe" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Mar 07 11:06:37 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 07 11:06:37 2025 +0100" }, "message": "Merge changes Ic57f049d,Ifc98b8c6,I7e34a007,I20cbb9d0\n\n* changes:\n test(realm): extend ripas tests for planes\n test(realm): enhance realm memory exception tests for planes\n test(realm): add test for multi rec planes\n test(realm): validate NS EL1/EL2 context is preserved by RMM\n" }, { "commit": "c8f5a2ee90f2b376da910f08170af4c4dc7396ae", "tree": "625509a3d6d8838e0c31c9e89fbf23ed9361d15f", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Tue Feb 04 15:22:01 2025 -0600" }, "committer": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Mar 06 16:55:05 2025 -0600" }, "message": "test: test the save restore logic for brbcr_el1\n\nThis patch tests the save/restore logic by enabling\nbranch recording at NS-EL2. Additionally this\npatch also tests the trap logic when FEAT_FGT is enabled\nand a Realm tries to access any FEAT_BRBE related registers.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I176ea6feaf01d42cfd6231dc65a9470da8d1e37c\n" }, { "commit": "55d5db87b83b6a073ed3c954d455b862e7b2e7fe", "tree": "0019d75c61f3cbac06bc2f1e25d5944c8f9f3880", "parents": [ "7d3b999376c7416584639411f36bdadf877060d3" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Mar 03 12:56:04 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 21:08:59 2025 +0000" }, "message": "test(realm): extend ripas tests for planes\n\nTest that accessing page with RIPAS\u003dEMPTY from\nPlane N causes plane exit to P0.\n\nChange-Id: Ic57f049d0fa0140630aa7bfc0702a2dc729967a8\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "90506fbda56864b578980bc2d433f2ba38207e61", "tree": "b77200b91f6f52038c3754cc14fc2896d407f149", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120", "b3d451c3bb4b3b6c6a03aaaa8e1a785c5a4ca0a5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Mar 06 21:39:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 06 21:39:06 2025 +0100" }, "message": "Merge \"fix: add xpaci instruction to exception report\"" }, { "commit": "5668f34a89dfcee72c2a8e6aa443c7436f341d61", "tree": "9a7778183d2dedaa383e4c517a4a17dae6a7fa49", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Mar 04 02:01:16 2025 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Mar 06 12:43:08 2025 -0600" }, "message": "fix: add split workaround check in Errata ABI test\n\nThis patch adds support to validate split workarounds\nas part of Errata ABI CPU Features testcase. It also\nimproves the test case, making sure it also\nruns on lead cpu.\n\nChange-Id: Ic21fffdf20714ad639e92ad0be96d2f154f37f04\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "bd729193dcdb19a5f5fa9b259770f1d1f365bad0", "tree": "00c47d7308aee2d02a16a3d4a5fbacaf7cf4407d", "parents": [ "78effaa2c47b04abd68273bdea4ebb4f6f9455c0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 24 17:02:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:57:56 2025 +0000" }, "message": "test(realm): add test for multi rec planes\n\nTest exercises SMC_PSCI_CPU_ON from aux plane.\nRequest is first routed to P0 and then to Host.\nHost enters P0 and then P1 on all CPUs.\n\nChange-Id: I7e34a0070ffa7305b97a0d93de62b64042771a18\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "78effaa2c47b04abd68273bdea4ebb4f6f9455c0", "tree": "9ffb7b9430ee5600da7f8e0cd5cd557752ea85fa", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 07 10:30:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:18:01 2025 +0000" }, "message": "test(realm): validate NS EL1/EL2 context is preserved by RMM\n\n- Test validates that NS EL1/EL2 registers are preserved while\n entering and exiting realm world.\n- Test validates that accessing s2por_el1 in realm causes data abort.\n\nChange-Id: I20cbb9d0d59474507f89ee7cf8e127fff4706610\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "992c62b427ad7fc425ec3c02e6c2f5e98e94d120", "tree": "1267fde5c9244b900105a5d2d073c4d938ef7e0d", "parents": [ "3e496b408634030405c5fa5fbcb8b8babcebfb30", "eb2dd23469c8a5f3624b60ce21fab8299785fe4e" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 05 20:46:05 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 05 20:46:05 2025 +0100" }, "message": "Merge changes from topic \"kc/stmm\"\n\n* changes:\n refactor: move StMM to cactus tertiary\n feat(hob): add boot-time prints for cactus-stmm HOB list\n refactor(cactus): map boot information regions\n feat(hob): add HOB definitions to TFTF\n feat(spm): add STMM cactus partition\n" }, { "commit": "b3d451c3bb4b3b6c6a03aaaa8e1a785c5a4ca0a5", "tree": "4f962c5a8e86e12e0bdd0526bbb59dda55efe9b7", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Feb 13 14:24:06 2025 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Mar 04 10:37:16 2025 -0600" }, "message": "fix: add xpaci instruction to exception report\n\nWhen reporting an exception with ENABLE_PAUTH\u003d\u003d1 calling xpaci\nbefore printing the ELR value will remove the PAC and make the\npointer readable.\n\nChange-Id: I45339dbb3396f403768ea3ee780d0c5010da44c4\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "de01b5dd3ae940a16ad9f370ad1e734190553e73", "tree": "9dcf2ef13e4449a8322e044da38a1ed94579e171", "parents": [ "6164898b4355bf1f311a78f0796a75baf7f50983" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 02 21:17:11 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 28 13:01:16 2025 +0000" }, "message": "test(realm): add support for s2poe/pie for planes\n\nAdd support for s2poe/pie for planes.\nUpdate planes test to run with s2poe/s2pie\nboth enabled and disabled.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If85b8c4cff9e8fe43978088beaf848fe4b2b9a40\n" }, { "commit": "716c8cc0951fb6a3e212d4bd9b79ea0b6f9bdf9b", "tree": "858cebc6186fb65cc28fc02883dec4a112534603", "parents": [ "42dd088203e40911c67106d46cfccde58d55e1b5" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Feb 25 18:22:45 2025 +0000" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Feb 26 11:33:37 2025 +0000" }, "message": "fix(lib/pcie): bdf macro\n\nThe existing PCIE_CREATE_BDF macro is a non standard way of deriving bdf\nvalue. This fix assigns 3 bits for function number, 5 bits for device\nnumber and 8 bits for bus. This bdf value is used as TDISP function id\nwhile passing it to DSM. Using a wrong bdf value results the TDISP\ncommand to fail.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I31301be4dfc9bd2409da73e54715f73079a921cb\n" }, { "commit": "42dd088203e40911c67106d46cfccde58d55e1b5", "tree": "48f1d07ae117eadadd1c0496cc0a8ad895abff3b", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd", "c779d0d0ac9faf894963675dcccb6110e3f0229a" ], "author": { "name": "Sandrine Afsa", "email": "sandrine.afsa@arm.com", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "message": "Merge changes from topic \"xlnx_fix_custom_inval_entry\"\n\n* changes:\n fix(versal): platform definition of invalid entry\n feat(tftf): new interface to get an invalid entrypoint address\n" }, { "commit": "eb2dd23469c8a5f3624b60ce21fab8299785fe4e", "tree": "5e4c4725690951c6339593a72f39466cf6eea1b6", "parents": [ "8808a945590fbc4138c0961717da75ddc383ede0" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Fri Feb 07 18:41:54 2025 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 23:05:23 2025 -0600" }, "message": "refactor: move StMM to cactus tertiary\n\nReuse existing cactus tertiary partition for StMM testing rather than\nadding an additional partition.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I0c40758cc8f5e7cb2239c80346ad785c0d6888e5\n" }, { "commit": "8808a945590fbc4138c0961717da75ddc383ede0", "tree": "992e6e95734b14bddb4dddc924c19122fccc6f69", "parents": [ "8ac4dd8ce81ba17121c62b4d39925ae6b62d7998" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Jan 07 15:45:39 2025 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 23:05:15 2025 -0600" }, "message": "feat(hob): add boot-time prints for cactus-stmm HOB list\n\nAt boot time, print HOB headers and contents.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ic634f045cacdbc8e318836eba85982a93f55fc0f\n" }, { "commit": "bde3eab2e68bc0059b5ccfc83a13759287eb9cf4", "tree": "90acb838f69c8c620e7790409df205077a8fe65b", "parents": [ "e8a17a905ca1c20acb1b9248ac725ab847bddc42" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Dec 09 14:04:43 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 13:51:36 2025 -0600" }, "message": "feat(hob): add HOB definitions to TFTF\n\nAdd necessary HOB structure definitions and HOB library to TFTF.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I1a81cd99df52436a077a71030244ca642122497a\n" }, { "commit": "e8a17a905ca1c20acb1b9248ac725ab847bddc42", "tree": "4f6dd3a344ab642adacdbddd6d06a409ee356b8e", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Thu Dec 05 18:28:29 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Fri Feb 21 09:42:27 2025 -0600" }, "message": "feat(spm): add STMM cactus partition\n\nAdd another instance of cactus S-EL1 partition, using\nStMM manifest.\n\nThis is to validate HOB generation at build-time.\n\nThe manifest contains memory region nodes using the\nsame node names as in the StMM partition manifest,\nbut changed the ranges to align with memory map of\nbase FVP. The device region nodes have been dropped,\nas they didn\u0027t affect the creation of the HOB list.\n\nDefined the UUID for the partition in the test code,\nand refactored slightly some of the code paths,\nso it has an RXTX buffer and is able to do the basic\nFF-A setup tests.\n\nAlso added the cactus-stmm node to the sp_layout\nfile.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I05971fc9d63f03bd7ea43b3bcaba5b6362a44ca0\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "1e4f7a064f08205a0a37922e660b238be04a8137", "tree": "ccf0e6f9e63ee23a7b249eed564ceedafcee9035", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:40:56 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:16 2025 +0000" }, "message": "feat(tftf): new interface to get an invalid entrypoint address\n\nTFTF test for invalid entry address in cpu hotplug, validates\nfor default entry address 0x0 which doesn\u0027t account for platforms\nfor which 0x0 is a valid address. Added function to retrieve invalid\nentry address for default scenario and platform implementation to\nretrieve specific custom invalid entry address.\n\nChange-Id: I9f109acc8d0443dabd3088cb31852900e8e07853\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "2f2bd013021b4723d42c168f613c4c0ca37223bd", "tree": "968260569451b377582640305eea94d206d9a42c", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e", "af8934c8574fd64bef6ac4b0201c2144b78c8fd7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "message": "Merge \"test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\"" }, { "commit": "5bccf1d188115e268101024018d26b710c86d3c9", "tree": "a185504f6b740a4bfc63fc62f8ee8d91f08d4791", "parents": [ "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "message": "fix(realm): fix PMU save/restore registers\n\nRemove pmxevcntr_el0 and pmxevtyper_el0 registers\nfrom saving/restoring as aliases for pmevcntrN_el0\nand pmevtyperN_el0, selected by pmselr_el0.sel.\n\nChange-Id: I3def527c46d53c3203f7c3ebc565a2aaf282309c\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "tree": "010803c4d3fb8186d23cfd2f54f923c8271b45cd", "parents": [ "23ec8506918aff276b21b9543831d4825855906d", "82cd82e9868b1f381a5c8d84195657e1583cfca1" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "message": "Merge \"feat(rme): add tests for FEAT_MPAM on Realms\"" }, { "commit": "82cd82e9868b1f381a5c8d84195657e1583cfca1", "tree": "c7be244d493e784e55df370f501d8c3ba9275523", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jan 17 17:37:42 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Feb 04 15:01:14 2025 +0000" }, "message": "feat(rme): add tests for FEAT_MPAM on Realms\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6e138cbf121793bdaaa3a44824c0dbff74daced1\n" }, { "commit": "c398c8f7248e9aec29bbc41c94e41005d539863c", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jan 16 14:35:48 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Feb 04 11:38:28 2025 +0000" }, "message": "fix(realm): fix realm PMU tests\n\n- FEATURE_PMU_NUM_CTRS field in feature_flag was used\nto pass number of PMU event counters in realm creation.\nThe width of this field was set to 4, which was not\nenough to pass numbers \u003e 15 and was causing PMU tests\nfailures in FVP configuration with more than 15 event\ncounters implemented.\n- This patch removes all FEATURE_XXX macros for setting\nfeature_flag and replaces them with the corresponding\nRMI_FEATURE_REGISTER_0_XXX to match feature register 0.\n- In host_set_pmu_state() function was setting PMSELR_EL0\nto incorrect value 0 instead of 31 to select PMU cycle\ncounter for configurations with no event counters implemented.\n- Test host_realm_pmuv3_mul_rec() was running incorrectly\nwith number of event counters set to 0 or 31.\n- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0\ncan be constrained unpredictable depending on the\nvalue of PMSELR_EL0.SEL and number of accessible event\ncounters. See corresponding TF-RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573\nThis patch fixes host_set_pmu_state() and\nhost_check_pmu_state() functions to avoid unpredictable access\nto these registers.\nThis patch makes Realm PMU tests pass for all possible FVP\nconfigurations clusterN.pmu-num_counters\u003d[0...31].\n\nChange-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "042541196fbdd814a7c04ee4e24be94f1a2ab4ef", "tree": "0852b3939e094f0d2fd4b848f3ebb617bfa6efd0", "parents": [ "c8943ba881807922cb84e357461f5482475a47c3", "47078f35247dcb85f5a1ce8ea0bc52d3aee74451" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "message": "Merge changes I7c4ad397,I92e0aeef\n\n* changes:\n test(realm): fix multi rec PMU tests\n test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n" }, { "commit": "c8943ba881807922cb84e357461f5482475a47c3", "tree": "a951dd70d63e29f3616dc48935890f96c8b52fab", "parents": [ "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "message": "Merge changes from topic \"fuzzinit\"\n\n* changes:\n test(fuzz) adding fuzzing for vendor-el3 smccc calls\n test(fuzz) adding fuzzing for all SDEI calls\n test(fuzz): Capability for random inputs\n" }, { "commit": "0fa7d21bf97d14283ebf8c3df866cd05afaff91e", "tree": "b1927aea547dcd718dccc20301cbc301d986faec", "parents": [ "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jun 18 11:17:01 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 14:03:27 2025 -0600" }, "message": "test(fuzz) adding fuzzing for all SDEI calls\n\nadded constraints for all calls\nadded fuzzer feature to start at arbitrary call number\nadded fuzzer features for function exclusion, fuzzer starting/ending call\nworked on additional fuzzing for event_register\n\nChange-Id: I9814b8387ea9e0fb00b53adbdbe0f8429845924e\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" } ], "next": "47078f35247dcb85f5a1ce8ea0bc52d3aee74451" }