)]}' { "log": [ { "commit": "e04fce4d6420bc25b889d33dd678889978209956", "tree": "cd7d8c82285cc5ffd42b99f9f0e1661174689e61", "parents": [ "4bc0b124a708f7187839e8658bf65b4045396304" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 03 12:49:06 2025 -0500" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Apr 10 17:08:29 2025 +0200" }, "message": "feat(mbedtls): update mbedtls to version 3.6.3\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I4bfb546c351c30a6fc4d22f29bc03efad316df7d\n(cherry picked from commit d5bb5f6c82f7ebcf28dccbbfad058e27e207c14f)\n" }, { "commit": "4bc0b124a708f7187839e8658bf65b4045396304", "tree": "d327cf40a16d76c027e1f5fc314b2b2fe625bb02", "parents": [ "37b1037dbed1dec729f02e8d319a9d5ffafee38a" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Dec 17 09:14:50 2024 +0000" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Apr 10 17:08:18 2025 +0200" }, "message": "feat(mbedtls): update minimum version to latest MbedTLS v3.6.2\n\nUse the latest MbedTLS version 3.6.2 as the minimum to stay in\nsync with TF-A.\n\nChange-Id: I4c70ec87805a99ba0cfaf2c23cfea51133d0daf7\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n(cherry picked from commit d8092a550b85c6369aabf96430c9b06cc8444298)\n" }, { "commit": "37b1037dbed1dec729f02e8d319a9d5ffafee38a", "tree": "5b2eee768f2145f2d49840d5c7edee59a3695a34", "parents": [ "5066338f8b05659a7a86e3851b310dae33c18602" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 12:19:32 2024 +0000" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Apr 10 17:08:07 2025 +0200" }, "message": "feat(lib): add mbedtls support\n\nAdd support for compiling Mbed TLS from external source.\n\nThe Mbed TLS library is compiled from source pointed by MBEDTLS_DIR\nenvironment variable. Any TFTF test that includes mbedtls.mk will have\nsupport for mbedtls library. Note that by default the MBEDTLS_DIR will\npoint to the default submodule directory (ext/mbedtls).\n\nThis support is added for testing RMM capabilities related to\nDevice Assignment in RMM.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I0e386334078812e5ff5bdcffd4143732e0478b64\n(cherry picked from commit 23788fa84220f873a21f8bca53d973e240ae8740)\n" }, { "commit": "9a21efb69db15b3a6ccf85358b4c362554607833", "tree": "5ab1d933b39fa0b0407591dd3b134ac260715d75", "parents": [ "c4f53cd7820cbbcbf7fb5e6a5393b199c30077a2" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Feb 06 09:46:56 2025 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Feb 06 09:51:36 2025 +0100" }, "message": "test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\n\nTesting was conducted using FVP Version 11.26.11\non Cortex-X3, Cortex-X4, Neoverse-V2, Neoverse-V3\nand Cortex-X925. Additionally, negative testing\nwas performed on Cortex-X2.\n\nThis patch tests SMCCC_ARCH_WORKAROUND_4 [1] for CVE_2024_7881 [2]\n[1]: https://developer.arm.com/documentation/den0028/latest\n[2]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881\n\nChange-Id: I4c33b7a9372236ce3ef38f9d1786d5794bb7ddbc\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n(cherry picked from commit 43d421bb292984fdc56269fb3e87e619ca0892d3)\n" }, { "commit": "2162802763be49ffc68a4c23ae2663a67d50e22e", "tree": "be9b8d9137e426bc6b447ed4e5b3ec37ac7638d3", "parents": [ "5b8229cd99830d4d98671c96153d54f03c3dbcd4" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Feb 15 14:14:59 2024 -0600" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Mar 27 18:59:10 2024 +0100" }, "message": "refactor(errata_abi): update the cpu structs for errata ABI\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I4650a88003db2ded9277b35c7fc521026fe4a5d7\n(cherry picked from commit 7bb1c84eca3a7dc46051b75b6b1cf13046b88c92)\n" }, { "commit": "c6a3abf980d69e59c08a66a0f4743958c1de6092", "tree": "bee421ee4ad87734d661b3dcf6cb36f61e0d92c0", "parents": [ "092189660673eeac7de4514035033240fde95b42" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Oct 25 16:47:23 2023 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 02 21:36:07 2023 -0500" }, "message": "fix(interrupts): check support for ESPI before testing it\n\nIt is possible for extended range interrupts to be enabled by software\nbut the underlying hardware (GIC) may not support it. In such,\nscenarios check if the support exists before exercising the\nESPI functionality.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ibdf18be8403539c0ae9204309adc8a81dd0382d3\n" }, { "commit": "1768e59c3a6ac8d727ac012719b4b09947c8400d", "tree": "cc6ad04618bb60fb861bf3e7e4da2538c1a5cf42", "parents": [ "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue May 23 13:28:38 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:54 2023 +0000" }, "message": "feat(rme): add tests to check NS SME ID registers and configurations\n\nThese tests checks the functionality of RMM for NS SME support.\n- Create Realm and test ID registers specific to SME\n- Check if Realm gets undefined abort when it accesses SME\n- Check whether RMM preserves NS SMCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ia8ffd0188297a74c095dbadfb389add50c548e10\n" }, { "commit": "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581", "tree": "3e0552b2dae1f333abe34bddd7a4ea63c40f985f", "parents": [ "47b702c49a622e895d70104d78a20bb979dae229" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 06 16:31:19 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "feat(sme): add sme helper routines and add streaming sve support\n\nThis patch adds a few helper routines to set the Streaming SVE vector\nlength (SVL) in the SMCR_EL2 register, to enable/disable FEAT_SME_FA64\nand to get CPU\u0027s Streaming SVE mode status.\n\nThis patch also makes SVE compare routines compatible for both normal\nSVE and streaming SVE mode.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7294bb17a85de395a321e99241704066662c90e8\n" }, { "commit": "47b702c49a622e895d70104d78a20bb979dae229", "tree": "0d8eb64935c78a960998a4163c996f418c0fd96b", "parents": [ "92f1868013792ac13497d1045078b7e8a12d4f02" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 06 13:31:46 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "fix(sme): use rdsvl instead of rdvl\n\nUse rdsvl instruction to get Streaming SVE vector length instead of rdvl\ninstruction. When the CPU is in Streaming SVE mode both rdvl and rdsvl\ninstruction returns the same value but that is not true when the CPU is\nin Normal SVE mode. So it\u0027s preferred to use rdsvl to get SVL.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ieb6226f4fc275ee8a81eb359af465c26e307bc75\n" }, { "commit": "92f1868013792ac13497d1045078b7e8a12d4f02", "tree": "c94edb176be497ef790dfeaf98bb7b1e49cef824", "parents": [ "3dc2d746aa4bc44174a9981fa082c1473d0006a4" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Sat Sep 02 01:41:28 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:17 2023 +0000" }, "message": "fix(sme): enable SME/SME2 during arch init\n\nThis change enables SME/SME2 for nonsecure use at EL2 for TFTF cases\nduring arch_setup. This removes dependency on testcases to explicitly\ncall sme_enable or sme2_enable to access SME or SME2 functionality.\n\nThis change also adds CPTR_EL2 register in suspend context. CPTR_EL2\nregister is saved/restored in CPU suspend entry/exit path.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2c99fd49c48c1a9ff2110747714db858a78d3a32\n" }, { "commit": "3dc2d746aa4bc44174a9981fa082c1473d0006a4", "tree": "e62c636478dc937e944d7f236837096b535d3551", "parents": [ "ab2fe6b01abef3c4b17ffb2c6ee4759f6801e095", "40de8ec10f4d9925c24d2b9dd22822e0c8fd4224" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 12:08:26 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 31 12:08:26 2023 +0100" }, "message": "Merge changes from topic \"rmm-eac5\"\n\n* changes:\n feat(rmm-eac5): update RSI_VERSION, RMI_VERSION\n feat(rmm) : add api for rec force exit\n test(rmm-eac4): add testcase for CPU_ON denied\n" }, { "commit": "40de8ec10f4d9925c24d2b9dd22822e0c8fd4224", "tree": "30347a76b3f2429f8ab3d0f124526d860ee77503", "parents": [ "6bb95105b289a4d9015d74af7cb7254455b2344e" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Oct 12 21:45:12 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "feat(rmm-eac5): update RSI_VERSION, RMI_VERSION\n\nThis patch adds necessary support for RMI_VERSION\nand RSI_VERSION commands.\nMacro SMC_RSI_ABI_VERSION renamed to SMC_RSI_VERSION.\n\nNote.\nThis patch sets both RSI and RMI version numbers to\n1.0 as per RMM Specification 1.0-eac5.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If4eb14d93f657388e2fe64ceefee002403cc4ae8\n" }, { "commit": "6bb95105b289a4d9015d74af7cb7254455b2344e", "tree": "faf71d64251c88b5aa5caa5512a76eff62601851", "parents": [ "24597d136cc199d8399be2291fda2efb0a652741" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 02 13:21:37 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "feat(rmm) : add api for rec force exit\n\nadd api to force exit a rec\nadded testcase for force exit rec\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I56c70234e236c7d3615237d11c773bdb970012e3\n" }, { "commit": "24597d136cc199d8399be2291fda2efb0a652741", "tree": "686e70f45e398155a42fc811e6abad9eb2a84254", "parents": [ "a29e811d596794b5e135904be9033e9a1662507e" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 02 10:40:19 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "test(rmm-eac4): add testcase for CPU_ON denied\n\n- Testcase creates multiple rec\n- Host receives CPU_ON request from realm\n- Host calls PSCI_CCMPLETE with denied status\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie89b7a3b9603916275913a273751210350075e96\n" }, { "commit": "ab2fe6b01abef3c4b17ffb2c6ee4759f6801e095", "tree": "8285b1a38265e0fa5dd691874d8bf0cdd58aa93f", "parents": [ "406e19135f9fe88bb7794c60012759ca3fb3bdc8", "6e011646ae828f789fc8643e0e6a0c225130cd0c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 27 15:46:09 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 27 15:46:09 2023 +0200" }, "message": "Merge \"feat(handoff): add basic firmware handoff tests\"" }, { "commit": "6e011646ae828f789fc8643e0e6a0c225130cd0c", "tree": "d82ffdaee70f155372aac8519e8244d37f510a6f", "parents": [ "cdf525212326f8b453f22122dddc9d8bf0725981" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Sep 22 17:17:35 2023 +0100" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Oct 27 11:00:34 2023 +0100" }, "message": "feat(handoff): add basic firmware handoff tests\n\nAdd tests to sanity check information shared between BL31 and NS world\nusing the firmware handoff framework.\n\nChange-Id: I9d00292db7732157d0815e6159438c0db08551ad\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "f369717f93ee8d7e2c12460e71d335bc702e37b4", "tree": "ff959de9f2e05c711dae73bedf2e5b8a34d56f2b", "parents": [ "6e587999a0b2f3055d14e08b7bbcfa5735db9891" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Sep 04 15:04:46 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 15:07:15 2023 +0100" }, "message": "test(rme): check various SIMD state preserved across NS/RL switch\n\nThie test case verifies whether various SIMD related registers like\nQ[0-31], FPCR, FPSR, Z[0-31], P[0-15], FFR are preserved by RMM during\nworld switch between NS world and Realm world.\n\nRandomly verify FPU registers or SVE registers if the system supports\nSVE. Within SVE, randomly configure SVE vector length.\n\nThis testcase runs on below configs:\n* with SVE\n* without SVE\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I3fc755f75bdcdc8c24af0440d8a5f094beafca73\n" }, { "commit": "fa05bd9ea226541e860789443b8f68f8d8846390", "tree": "e63b0399f570e205112b27f7fd92b3d26cbb1a74", "parents": [ "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 14:36:53 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 15:07:14 2023 +0100" }, "message": "feat(sve): add helper routines to read, write, compare SVE registers\n\nAdd helper routines to read, write, write_rand and compare SVE\nZ, P, FFR registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to configure SVE vector length and\nhas to pass memory to read/write SVE registers.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I3fa064c76a498ee2348d92cba2544a6e50331e15\n" }, { "commit": "7e514f6a01af8af9e6f203b1406a3f5c3ea1f045", "tree": "68f9b32383bb80a3542368ebe9ffc15e4bba1c43", "parents": [ "035899729133080ffff3ed691ba65664c34f75ca" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 13:27:36 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:24:42 2023 +0100" }, "message": "feat(fpu): add helper routines to read, write, compare FPU registers\n\nAdd helper routines to read, write, write_rand and compare FPU state\nand FPU control/status registers.\n\nThese helper routines can be called by testcases running in NS-EL2,\nR-EL1, S-EL1 payload. The caller has to pass memory to read/write FPU\nregisters.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I10ae5487c9f58e46434c1bd5b42fd458ec755045\n" }, { "commit": "035899729133080ffff3ed691ba65664c34f75ca", "tree": "02a0b07c127329297d5c28e0683352357c8c0d8a", "parents": [ "73949a20b61def813b3265c2a6a330656bd001af" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 11:04:51 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:15:59 2023 +0100" }, "message": "fix(sve): represent sve Z0-31 registers as array of bytes\n\nCurrently each Z register is type defined as sve_vector_t but the helper\nroutine to write or read Z registers works based on current vector\nlength.\n\nIf test case defines \u0027sve_vector_t zregs[32]\u0027 and reads all Z registers\nusing sve_read_vector_regs() then zregs[n] might not corresponds to Zn\nregister unless the vector length is set to max value.\n\nThis patch also renames sve_vector_length_get() to sve_rdvl_1()\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I42955f8009bdd7f40d74c5a8d21d7c16ce6d761e\n" }, { "commit": "73949a20b61def813b3265c2a6a330656bd001af", "tree": "ab41f5043a87d13fcccbc8bf0473bc2817fa13a4", "parents": [ "cbfec24f12c205a8c827604864e2c51f7d419b33" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 05 12:01:05 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:15:55 2023 +0100" }, "message": "test(rme): check if non SVE realm gets undefined abort\n\nThis test checks whether a non SVE realm receives undefined abort upon\naccessing SVE register state or instructions.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2785488b1344cc4d59dde75e38d9e0d6f856af61\n" }, { "commit": "52b5f02cf50a79efdaf7bd6682e40a069dec04b7", "tree": "62b0019e05420486a64cfd7507fb4f2437fd4735", "parents": [ "699cd4feef98deb1e1d3bc95adc42a16da40052d" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Oct 12 22:02:29 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(rmm) : use shared data buf to pass arg to rec\n\nHost can pass arguments to rec using\nper rec shared buffer.\n\nChange-Id: Ic34acf6253031b3b5f184669084f15460b0fc5fd\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "8ce3053050bc37f5cfccadefd575a597ac86dd95", "tree": "bd9c9d8e6eeba40a81702f88e8cb3bcbb44b9abf", "parents": [ "550e3e88891507cd514fbd8f27d6ba6b8c5a3162" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 16 15:58:38 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(realm): add host call to flush realm prints\n\nadd new host call to push out realm print buffer\nbuffer is flushed after every print statement\n\nChange-Id: I6efa92a7c75ab7df4615a432802426de39d0032c\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "550e3e88891507cd514fbd8f27d6ba6b8c5a3162", "tree": "81485909f1376913447c3480d640f9717bb61de0", "parents": [ "cdf525212326f8b453f22122dddc9d8bf0725981" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Aug 16 13:20:11 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(rmm): add support for multiple rec and cpu\n\nChanges to support creating and\nexecuting multiple rec on multiple cpus.\nAdded per REC shared buffer between Host and Rec.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ib6dbd814ee9f68df4a53f9cfdc8b7f9c905c35fe\n" }, { "commit": "cdf525212326f8b453f22122dddc9d8bf0725981", "tree": "cb2921b3cfa538802547572d0e8ea360bc0eb309", "parents": [ "9b2f7db4f52d6f144641761b2d2b01644b2b6684", "9e267a0f899d699cb840572eb8fc12936ac49d03" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 20 18:49:36 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 20 18:49:36 2023 +0200" }, "message": "Merge \"test: exercise secure espi interrupt handling\"" }, { "commit": "9e267a0f899d699cb840572eb8fc12936ac49d03", "tree": "869431e9ca81b7a20027416704453766d7c10f56", "parents": [ "2f13adbc1ac240bdee4c901cbd0e09119f17fce4" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 11 21:25:26 2022 -0700" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 13 12:04:15 2023 -0500" }, "message": "test: exercise secure espi interrupt handling\n\nHafnium/SPMC added support for enabling interrupts in the extended SPI\nrange. With the help of an SiP SMC call that can pend an interrupt,\nthis patch adds a test to trigger an espi interrupt when cactus is\nrunning and ensure it is handled.\n\nAdditionally, a dummy device region node representing a fake\nperipheral has been added to the Cactus SP manifest. It is used to\nspecify properties of the interrupt in the extended SPI range used\nfor the above test scenario.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ief932c40e3abd33d619f2b144e61cae449147b27\n" }, { "commit": "5e07e7eb18d5b21e1e356b1d040fc9008b8ad221", "tree": "2340fad9f8c4ec95fc92dd649b1896f70241ffba", "parents": [ "d13d760570e9d0f640e8bd83bcfbc21240949156" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 14:36:09 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:08:49 2023 +0100" }, "message": "feat(cactus): use security state attribute\n\nCactus uses security attribute from memory transaction\ndescriptor in the shared memory related tests.\n\nChange-Id: I7c4f3ef2c72e36236d23e5a061e27a2ea60fa2d6\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "d13d760570e9d0f640e8bd83bcfbc21240949156", "tree": "a0b70191908599e7242033b0629d97c14c6ce5b6", "parents": [ "7043e2a82e3b271552744b46fd180c4bc011ccc3" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 14:19:03 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:08:49 2023 +0100" }, "message": "feat(ff-a): define memory security state attribute\n\nFF-A v1.1rel0 defines the security state attribute for the\nmemory transaction descriptor. Add respective definition\nto ffa_helpers.h.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Iefb510f5272587bc9faa96731af0159e2379576b\n" }, { "commit": "6e5c99643b199e064f1e8090d963671965ced1d7", "tree": "c5079b4d7de61ed810e5241021b5005d35990ba7", "parents": [ "92b99ee435ebafa5e503b19dce753079ad35218d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Oct 06 16:38:13 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 10 14:31:18 2023 +0100" }, "message": "fix(rme): append realm.bin at end of tftf.bin\n\nCurrently realm.bin is appended to tftf.bin at offset of 10 MB.\nThis patch removes this dependency by reserving empty sections\nfor realm image and dependencies, in tftf binary after\nall loadable sections (end of binary),\nand append realm.bin at end of tftf.bin later in build process.\n\nThe patch removes the need for TFTF to map memory corresponding\nto Realm payload dynamically at runtime.\n\nChange-Id: Iead2dc62ff2965cf7bb03e61c93e76df218da973\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "afffe3a45076fa46a8cd73b0923e06874c8ab135", "tree": "d751b1c0856b93b8e7730c825c614c64b444bad4", "parents": [ "6d8721db1753e0b9fc4252308186d5eb152252a8" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Sep 22 17:14:52 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Sep 28 15:15:38 2023 +0100" }, "message": "fix(spm): instruction permissions on memory sharing\n\n- FFA_MEM_SHARE the instruction access to be used shall be NX,\nhowever both sender and the borrower should leave it not specified.\n- FFA_MEM_LEND/FFA_MEM_DONATE the lender must specify the instruction\npermissions it wishes to receive on the retrieve request.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I0c6e49c30cbbca513644b592695f853bbdf1994b\n" }, { "commit": "4550b49db8ddf98e4445fdd121d3e2bed466b034", "tree": "040deae47b58fde8636d6e6b2e0d350eaaa8545f", "parents": [ "35b0fa999146f9b1fe12abb237f9eecec42030c8" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Jul 14 12:07:56 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:50:15 2023 +0100" }, "message": "fix(rme): remove RIPAS_UNDEFINED definition\n\nThis patch removes RIPAS_UNDEFINED definition\nand matches RMM-TF patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21987\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I26d6c5e6f7c1053d1b2a7688118e6175985be029\n" }, { "commit": "35b0fa999146f9b1fe12abb237f9eecec42030c8", "tree": "39051ad40d5b1f3415349f9c8a5998c7525380e9", "parents": [ "4067f8610d0d9e89bac0499f09bcbd89d904ff36" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Jul 04 16:24:14 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:50:00 2023 +0100" }, "message": "feat(rme): use RIPAS/HIPAS EAC 2 definitions\n\nThis patch:\n- Modifies HIPAS/RIPAS definitions\n as per RMM Specification 1.0-eac2. It matches\n the changes introdiced by TF-A RMM code patch\n https://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21822\n- Return value of host_realm_destroy_undelegate_range()\n changed from void to u_register_t to report errors in\n the code flow.\n- In \u0027struct rtt_entry\u0027 types of \u0027state\u0027 and \u0027ripas\u0027 fields\n changed from \u0027unsigned int\u0027 to \u0027u_register_t\u0027 to match\n the size of values returned by RMI_RTT_READ_ENTRY command.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ied80fb6e1cd4b2da392514ace33201ffd9fc1da9\n" }, { "commit": "4067f8610d0d9e89bac0499f09bcbd89d904ff36", "tree": "e8f75c7f51dbd6d4237c327a63641df9920b5eaa", "parents": [ "f81345ce2cd13d59cb6efa5847ec02baf54cd489" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Jun 12 12:22:37 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:49:49 2023 +0100" }, "message": "feat(rme): support for PMU as per RMM Specification 1.0-eac2\n\nThis patch introduces PMU changes as per RMM\nSpecification 1.0-eac2:\n- pmu_ovf, pmu_intr_en and pmu_cntr_en fields in RmiRecExit\nare replaced with a synthetic single-bit field pmu_ovf_status\nwhich reports the level of the virtual PMU input to the GIC.\nThis field also includes the state of PMU Enable bit PMCR_EL0.E.\nThese changes match RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21434\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I4135c62927e8156931af9a43a665a19d0e90b342\n" }, { "commit": "f81345ce2cd13d59cb6efa5847ec02baf54cd489", "tree": "ca115e7029fc8f338a96f41ce044583aafa3bc2f", "parents": [ "cd04e41b418decee80a03d25eb7598e7a6b8da95" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 07 17:30:10 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:49:37 2023 +0100" }, "message": "feat(rme): add Realm SVE tests for EAC1\n\nThis patch adds SVE tests for RMM EAC1.\nThe \u0027feature_flag\u0027 parameter passed to\n\u0027host_create_realm_payload()\u0027 function is modified\nto contain \u0027sve_vl\u0027, \u0027num_bps\u0027, \u0027num_wps\u0027 and\n\u0027pmu_num_ctrs entries\u0027. This allows to pass values\nwhich can exceed these fields in feature_register_0\nfor testing. It makes possible to pass\n\u0027Create SVE Realm with invalid VL\u0027 which was\nskipped originally, when SVE was configured with\nthe maximum supported vector length value.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Icd5e57c1bb0cb8dee27b7ace5643aec597e036c1\n" }, { "commit": "1e44db50fb7d1f04c072865e879e7cd5b44a02b8", "tree": "456759fe83f4c0f99e90697dc3af29a52a4576ee", "parents": [ "81025b4c9789e0721db8efcacb7632946d2d108c" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Apr 19 17:26:51 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:45:23 2023 +0100" }, "message": "feat(rme): update API of data/rtt functions\n\nThis patch modifies API of host functions calling\nRMI_DATA_DESTROY, RMI_RTT_DESTROY and RMI_RTT_FOLD\ncommands according to RMM Specification 1.0-eac1.\nIt matches changes in RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20604\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I4410ea1cdbc093359b22a0a9495167efbe443c85\n" }, { "commit": "81025b4c9789e0721db8efcacb7632946d2d108c", "tree": "3f27881f023ff485cd6c90d81741565aad4fad86", "parents": [ "ac174ab64b45ee0d943c1e9c60edae5a0e294c77" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Apr 18 11:55:04 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:43:33 2023 +0100" }, "message": "feat(rme): remove RMI_VALID_NS status\n\nThis patch removes RMI_VALID_NS s2tte status as per\nRMM Specification 1.0-eac1, it matches RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20581\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Idcf4f421ec8d4d89d441986f50694c82877b3755\n" }, { "commit": "ac174ab64b45ee0d943c1e9c60edae5a0e294c77", "tree": "f4f637dfcea9bf6c14cfb9de626a4abef8f85963", "parents": [ "3d3dea2c3712b9b3f6b69b1690a6c73aeefc9a3e" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 16:35:22 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:43:21 2023 +0100" }, "message": "feat(rme): remove RMI_ERROR_IN_USE error code\n\nThis patch removes RMI_ERROR_IN_USE error code,\nas per RMM Specification 1.0-eac1, no functional\nmodifications are made.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ia911f9ba07b69d384bbd910f4b4dd3b68646c98a\n" }, { "commit": "44927c3293c656b878ef1c93e1c8cc4dc92944af", "tree": "1bc325c1ab0b86418f58b3c5159a66066709e719", "parents": [ "b69eae0e22dde3487cc0edcf0c8d2e092f54cf13" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 15:17:13 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Sep 12 16:55:14 2023 +0100" }, "message": "feat(rme): pass RD pointer in arg0 register X1\n\nThis patch makes changes according to RMM Specification\n1.0-eac1 for passing RD pointer in arg0 for RMI_DATA_CREATE,\nRMI_DATA_CREATE_UNKNOWN, RMI_REC_CREATE and RMI_RTT_CREATE\ncommands.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ia19baaf59209b2de06d63cd392c53e3ee19e3ec9\n" }, { "commit": "b69eae0e22dde3487cc0edcf0c8d2e092f54cf13", "tree": "19a9dc33bef7c68b8de1efe361bbd1f7b30434ef", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 10:27:58 2023 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Sep 08 12:24:42 2023 +0200" }, "message": "feat(rmm): modify rmi_realm_params structure\n\nThis patch modifies rmi_realm_params structure\naccording to definition of RmiRealmParams in\nRMM Specification 1.0-eac1.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I63c3097290004de90cd2222b24419aef517d9b49\n" }, { "commit": "507ed939b32d26244412af3f6253a7adcc22420c", "tree": "e47b85a68d09cea2d4b9d29998c2893141ece874", "parents": [ "c94fb400ec40a8550a89cd484bd1137dca029336" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Jul 10 16:09:31 2023 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Thu Aug 24 11:08:53 2023 -0500" }, "message": "refactor(fgt): modify FEAT_FGT test to check for init values\n\nThe original test checked only if FEAT_FGT was enabled. This new version\nof the test also checks whether the values of registers HFG*_EL2 are the\nvalues used during initialization.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I17673b813da7f14ef03349eead2c0a47cf3a8b26\n" }, { "commit": "c94fb400ec40a8550a89cd484bd1137dca029336", "tree": "863c7398f9252136f958d03c3b6d6ce5fc781ec1", "parents": [ "c68ba0dec2989735fa24a8ed4efcf9cd76af2b05" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri Jul 21 17:19:42 2023 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Thu Aug 24 11:05:53 2023 -0500" }, "message": "feat(cpufeat): add feat detection helpers\n\nThis patch adds multiple feature detection helpers, useful for\ntests that need to check for the presence of those features.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ie6d39b9e9c8d28d0a4cd9d02350e2bedd016e45e\n" }, { "commit": "9f864523cb2a5a3581b7f5a0b99410838b7cb9bd", "tree": "f8c0446f05fe4e4664f375b846b3952f29473a0b", "parents": [ "ab5321a53201619be2be50b9b0d14cd2fee51299" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Sun Apr 23 16:19:10 2023 -0700" }, "committer": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 03 07:08:20 2023 -0700" }, "message": "test: add discovery of el3 spmd logical partitions\n\nThis patch adds a test to query the presence of an SPMD logical\npartition and also tests basic functionality using the\nffa_partition_info_get_regs abi. Note that the register based discovery\nreports the presence of el3 spmd logical partitions whereas the memory\nbased discovery interface does not report the el3 spmd logical\npartitions. To that end, the patch adds helper functions to use the\nregister based discovery, and also refactors code that can be shared\nbetween the register and memory based interfaces.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nChange-Id: I755ffe4098c635de2c6aeb0ebe73eb16c3acd206\n" }, { "commit": "ab5321a53201619be2be50b9b0d14cd2fee51299", "tree": "2b15c3c77a8dac037f83b588ce4c9680ac5c7abc", "parents": [ "868c623c786b9c403df1eb57515c828e0b2e8982" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Sun Apr 23 16:14:28 2023 -0700" }, "committer": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 03 07:08:20 2023 -0700" }, "message": "feat(ff-a): partition information via registers\n\nThis patch enables basic support for getting partition information via\nthe ffa_partition_info_get_regs abi. This interface can be used to query\npartition information in the absence of rx/tx buffer or when using\nmemory is inconvenient (such as early boot loaders etc). The patch adds\nthe required calls, a few helper functions and enables the use of x8-x17\nas return values, that is required for this abi to work.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nChange-Id: I70ed78e809a5bf77d77a49e5bc122c1989303ebb\n" }, { "commit": "229d8a4c5d118db288325e3390278bc17d2f25ef", "tree": "74b83622d50166d19c842b0db9eaab4f64782b43", "parents": [ "84986d5d9f95d6a300339f94e05003267a743e02", "82bf339c9e178e8200f763146f2f21abee9410ea" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 01 15:54:46 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 01 15:54:46 2023 +0200" }, "message": "Merge \"fix(spm): stop spm from being built for in aarch32\"" }, { "commit": "82bf339c9e178e8200f763146f2f21abee9410ea", "tree": "d37718c9f321f866fbe0480ea758fb5175a5c032", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jul 28 18:32:27 2023 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Mon Jul 31 16:59:23 2023 +0100" }, "message": "fix(spm): stop spm from being built for in aarch32\n\nHafnium does not support Aarch32 therefore we do not want to build\nin this case. Move spm related test helpers into their own file\nand add FF-A tests to the aarch32_tests_to_skip.txt file\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ic5a83ddf4aae2b7dd4b1c30e4cc76b0447e5b405\n" }, { "commit": "9d0cfe88aedc34f1b61a51ff18013743c56e2fbc", "tree": "b5b65d1a477d3d46aacfb69bd3dff348a2136ce4", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Apr 17 10:57:26 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Jul 25 17:00:33 2023 +0100" }, "message": "test(tftf): test PAuth in Realm\n\n- Enable PAuth in Realm RL1 by default.\n- Check if PAuth keys are accessible in Realm RL1.\n- Check if Realm PAuth keys are preserved across RMM entry/exit.\n- Check if NS PAuth keys are preserved across RMM entry/exit.\n- Generate PAuth fault by cloberring LR.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I85d8e03ec604c96117555e7aa866453cb2745cfe\n" }, { "commit": "d648077f8284ada21b03871ce06bf568a2333bbd", "tree": "b2307d260395753bd714732500f51cd1f307f1ff", "parents": [ "baed8dd3577633768837048cb71351fb135d59ee" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Feb 27 13:23:06 2023 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 13 13:58:31 2023 +0200" }, "message": "feat: introduce SError exception handler\n\nIntroduce SError exception handler along with support to register a\ncustom handler. The default behaviour is same as before if no handler\nis registered.\nThis patch will allow tests to do a graceful exit after handling an\nSError.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Idbe37d3690e3a8e08fa3b0dff496d18d3022a8fc\n" }, { "commit": "2a32ff7161ef8711f9e7420c499a246e3d055f42", "tree": "041037f8c7b3126163c8988fd8041712da8447ff", "parents": [ "ec59c59afc953c306a4b83e919a787694ee6a88f" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu May 25 17:51:48 2023 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Jun 06 11:00:21 2023 +0100" }, "message": "feat(xlat): add support for 52 bit PA size with 4KB granularity\n\nThis patch adds support to the xlat library to for 52Bits of\nPA size with 4KB granularity (FEAT_LPA2). The patch only reports\nthe right granularity when it supports FEAT_LPA2 and it does\nnot enable the feature.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: Iee0cab8e1f8844a6af135771d8f940ec7e1dce84\n" }, { "commit": "5270d01e968b1b0a8b853a9263e767a467e541b9", "tree": "ac67959df7b5d536b4c662ed1f0a0e2f19970980", "parents": [ "c1136a849fc21470313e4e852a22ae4b9db50440" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 19 14:53:42 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed May 24 13:40:42 2023 +0100" }, "message": "tftf(rme): check if RMM doesn\u0027t leak Realm contents in SVE registers\n\nThis test verifies that the Realm contents in SVE registers are not\nseen by NS world once the Realm returns back to the host. This test\nperforms the below steps:\n\n1. Set NS world SVE VQ to max and write a known pattern.\n2. Set NS world ZCR_EL2 with VQ as 0 (128 bits).\n3. Create Realm with max SVE VQ\n4. Call Realm to fill in Z registers\n5. Once Realm returns, NS sets ZCR_EL2 with max VQ and reads the\n Z registers.\n6. The upper bits of Z registers must be either 0 or the old values\n filled by NS world at step 1.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I8205190d1ce9c37b99d35cf5b15df21ca9b838c3\n" }, { "commit": "c1136a849fc21470313e4e852a22ae4b9db50440", "tree": "b6b5e8854589497f4e2d2c159f0bd2e590dcd8c5", "parents": [ "d179ddcc64cac3b319b301cfe6c1bc32c1ea0eaf" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 12 15:24:44 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed May 24 13:40:42 2023 +0100" }, "message": "tftf(rme): intermittently switch to Realm while doing NS SVE ops\n\nInterleave NS SVE operations with Realm SVE operations and check whether\nSVE vectors are not affected.\n\nThis test also configures SVE op array and SVE vector length with random\nvalue in NS and Realm for test each iteration.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7a9ba4bd0d298f187baa3048ec622eb97ec3d99f\n" }, { "commit": "d179ddcc64cac3b319b301cfe6c1bc32c1ea0eaf", "tree": "f7ff4f156a0bf64c0f186e057dea7243ecc3ab8c", "parents": [ "0bbdc2dff449036aa65e4c53cd351d01484e0d23" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 12 10:41:42 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed May 24 13:40:39 2023 +0100" }, "message": "refactor(sve): move sve operations to a lib routine\n\nThis patch moves the SVE subtract operation to a common sve library\nroutine and takes a callback function that does the world switch while\nSVE operations are done in a loop.\n\nThe callback is invoked after z0, z1 vectors are loaded and before\nthe calculated results are stored back in the vector registers.\n\nThis refactoring later helps to use this function to do context switch\nfrom NS to Secure world or from NS to Realm world based on the\ncallback type.\n\nThis patch also moves the SVE fill vector registers, read vector\nregisters to a common sve library routine.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Iceb34b96fa85597be63a50c429ae0eb29f8fcaf8\n" }, { "commit": "0bbdc2dff449036aa65e4c53cd351d01484e0d23", "tree": "60f35abe7f72ade6409b3ffcd46262502a9b6885", "parents": [ "ed7cdc8b28137ab15d9f263825674d156b3c2b30" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 05 15:30:18 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu May 18 16:08:39 2023 +0100" }, "message": "feat(rme): add SVE Realm tests\n\nVerifies Realm with SVE support. Below tests are added\n- Check whether RMI features reports proper SVE VL\n- Create SVE Realm and check rdvl result\n- Create SVE Realm with invalid VL and check if it fails\n- Create SVE Realm and test ID registers\n- Create non SVE Realm and test ID registers\n- Create SVE Realm and probe all supported VLs\n- Check RMM preserves NS ZCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I98a20f34ce72c7c1a353ed13678870168fa27c48\n" }, { "commit": "073842171ae9d91b3bdc2031905faafabc7abe57", "tree": "d1b64e32752d2bd8ca31004cb2ee7955f4b7d6ad", "parents": [ "83fe74900c440b2728c458efd8b1c57be20ba039" ], "author": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Mon Nov 28 13:19:11 2022 -0600" }, "committer": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Mon May 08 18:19:04 2023 -0500" }, "message": "Add tests for Errata management firmware interface.\n\nAdd tests to confirm that the em_version, em_features and\nem_cpu_erratum_features calls conform to the errata abi spec.\n\nSigned-off-by: Sona Mathew \u003cSonaRebecca.Mathew@arm.com\u003e\nChange-Id: I8395026acc004a10d8c2c17ec689f4e0752143d8\n" }, { "commit": "6c6bc8ab7d93014fc6b3c7ee0c23c0afdebabf9c", "tree": "65a7c9ba3c70edd635a43d4aa869508a4bee6a07", "parents": [ "2dfb70fe3614b818bc86b247cf84230ec4c93afc" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri May 05 17:34:05 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri May 05 17:49:56 2023 +0100" }, "message": "fix(tftf) : add alignment to FPU state structure\n\nThis patch adds 16 byte alignment to FPU structure.\nWithout this change, the load/str instruction for\nFPU might fail depending on compiler.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If41f1625218c47f7801be80a3532ff782525d5ad\n" }, { "commit": "369955abac0a083f57bfb787eeda82a511eb8fc0", "tree": "54a35fd1b033a708569c91f2dfb1e1516d690cec", "parents": [ "38133fa69bfefab6e3d1d7461b42c806d36ae33b" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Apr 19 18:05:56 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri May 05 13:56:12 2023 +0100" }, "message": "test(tftf): test FPU state registers context is preserved in RL/SE/NS\n\nTest that FPU/SIMD state are preserved during a randomly context switch\nbetween secure/non-secure/realm(R-EL1)worlds.\nFPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers,\nthe test runs for 1000 iterations with random combination of:\nSECURE_FILL_FPU, SECURE_READ_FPU, REALM_FILL_FPU, REALM_READ_FPU,\nNONSECURE_FILL_FPU, NONSECURE_READ_FPU commands,to test all possible\nsituations of synchronous context switch between worlds, while the\ncontent of those registers is being used.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I6da5fd334777000111924bb1239b77123a3dcea6\n" }, { "commit": "38133fa69bfefab6e3d1d7461b42c806d36ae33b", "tree": "3a4ff89fad7a2c24f9d61c1cf28e0d073310ea05", "parents": [ "27479ee85d80268db99f77eea033a691a0bfda56" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Apr 19 17:00:38 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri May 05 13:55:50 2023 +0100" }, "message": "refactor(tftf): move SIMD/FPU save/restore routine to common lib\n\n- Move FPU routines to common lib\n- FPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers\n- Test that FPU/SIMD state are preserved during a context switch\n between secure/non-secure.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I88f0a9f716aafdd634c4eae5b885f839bb3deb00\n" }, { "commit": "525ec410c0dc991d1470084747a8f31a17f09841", "tree": "028b2c2d7237e5da5fd4be83365633e6438e24f8", "parents": [ "0c762d408014fe03ca648296ffdeee47842c47cf", "4b22111264f612da90789dc207d2c874817d9291" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu May 04 17:34:53 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 04 17:34:53 2023 +0200" }, "message": "Merge \"refactor(rme): add helper macro for RME tests\"" }, { "commit": "5688e77bb01b2af8efa848771f6570f006247079", "tree": "3133572c6430bbe4b37260b192bf28b5e2374f86", "parents": [ "03b60a805e64023c0bccc8ce1105261f1d4aa644", "be3bb7e18df9e944ff5132a03cd45897510444e6" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue May 02 22:53:27 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue May 02 22:53:27 2023 +0200" }, "message": "Merge \"feat(hcx): modified test to also check for reset value\"" }, { "commit": "be3bb7e18df9e944ff5132a03cd45897510444e6", "tree": "ceb09bc5e84f70aba9c8f7bfe6ac93fcdd6bc114", "parents": [ "8d80d6501af8a903b9a828ee57a6f490fc89bc18" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Wed Feb 22 10:18:14 2023 -0600" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri Apr 28 14:00:13 2023 -0500" }, "message": "feat(hcx): modified test to also check for reset value\n\nPrevious test only checked for the presence of FEAT_HCX.\nHowever, as register HCRX_EL2 is initialized in EL3,\nthe value read from it should be its reset value.\n\nAs the test already existed, there is no new CI config.\nIt can be run by using test group:\ntftf-l2-fvp/fvp-hcx-aarch64-only,fvp-hcx:fvp-tftf-fip.tftf-foundationv8\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I7fcd3d868fa4a7b4aee53fe3b141e8da1f670c0a\n" }, { "commit": "4b22111264f612da90789dc207d2c874817d9291", "tree": "bebdd61a896deb479ef7598e9fc8f2f0f3615071", "parents": [ "2a856b5f0b1e9b9183292fb44d3def6fdd69ee7c" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 05 14:19:03 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Fri Apr 28 11:40:15 2023 +0100" }, "message": "refactor(rme): add helper macro for RME tests\n\nThis change adds SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP macro that\nchecks if FEAT_RME is present and RMM is not TRP.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I100e713d8f4fce2826e60909580079834585fddb\n" }, { "commit": "95d5d2764c2f44b06af709dd093e9ff0f17ced14", "tree": "b0d3d8d67c94521b107522dac8631e13bc90b9f8", "parents": [ "b3ffd3c17ea83c48a90d7165ab5c5140540bc81f" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Jan 16 17:58:47 2023 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Apr 28 00:51:01 2023 +0100" }, "message": "feat(sme): add basic SME2 tests\n\nFEAT_SME2 introduces an architectural register ZT0 to support\nlookup table feature. This patch ensures that EL3 has\nproperly enabled the SME2 for use at lower exception levels,\nthereby disabling the traps execution at lower exception levels,\nwhen instructions access ZT0 register to EL3.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I46d51184b74c1e82c88344530601f2a3c1aee8ea\n" }, { "commit": "b3ffd3c17ea83c48a90d7165ab5c5140540bc81f", "tree": "ae9e356822c85c2d410e761150dcc5fdce6ddb09", "parents": [ "d6325a6dee06c281d90e875bc5df2ca4fba9d7f5" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Feb 13 12:15:11 2023 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Apr 28 00:50:50 2023 +0100" }, "message": "feat(sme): update sme/mortlach tests\n\nFEAT_SME is an optional architectural extension from v9.2.\nPreviously due to the lack of support in toolchain, testing\nSME instructions were overlooked and minimal tests were added.\n\nThis patch addresses them, with additional tests to test\nthe SME instructions. In order to avoid toolchain requirements\nwe manually encode the instructions for accessing ZA array.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: Ia9edd2711d548757b96495498bf9d47b9db68a09\n" }, { "commit": "cd66846bce520895b901fa384d61157d70902944", "tree": "ba6abe80cb997cd79bbdb9f777e300aebcdd0db8", "parents": [ "eb95d1a202832e834d231c9a40ec6bd628d0590f" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Sun Nov 06 15:29:44 2022 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Apr 24 14:10:10 2023 +0100" }, "message": "test(tftf): test Secure interrupt can preempt Realm EL1\n\n- Send a direct message request command to first Cactus SP to start the\n trusted watchdog timer.\n- Create and execute a busy loop to sleep the PE in the realm world for\n REALM_TIME_SLEEP ms.\n- Trusted watchdog timer expires during this time which leads to secure\n interrupt being triggered while cpu is executing in realm world.\n- Realm EL1 exits to host, but because the FIQ is still pending,\n the Host will be pre-empted to EL3.\n- Once the SP handles the interrupt, it returns execution back to normal\n world\n- TFTF parses REC\u0027s exit reason(FIQ in this case)\n- TFTF sends direct message request command to first Cactus SP to query\n last serviced interrupt and verifies it is Trusted watchdog interrupt.\n- TFTF disables watchdog and destroys Realm payload on exit.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: I6f4cfd334777000d33924bb1239b77182a3dcea6\n" }, { "commit": "eb95d1a202832e834d231c9a40ec6bd628d0590f", "tree": "8b5a4b63a345ccca05bfbf1e9577a537d51af90b", "parents": [ "cd6fdd5c6b8fe046ac43438577ae88269205f956" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Sun Nov 06 15:18:06 2022 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Apr 18 02:35:34 2023 +0100" }, "message": "refact(twdog): move trusted wdog API to spm_common\n\nOther tests cases need same API to enable/disable twdog,\nso we need to move them to common place.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: Ie54cfdf44777000dda924bb1239b77182a3dced9\n" }, { "commit": "b42d17f3028e759bb38e2e09430dd2b8a7ad1c34", "tree": "a89bfc7eb19d812ae18f728bcc19d6a353b69c3c", "parents": [ "79fc9196228a9aa2fd6832b1cd4275932871d95c" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 04 12:42:13 2022 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Apr 13 09:43:33 2023 +0100" }, "message": "feat(ff-a): memory share bump to v1.1 EAC0\n\nHafnium was updated to match FF-A v1.1 EAC0 [1].\nThis is the equivalent change for FF-A memory sharing\ntests.\n\n[1] https://review.trustedfirmware.org/c/hafnium/hafnium/+/15012\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ibf39ac35e1c7e336843be848fb389401dd792516\n" }, { "commit": "79fc9196228a9aa2fd6832b1cd4275932871d95c", "tree": "9a8416096f7b636165244ad0e6bbc2b8d0877c49", "parents": [ "fc5e23eb867be79cca7200314f9937baf14b80c8", "31b81775100595e7345fc836d5c83b4d7422f8f8" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Apr 05 09:19:44 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Apr 05 09:19:44 2023 +0200" }, "message": "Merge \"feat(memory share): FFA_FEATURES(FFA_MEM_RETRIEVE_REQ)\"" }, { "commit": "31b81775100595e7345fc836d5c83b4d7422f8f8", "tree": "4e1231d2af58033bf108eb310e8b52c73b8f3020", "parents": [ "957863b79430bc89c0894a677190b3a78855515b" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Mar 14 15:38:17 2023 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Mon Apr 03 13:07:52 2023 +0100" }, "message": "feat(memory share): FFA_FEATURES(FFA_MEM_RETRIEVE_REQ)\n\nUpdates tests to pass when built against\nhttps://review.trustedfirmware.org/c/hafnium/hafnium/+/18909\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: Ic6c39ca6916b9f9298d7668021963fec287b72c8\n" }, { "commit": "fc5e23eb867be79cca7200314f9937baf14b80c8", "tree": "45b69e1ca06d393b1f58d9cd4b16f86bde8a65c5", "parents": [ "8371bb91c1a039e01454cbb4e98bfdb564a8fc16", "cb88add07daff59486f850be6b4cd4750f94d97c" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Sat Apr 01 16:22:24 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Apr 01 16:22:24 2023 +0200" }, "message": "Merge \"test(psci): add tests for OS-initiated mode\"" }, { "commit": "2f30f1030f186760b20cd06b59832e332b2bdd0a", "tree": "e06899ba1be405650b4a15603429900dac67ccc2", "parents": [ "2eb601b98a245df8a31e670a7dc322c2e8f153cf" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Mar 13 19:37:46 2023 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Mar 31 11:41:56 2023 +0200" }, "message": "feat(rme): add PMU Realm tests\n\nThis patch adds Realm PMU payload tests with\nPMU interrupt handling.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2\n" }, { "commit": "cb88add07daff59486f850be6b4cd4750f94d97c", "tree": "3737ad2a8a2aa4c4d9e8d4eea54720009ca4e94a", "parents": [ "e0400c6d2b0372d742cd2cda9aaa7c5cf4741c4a" ], "author": { "name": "Wing Li", "email": "wingers@google.com", "time": "Sat Oct 29 02:32:06 2022 +0100" }, "committer": { "name": "Wing Li", "email": "wingers@google.com", "time": "Thu Mar 23 19:37:52 2023 -0700" }, "message": "test(psci): add tests for OS-initiated mode\n\nChange-Id: I33e135f659aea600f71e053ac3db57eb0172e22b\nSigned-off-by: Wing Li \u003cwingers@google.com\u003e\n" }, { "commit": "08b78604af08378bfa587eaeaf7092770bf9c20d", "tree": "5ca074e6b99e3e908e241a4fc23c78800914a318", "parents": [ "d17c6113997733fb39606aa3c3643896248ac44d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jan 24 15:54:50 2023 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 26 10:44:54 2023 +0000" }, "message": "fix(ff-a): tftf handling of its RXTX buffer pair\n\nThe way tftf was handling the RXTX buffer pair created a dependency\non a set of tests from \u0027test_ffa_setup_and_discovery.c\u0027. This was\nproblematic for test configurations for which the SPM tests are\nnot present.\n\nThis patch removes such dependency:\n- Delete the \u0027INIT_MAILBOX\u0027 macro, and \u0027init_mailbox\u0027 function;\n- RXTX buffer pair allocated within the \u0027get_tftf_mailbox\u0027.\nThey are mapped into the SPMC via FFA_RXTX_MAP, and are returned\nin the function\u0027s argument.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ia010ebd21f11ab7ca6582b574ffc9179693b1eed\n" }, { "commit": "c21694de5a14d1b4d32f0fd56cc6cf67750912de", "tree": "206ab841c46c74c2911c34384f8dc8cb3578e214", "parents": [ "17df525fd6be6db49f48f01c5cf26fd2a1279231" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Dec 16 12:19:52 2022 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Dec 16 13:32:45 2022 +0100" }, "message": "fix(tftf): align with RMM bet0 return code\n\nUpdate test cases return codes according to\nRMM Bet0 Specification. These changes are based on\nhttps://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/17892\n\nThis patch also fixes failure of\n\u0027Access from a SP to a Root region\u0027 tests when SPMC\nis not present.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I340f2b3bcee2b072f3874fd6a9f211b48ddf882b\n" }, { "commit": "953653743aaf56c979b71e211800cf1bee6c4e34", "tree": "31c5a7d0502c2a08710a7bb9dd5873ab3c05cf10", "parents": [ "884883bfa0b26a37d9b61b935f4699add050bf8d", "380b2affda50fe487239f490026517e1bc35709f" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Dec 15 15:51:54 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Dec 15 15:51:54 2022 +0100" }, "message": "Merge \"feat(tftf): TFTF Realm extension enhancement\"" }, { "commit": "380b2affda50fe487239f490026517e1bc35709f", "tree": "212567970ee50d84a7054cd2d171d538d5c814fd", "parents": [ "f7b3be91ab954c495912fc7bc48383cd83bfec2d" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Nov 23 17:31:27 2022 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Dec 07 16:21:21 2022 +0000" }, "message": "feat(tftf): TFTF Realm extension enhancement\n\nAdds randomisation of SMC RMI commands parameters\nand checking of X4-X7 return values as per SMCCC v1.2.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I7a332db873d2bd6cb400c5bf97ef0b8e9792b2d4\n" }, { "commit": "35e3ca03ea641e61bb9e8dafc25fcb2d577c6ac8", "tree": "ec0ce15d0f947ca27bda67f5c8dd0e170569597d", "parents": [ "ba3f3f37a6a8952e416eaf2726f771fe794dceaf" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 10 16:39:45 2022 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Dec 06 16:08:17 2022 +0000" }, "message": "test(pmu): check if PMUv3 is functional\n\nThe PMU is tested for secure world leakage but there are no checks\nwhether it works in the first place.\n\nThe counter and event counters are exercised separately. This is because\nthe functionality of one does not imply the functionality of the other\n(EL3 has separate controls for both). This additionally catches a corner\ncase with FEAT_HPMN0 missing without failing all tests.\n\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I966d3155cdd6edfde01af32f7c50c3bb3644274a\n" }, { "commit": "ba3f3f37a6a8952e416eaf2726f771fe794dceaf", "tree": "ce9f9af1e1de617fc62f1d0b9680704c26cb0420", "parents": [ "69b18fe71ea8aa0334ff9fb641dc68a4b2def6c8" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 10 16:33:10 2022 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Dec 06 16:07:44 2022 +0000" }, "message": "fix(pmu): extend PMEVTYPER.evtCount width\n\nFEAT_PMUv3p1 extends this field from 10 to 16 bits. The upper bits are\nRES0 so backwards compatibility is preserved\n\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I98abb14bfe8e72f99318fe7d3e26420d91c1c55a\n" }, { "commit": "69b18fe71ea8aa0334ff9fb641dc68a4b2def6c8", "tree": "cc0d3574c8bf21ccb5ca9e93e1d3b3121450c53b", "parents": [ "4ca852f826e4b1e43739493c4d0916a426a8722a", "41bce21cb52e088f988ca2a5a5d67c0fa3ba049c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Dec 06 16:58:27 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Dec 06 16:58:27 2022 +0100" }, "message": "Merge \"feat(spe): add support for more SPE versions\"" }, { "commit": "7774d6e975aabe01903b7ca9d7557386f4502bf6", "tree": "a36639a7089b3c898021af58c5208eb109d8a66c", "parents": [ "93eb010ed1008d0f4e4291104484b7d3ba09e18a" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Wed Nov 23 19:06:21 2022 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Nov 28 12:31:22 2022 -0500" }, "message": "test(ff-a): check execution state property of partitions\n\nFF-A Version 1.1 adds several additional flags to\nthe properties field of the partition information\ndescriptors. Test that execution state flag is set\nwhen FF-A v1.1 is specified and zero when FF-A v1.0\ndescriptors are being used.\n\nCurrently only 64-bit execution state is supported for\nFF-A compliant partitions.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ice1b9a5a417e89cb26dd642be49348e8bfa282b9\n" }, { "commit": "40777f82efb1854ab815f501059ac58430cba888", "tree": "349cef469973eb41ef7a58e914baeb57a67d5284", "parents": [ "f7b3be91ab954c495912fc7bc48383cd83bfec2d" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Nov 09 10:15:28 2022 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Nov 22 13:36:28 2022 +0100" }, "message": "refactor: remove deprecated spm libs and test code\n\nRemove references to former SPCI/SPRT implementation pre-dating now\nreleased FF-A specification.\nRemove the sample quark partition image based on those deprecated\nspecifications.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I5b4e51457307c4ff5befd46132fd26d4ef21cdfa\n" }, { "commit": "41bce21cb52e088f988ca2a5a5d67c0fa3ba049c", "tree": "c55450ab46f5fe944c72786c77330a82fea1ee82", "parents": [ "4492ba63d93fad8bc40348414799e5560b15f60a" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Nov 17 12:34:40 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Nov 17 15:53:06 2022 +0200" }, "message": "feat(spe): add support for more SPE versions\n\nFrom Armv8.8, more SPE versions are supported, such as FEAT_SPEv1p3\nand FEAT_SPEv1p4. Included these versions in the test case.\n\nAlso, moved enum and function to appropriate header.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I5d2999068e619aa5fdad104bbe0177dcedcd0d8c\n" }, { "commit": "6941bdf96b402704e5234a43da5099972dcce946", "tree": "d2d90d37b2878824cf7fd0d1f86fad6dd4faa77b", "parents": [ "ca3380a5e774d5ccfd45299a926cb5406be2fd20", "002e569021f2e219456d02dfe239218eba5c7cfa" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 10 11:38:52 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 10 11:38:52 2022 +0100" }, "message": "Merge \"feat: tftf realm extension\"" }, { "commit": "ca3380a5e774d5ccfd45299a926cb5406be2fd20", "tree": "51f45a834b523339d21bd35338228a028ef9a1b3", "parents": [ "68f764d27ddfe2f108a82cdaa016e3014117a970", "4e57757d1380d00dddc45ca187348b5e6565ab28" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Nov 09 17:37:01 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 09 17:37:01 2022 +0100" }, "message": "Merge \"test(SMCCC): add test for SMCCC_ARCH_WORKAROUND_3\"" }, { "commit": "002e569021f2e219456d02dfe239218eba5c7cfa", "tree": "4c2ea2d7cce38d168ce5e03849498161d537f1c2", "parents": [ "0fcfd47a5936180b754819ee928e8d5af173c5d2" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Mon Oct 10 12:36:46 2022 +0100" }, "committer": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Tue Nov 08 16:34:01 2022 +0000" }, "message": "feat: tftf realm extension\n\nThis patch adds Realm payload management capabilities to TFTF\nto act as a NS Host, it includes creation and destruction of a Realm,\nmapping of protected data and creation of all needed RTT levels,\nsharing of NS memory buffer from Host to Realm by mapping of\nunprotected IPA, create REC and auxiliary granules, exit Realm\nusing RSI_HOST_CALL ABI.\n\nOlder realm_payload name is used now for only R-EL1 test cases,\nRMI and SPM test cases have been moved to new file tests-rmi-spm.\n\nNew TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk,\nas an offset from where R-EL1 payload memory resources start.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7\n" }, { "commit": "afcf4668ac738f45ffe3f238d1b2d90020de759c", "tree": "94c9309be7829e0cf91ddbf1b3a7d7319ba8495c", "parents": [ "15033e6778464862333c49c47ea960daa6dbfc93" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Oct 21 20:49:53 2022 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Nov 08 15:21:36 2022 +0000" }, "message": "refact(trng): cleanup TRNG service tests\n\nThis patch adds the following changes:\n1. Updates tftf-docs on the TRNG test support\n2. Improvise few other files and macro names\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I69bbcb24e8485d2cd1384970e7424541d11838af\n" }, { "commit": "4e57757d1380d00dddc45ca187348b5e6565ab28", "tree": "418d0d08c73395150ae0fdd7fb1be53295788993", "parents": [ "4a915e0c57010bc120d751ef7877ccc6dca41087" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri May 13 15:30:46 2022 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Nov 04 21:35:02 2022 -0500" }, "message": "test(SMCCC): add test for SMCCC_ARCH_WORKAROUND_3\n\nThis adds SMCCC tests for SMCCC_ARCH_WORKAROUND_3 applicable for\nCortex-A57/72/73/75 introduced as part of CVE-2022-23960 mitigation.\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: If56bb0a69deda9032e050bdd2de98c8c4a5becbb\n" }, { "commit": "c59184cc1913bd3199a66cd8812813bc0a2f5dfb", "tree": "156871629b97b30a20ede873e0bcdaa18f220c23", "parents": [ "4a915e0c57010bc120d751ef7877ccc6dca41087" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Aug 23 19:09:41 2022 -0400" }, "committer": { "name": "kathleen.capella", "email": "kathleen.capella@arm.com", "time": "Wed Oct 19 18:23:18 2022 +0200" }, "message": "test(sve): test SVE operations in NWd\n\nTest that SVE operations done in Normal world are unaffected\nby overlapping use of SIMD registers in Secure world.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I2da5e6737e237974ddae87d9f766e7628478d899\n" }, { "commit": "0b0ca11f7cfc0f9f9f6dfb42f9b6ec201f746550", "tree": "cb25a52c6eedbaf66d5a3b64e97cbb0b4b977512", "parents": [ "4b293417d91d67e85e6f1077375f772241d5c131" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Sep 19 13:39:48 2022 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Oct 04 15:01:22 2022 -0500" }, "message": "test(interrupts): command to resume after managed exit\n\nThis patch introduces a new command sent through direct request\nmessage to be used by an endpoint to allocate cpu cycles to resume a\nCactus SP after managed exit.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Iee3cca5c8db0a46048c14ed1c41d5af90a843c82\n" }, { "commit": "4b293417d91d67e85e6f1077375f772241d5c131", "tree": "cdfdb05d79d7d0cff309ff3790b745683329cf96", "parents": [ "889037307cd441431e448c752ad4fe0cebe8939b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Sep 12 11:39:20 2022 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Oct 04 15:01:22 2022 -0500" }, "message": "test(interrupts): hint fwd destination SP could be interrupted\n\nTFTF can send a hint to the destination SP to expect that the\nforwarded sleep command could be preempted by a non-secure interrupt.\n\nThis can make the tests exercising SP\u0027s response to non-secure\ninterrupt robust by allowing the destination SP to check if the\nforward destination SP has indeed been preempted.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I808ee6c63687438d0092a53389f11bf9b3dd532d\n" }, { "commit": "889037307cd441431e448c752ad4fe0cebe8939b", "tree": "fc532db7e1e3ddae86c94b949d25022773e67bf6", "parents": [ "c19d208327f2ca05d261f8d2c4a40889eb2ffd33" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Sep 01 16:48:01 2022 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Oct 04 15:01:19 2022 -0500" }, "message": "fix(interrupts): dont enable virtual maintenance interrupts\n\nSPMC enables the following virtual maintenance interrupts by default\nfor each Secure Partition:\n \u003e MANAGED_EXIT_INTERRUPT_ID\n \u003e NOTIFICATION_PENDING_INTERRUPT_INTID\n\nHence, no need to send a request to SPs to enable them.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I7fc605b9b78ad759728909cd28ad2d2083c5de54\n" }, { "commit": "4d76de0f4bf444d4ba7cc7a117b2a83bf134fb2b", "tree": "9717bcf4b4e1c532980f0f207b3003c3d905a34c", "parents": [ "9af4d275ed83d1ff81b29b85267babca70484972" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jun 22 17:38:21 2022 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Sep 30 14:21:58 2022 -0500" }, "message": "test(interrupts): exercise ns interrupt being signaled to SP\n\nThis patch adds a tftf based test to exercise non-secure interrupt\nhandling being signaled to the Cactus SP by the SPMC while processing\na direct message.\n\nA detailed description is provided in the comment leading the test\nfunction.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I2f8511135470d2ca8f567532a1cb7c4ae374af3f\n" }, { "commit": "ebd1b69ee3b9551948dfd688b2b92ce8c7c8e016", "tree": "09859ba3291273fa929c7a8b53edc8e9962e08a2", "parents": [ "48bdf4c5f570e4dc7383d725bea26a731b50d725" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Thu Jun 30 17:47:35 2022 -0400" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Tue Sep 27 12:33:18 2022 -0400" }, "message": "test(pauth): updated helpers to include QARMA3\n\nQARMA3 is a pointer authentication algorithm introduced by v8.3\nextensions. Previous tests did not consider the possible presence\nof QARMA3 algorithm, as it was released in v8.8. This algorithm\ncan be detected through fields ID_AA64ISAR2_EL1.{GPA3, APA3} when\nthey are not 0.\n\nThis patch modifies the helper function that detects the presence\nof PAuth, considering the possibility of having QARMA3 available.\nIn addition, is_armv8_3_pauth_gpa_gpi_present() and\nis_armv8_3_pauth_apa_api_present() were modified to take into\naccount fields GPA3 and APA3 (from ID_AA64ISAR2_EL1) respectively.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I486c6d3118a040b3352eff2b0d5709baf0518314\n" }, { "commit": "48bdf4c5f570e4dc7383d725bea26a731b50d725", "tree": "ef837fd016949c482756868126f3e12b620a890f", "parents": [ "fe6d8d0d22143d9175c53568ce26dc7cc92402d6", "1920238168db83d7ff4d20570a49caf5575cf45b" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Aug 25 12:04:45 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 25 12:04:45 2022 +0200" }, "message": "Merge \"fix: mismatched sme header guard name\"" }, { "commit": "1920238168db83d7ff4d20570a49caf5575cf45b", "tree": "50a3413317d6aaf67ee89aaf60636af71cecf9e0", "parents": [ "f34b9477fdc940bf9c263a2a3c21a87536afb1c6" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Aug 17 14:18:51 2022 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Aug 24 17:28:05 2022 +0200" }, "message": "fix: mismatched sme header guard name\n\nFix SME extension header pre-processor macro name for the header\ninclusion guard.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I1ab95d67f77212342416c24f9fb97d42dd0e8c63\n" }, { "commit": "56b270fe353b7955834c4737b32a974e67471005", "tree": "1afc08b2a090b4711b0f958192d81277ff737676", "parents": [ "f34b9477fdc940bf9c263a2a3c21a87536afb1c6" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 23 17:18:55 2022 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Aug 24 16:23:05 2022 +0200" }, "message": "refactor: rename FFA_MSG_RUN to FFA_RUN\n\nThe correct ABI function name is FFA_RUN per FF-A v1.1 EAC0\nspecification. Update it in the relevant FF-A helpers.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I82858c6a6080b946f4882f8d85a30795d8e60e58\n" }, { "commit": "f34b9477fdc940bf9c263a2a3c21a87536afb1c6", "tree": "75bcafb9019d5a7490acdab80ff00fead1ae8372", "parents": [ "29039db03dc0db29bd53e6380b9e2f06cde238c2", "9303f4d1c196a1a193e6c49d19edaff41bb71bfd" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Aug 18 19:29:35 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 18 19:29:35 2022 +0200" }, "message": "Merge \"feat(rng_trap): add tests for FEAT_RNG_TRAP\"" }, { "commit": "9303f4d1c196a1a193e6c49d19edaff41bb71bfd", "tree": "52dc8e057caa71e975e75150cba14107fb480570", "parents": [ "f70e2912afc18f4f8e6697e36c2d9e9b7341ac5b" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Jul 25 16:38:01 2022 -0400" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Tue Aug 16 14:47:58 2022 -0400" }, "message": "feat(rng_trap): add tests for FEAT_RNG_TRAP\n\nAdded 2 tests that expect a trap to be triggered when a read is\nperformed on:\n1. RNDR register\n2. RNDRRS register\nThe result will be a panic signal and the whole system will halt,\nas there is no handler set for such trap.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ia979e60a106b394cc09dfdf94115354fb72142d1\n" }, { "commit": "569be40971323c2de87f798bc7da3bee142c2009", "tree": "a9c35323d71a9164e8a4f1972116713d5581a267", "parents": [ "f70e2912afc18f4f8e6697e36c2d9e9b7341ac5b" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Jul 08 10:24:39 2022 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Aug 04 14:13:26 2022 +0200" }, "message": "fix(sve): discover the SVE vector length\n\nCurrently the (SPM) test that the SVE vectors are preserved\nassumes that the SVE vector length is whatever the hard\ncoded maximum vector length we have at build time is,\ncurrently 512 bits. The tests fill a buffer that can\nhold the full set of maximally sized vectors, load it\ninto the registers, do a call and then read the values\nback into a separate buffer and compare with the original\nbuffer. If the VL is less than the maximum then this\ncomparison will fail since only the subset of the read\nbuffer used by the actual vector length will be filled.\n\nFix this by reading the SVE vector length at runtime and\nusing that when verifying the read data rather than the\nhard coded maximum value.\n\nIncrease the SVE test buffers to the maximum permitted by\nthe architecture. Configure ZCR_EL2.LEN to the maximum\npermitted value (to the limit of the implementation and\nEL3 constraint).\n\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I1d96327d3423f2f8a3d7289ae02ab06a4bf9fde3\n" }, { "commit": "0b452235757293d5cd263619ee44e288cb53ca98", "tree": "216325d3520904f51620a44c7a387754d4ab6eaa", "parents": [ "a05984ed72fbff51ffe46fde2b2f3bba9fb3681d" ], "author": { "name": "Maksims Svecovs", "email": "maksims.svecovs@arm.com", "time": "Tue May 24 11:30:34 2022 +0100" }, "committer": { "name": "Maksims Svecovs", "email": "maksims.svecovs@arm.com", "time": "Wed Jul 20 13:05:33 2022 +0100" }, "message": "feat(ff-a): add FFA_CONSOLE_LOG ABI test.\n\nAdd Cactus FF-A test to exercise FFA_CONSOLE_LOG ABI.\n\nSigned-off-by: Maksims Svecovs \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: Icad3b546c8eddd80c7a9cc3843d39679e91c6c2a\n" }, { "commit": "9ea16641579ee5b9b0e62ce56c52e7cc6b4ab4f3", "tree": "270c329d0258608e81b403ec34f76afe080df2ad", "parents": [ "e9a1d61bd0ea73bc9cf7cfe5f1a7ea8f92ff54af" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Tue Mar 01 19:39:59 2022 +0000" }, "committer": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Thu Jul 07 16:25:12 2022 +0100" }, "message": "feat(tftf): refactoring of some tftf function helpers\n\nThis refactoring is introduced in order to reuse some useful\nfunction helpers which already exist in the code base,\nby moving one function to test_helpers.c\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: If5c24da9062d100419220fe000409b73596e773c\n" }, { "commit": "4a2888a2f46e812f715d07eee82458635a751475", "tree": "3c15e70075a35642d188678150dccf4fe9002c06", "parents": [ "07d751ee6b699387da1ec7093c2a18c7244247de" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue May 31 16:07:36 2022 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Thu Jun 23 13:37:43 2022 +0100" }, "message": "test(ff-a): uuid field for ffa_partition_info_get\n\nThe EAC0 v1.1 FF-A spec now requires that the UUID field in the\npartition information descriptors is only populated when\nFFA_PARTITION_INFO_GET is supplied with a null uuid (Table 13.37).\nThis patch updates the tests to check for this.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: I241c6bed4fc5f63ec91a7b86725be5b2ee838601\n" } ], "next": "07d751ee6b699387da1ec7093c2a18c7244247de" }