)]}' { "log": [ { "commit": "31b91f4c51656adf5fe9e8319272d95fa1a2ecdf", "tree": "dca102360884f383515beb942623029e1960bc4f", "parents": [ "e39d55ab48b30c610859c277551b97c65cbe82bf" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Mar 20 12:57:10 2024 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Mar 20 12:57:10 2024 +0000" }, "message": "refactor: trim down extensive test list\n\nExtensive tests are meant to do stress testing but currently the list\nincludes most of the tests from standard test and two extensive ones\nrelated with PSCI and timer.\nSince we do standard tests in quite a few configurations, no need to\ntest them again in extensive.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I0be868e1e781fd95e95908b82bd138dc7c6d32aa\n" }, { "commit": "e39d55ab48b30c610859c277551b97c65cbe82bf", "tree": "e57adfb2e031af25a9f67d68ed6f06e35065890e", "parents": [ "296fab081902f787e2cac464fe4d019b490c495b", "b5154bcc110747a4bfdb605b7a346377a55643a2" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Sat Mar 02 12:30:04 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Mar 02 12:30:04 2024 +0100" }, "message": "Merge changes from topic \"sgi_to_nrd\"\n\n* changes:\n fix(arm): fix comments referencing \"SGI platform\"\n refactor(sgi): replace references to \"SGI\"/\"sgi\" for neoverse_rd\n refactor(sgi): rename \"CSS_SGI\" macro prefixes to \"NRD\"\n refactor(sgi): move apis and types to \"nrd\" prefix\n refactor(sgi): replace build-option prefix to \"NRD\"\n refactor(sgi): regroup \"sgi\" and \"rdinfra\" to \"neoverse_rd\"\n" }, { "commit": "296fab081902f787e2cac464fe4d019b490c495b", "tree": "72bfa719bf67c096ff879a9c7fda10ffac2a224f", "parents": [ "4ccf3b9a5e6eb7c87b588158ec33d30355dcfa27", "9c73678243bd8c27cd50b8fc097559444025cf40" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Thu Feb 29 11:28:29 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 29 11:28:29 2024 +0100" }, "message": "Merge \"refactor(xilinx): mark ttc clock select platform specific\"" }, { "commit": "4ccf3b9a5e6eb7c87b588158ec33d30355dcfa27", "tree": "5ad502bb1c75c908b7d7e3f4f897e93539beadd5", "parents": [ "f6328f67e4e87639b48e00d842192122360e1c89", "8ba06f324d4a1047aed7bc584e4c2ae635e197cc" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Thu Feb 29 11:27:28 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 29 11:27:28 2024 +0100" }, "message": "Merge \"fix(xilinx): wire Xilinx platforms in docs\"" }, { "commit": "f6328f67e4e87639b48e00d842192122360e1c89", "tree": "fa8e1d90237ac255382b19b74da650f55b9c6faa", "parents": [ "8c2ca7ec7e312f48486c75c42ffad9dc1401d563", "d72ab0984a2318cfa5b74a2dff5b708734d4d402" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Feb 28 14:51:13 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 28 14:51:13 2024 +0100" }, "message": "Merge \"feat: introduce UNDEF injection test\"" }, { "commit": "8c2ca7ec7e312f48486c75c42ffad9dc1401d563", "tree": "452393e32b8e1ee9bbc99bd104d4386c82e7ed6b", "parents": [ "90d61cd1e36634597a71b86fcb9701b94741a553", "4aaccc671a4750c72e30e282eff0c4c863eb57a9" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Feb 22 16:30:56 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 22 16:30:56 2024 +0100" }, "message": "Merge \"feat(rmi): force max IPA size on Realms to 48 bits\"" }, { "commit": "d72ab0984a2318cfa5b74a2dff5b708734d4d402", "tree": "7eb71791a47bcbea2491ddacfb27f65fe5406f4b", "parents": [ "90d61cd1e36634597a71b86fcb9701b94741a553" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Dec 11 17:43:53 2023 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Feb 22 14:21:33 2024 +0000" }, "message": "feat: introduce UNDEF injection test\n\nTest to verify UNDEF injection support in TF-A by trapping FGT register\naccess from tftf into EL3.\n\nTo trap FGT register access to EL3, run the test on model with FEAT_FGT\npresent but the traps from EL3 are not enabled (ENABLE_FEAT_FGT \u003d 0).\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Ic58ef797c64aad6d17ea33d9fc34e14b4e1a7055\n" }, { "commit": "4aaccc671a4750c72e30e282eff0c4c863eb57a9", "tree": "452393e32b8e1ee9bbc99bd104d4386c82e7ed6b", "parents": [ "90d61cd1e36634597a71b86fcb9701b94741a553" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Feb 22 12:26:57 2024 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Feb 22 12:51:48 2024 +0000" }, "message": "feat(rmi): force max IPA size on Realms to 48 bits\n\nCurrently, RMM might be able to support FEAT_LPA2 and 52 bits address\nsize, however as TFTF tests does not support FEAT_LPA2 yet, we need to\nlimit the maximum IPA space size for realm creation on RMI tests, as\nTFTF uses the maximum size supported reported by RMM as the IPA\nsize when creating new realms, which can cause an inconsistency if\nFEAT_LPA2 is disabled.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I3b77cbbb41a8a1353c7a35decc35d080fd3ad9f3\n" }, { "commit": "b5154bcc110747a4bfdb605b7a346377a55643a2", "tree": "f1527b16cec5b8eb497a6531c3c100e8d21428fe", "parents": [ "381d3912cedb1c257d9829933d723b117949e1e7" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Thu Feb 15 11:32:56 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:58:44 2024 +0000" }, "message": "fix(arm): fix comments referencing \"SGI platform\"\n\nCurrently, both N1SDP and TC platforms have references to \"SGI\" within\na comment in their respective source files. Fix this by replacing it\nwith the appropriate platform name.\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I523c3ef0bfa76d35819a8f776a08820ffd197c44\n" }, { "commit": "381d3912cedb1c257d9829933d723b117949e1e7", "tree": "e002d32e202aeb6ded5d9795a2914e4de6db5259", "parents": [ "5b113e102a86fbf61137c9f700c696609cfd503b" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Thu Feb 15 11:28:31 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:58:07 2024 +0000" }, "message": "refactor(sgi): replace references to \"SGI\"/\"sgi\" for neoverse_rd\n\nCurrently, there are several reference to \"SGI\" or \"sgi\" in comments or\nas macro prefix within the neoverse_rd directory. As part of the\nmigration to neoverse_rd, rename all occurences of \"SGI/sgi\" to\n\"Neoverse-RD\" or the \"NRD\" prefix accordingly. All references in\ncomments are rephrased as \"Neoverse RD platforms\". References in code\nare renamed as \"NRD\"/\"nrd\" accordingly.\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I55bdab01051974b3ddb2dae3bc4c0e253fb85fc3\n" }, { "commit": "5b113e102a86fbf61137c9f700c696609cfd503b", "tree": "9d35921dfa15afd1826bbe55cd02b5db6d77745a", "parents": [ "3f3f3e9e4ce8de3d6737d4ae9e2dd77fea11fb9c" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Wed Feb 14 12:49:55 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:57:40 2024 +0000" }, "message": "refactor(sgi): rename \"CSS_SGI\" macro prefixes to \"NRD\"\n\nAs of now, several internal macros utilize \"CSS_SGI\" as their prefix.\nGiven the change to neoverse_rd, the prefix \"CSS_SGI\" is no longer\nappropriate. Therefore, update the macro prefixes to \"NRD\" for\nconsistency and clarity.\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I252a5ece6c82a0a5a3b451238ed0da07f8a0c81e\n" }, { "commit": "3f3f3e9e4ce8de3d6737d4ae9e2dd77fea11fb9c", "tree": "e7913a36e9f110b29da39c1a557791ee2620b0a5", "parents": [ "8836f620855c8a7ed650b262e7704c54be5d2c0a" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Wed Feb 14 12:47:42 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:57:13 2024 +0000" }, "message": "refactor(sgi): move apis and types to \"nrd\" prefix\n\nCurrently, functions and types internal to neoverse_rd platforms are\nnamed with \"sgi\" as the prefix. Since common code and platforms are no\nlonger under the \"sgi\" umbrella, move the prefix to \"nrd\". This change\nwould amend the prefixes for functions, types and objects.\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I1080259b661081c535ab46f61df9e4563420bdb0\n" }, { "commit": "8836f620855c8a7ed650b262e7704c54be5d2c0a", "tree": "5dbb309edfeefc98c057bbe5a055b66edcb2e450", "parents": [ "cac32e9262ee8e0e23d2e3b6551227767297717f" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Wed Feb 14 12:43:21 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Mon Feb 19 09:56:24 2024 +0000" }, "message": "refactor(sgi): replace build-option prefix to \"NRD\"\n\nAs of now, CSS_SGI_PLATFORM_VARIANT and CSS_SGI_CHIP_COUNT are the\nexternal build option that sgi platforms support. As \"sgi\" has been\nrenamed to \"neoverse_rd\", replace the prefix \"CSS_SGI\" with \"NRD\".\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I585575788c14d1c3b26ab336672ef149771dab98\n" }, { "commit": "cac32e9262ee8e0e23d2e3b6551227767297717f", "tree": "495fd75302643a9a4097fe2c75b30b8de3a7fbe9", "parents": [ "90d61cd1e36634597a71b86fcb9701b94741a553" ], "author": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Tue Feb 13 22:02:45 2024 +0000" }, "committer": { "name": "Rohit Mathew", "email": "Rohit.Mathew@arm.com", "time": "Sun Feb 18 15:33:02 2024 +0000" }, "message": "refactor(sgi): regroup \"sgi\" and \"rdinfra\" to \"neoverse_rd\"\n\nCurrently, reference design platforms such as RD-N2, RD-N1-Edge, RD-V1,\nand SGI-575 utilize \"sgi/common\" as the common source directory. The\n\"sgi\" prefix originated from the System Guidance Infrastructure (SGI)\nand was initially associated with the SGI-575 platform. However,\nsubsequent platforms released were under the Neoverse reference design\nproduct name.\n\nTo align with the Neoverse reference design nomenclature, regroup all\ncommon and board files within neoverse_rd directory. Consolidate common\nsources and headers under neoverse_rd/common. Board files for RD-V1,\nRD-N2, RD-N1-Edge and SGI-575 are moved to neoverse_rd/platform. With\nthe changes in this commit, the tree view would look as follows:\n\n├── neoverse_rd\n│   ├── common\n│   │   ├── arch\n│   │   └── include\n│   └── platform\n│   ├── rdn1edge\n│   ├── rdn2\n│   ├── rdv1\n│   └── sgi575\n\nAdditionally, update all file prefixes from \"sgi\" to \"nrd.\"\n\nSigned-off-by: Rohit Mathew \u003cRohit.Mathew@arm.com\u003e\nChange-Id: I07e2af143fad82e48172612fe0e28db6464fa901\n" }, { "commit": "9c73678243bd8c27cd50b8fc097559444025cf40", "tree": "5f0f6c2eceeabb6c430740b6aa9cd4e3ae38e469", "parents": [ "90d61cd1e36634597a71b86fcb9701b94741a553" ], "author": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Fri Feb 16 12:29:16 2024 +0530" }, "committer": { "name": "Amit Nagal", "email": "amit.nagal@amd.com", "time": "Fri Feb 16 15:03:53 2024 +0530" }, "message": "refactor(xilinx): mark ttc clock select platform specific\n\nTTC clock select register(TTC_CLK_SEL) is used to select\nTTC reference clock.\nThe offset for TTC_CLK_SEL in LPD_IOU_SLCR register module\ndiffers on various AMD xilinx platforms.\nOffset is 0x380 for zynqmp platform and is 0x360 for versal\nand versal-net platforms.\nAccording define offset for TTC clock select in platform\nspecific files.\n\nChange-Id: I479f655704fcc515068425eedc5d73d24a32dde0\nSigned-off-by: Amit Nagal \u003camit.nagal@amd.com\u003e\n" }, { "commit": "90d61cd1e36634597a71b86fcb9701b94741a553", "tree": "2b617dacfc9f35422f55b82cd0280148f4494c51", "parents": [ "8cea7c5af9c2a300c4f5d143480d04c84cd5b21b", "2a5abadb8e841eedeaa1ff78b6f0da5f957b2ab8" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Feb 15 17:11:34 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 15 17:11:34 2024 +0100" }, "message": "Merge changes I26cbaaf6,Ibb393b41\n\n* changes:\n test(realm): add test for FEAT_DIT\n test(realm): test realm pauth state is preserved\n" }, { "commit": "8cea7c5af9c2a300c4f5d143480d04c84cd5b21b", "tree": "57c461b3762b34758df91774cbbcec09e0eb4e27", "parents": [ "a8deec5c0b51719b1f268e4f106c3a095a387074", "4f35ce6fcbb68fc1f2fb48df7f66ad0fd494a061" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Feb 15 16:57:40 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 15 16:57:40 2024 +0100" }, "message": "Merge \"tc: update UART base for TFTF\"" }, { "commit": "2a5abadb8e841eedeaa1ff78b6f0da5f957b2ab8", "tree": "42755e1512d2cf0d6abf3f0baa01a289d2a69e46", "parents": [ "21a30ed1ae35a8b32d23e96cdc143702a27bda90" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Jan 17 13:48:44 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Feb 14 12:51:31 2024 +0100" }, "message": "test(realm): add test for FEAT_DIT\n\nAdd testcase to enable FEAT_DIT in realm.\nTest if DIT Bit is preserved across context switch RL/NS.\n\nChange-Id: I26cbaaf669b53ecba14a451955b6f847c45e0575\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "21a30ed1ae35a8b32d23e96cdc143702a27bda90", "tree": "bd1d61a86ff59e96c33a98a036e542f43ce185df", "parents": [ "a8deec5c0b51719b1f268e4f106c3a095a387074" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Sat Jan 13 23:07:43 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Feb 14 12:51:31 2024 +0100" }, "message": "test(realm): test realm pauth state is preserved\n\nModify Pauth lib to work for multiple CPU\nTest if Realm pauth state is preserved for all RECs\non context switch to RMM/NS.\n\nChange-Id: Ibb393b415bab27066289b560be49e02d0c8f58ba\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "4f35ce6fcbb68fc1f2fb48df7f66ad0fd494a061", "tree": "18660e8c58860af4ed31186704b908c918c7201e", "parents": [ "1abd0d2332d79ef7e2889d648cd093bb90e10bf3" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jan 17 13:05:48 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Feb 13 15:14:34 2024 +0100" }, "message": "tc: update UART base for TFTF\n\nUpdated UART base for TFTF as per the TC memory map.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I98cf5318edcd793cf69ead5e940718e42f25e3c9\n" }, { "commit": "a8deec5c0b51719b1f268e4f106c3a095a387074", "tree": "ba834cd8cd46a432215cc09f6fb8886fc196e8c4", "parents": [ "a3ec1f1762236914d129dd8155d19b149b2c6570", "5d4936a7baed58a73cdf2a2a117e5d0501527237" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Feb 13 09:34:17 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 13 09:34:17 2024 +0100" }, "message": "Merge \"fix: map ns buffer only if needed for SMMU tests\"" }, { "commit": "5d4936a7baed58a73cdf2a2a117e5d0501527237", "tree": "ba834cd8cd46a432215cc09f6fb8886fc196e8c4", "parents": [ "a3ec1f1762236914d129dd8155d19b149b2c6570" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Feb 12 18:49:21 2024 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Feb 12 18:57:04 2024 -0600" }, "message": "fix: map ns buffer only if needed for SMMU tests\n\nSince SMMU based tests are only supported for FVP platform at the\nmoment, the non-secure memory region used as work buffer for\nSMMU test need not be mapped in the page tables for other platforms.\n\nThis patch helps to fix a hang noticed for TC based spm test.\n\nChange-Id: I137eeea684250f9620b4e6d585018ad3d62178b4\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "a3ec1f1762236914d129dd8155d19b149b2c6570", "tree": "932c808a0ca57770ecff5fd831ba2eddb0b25f9d", "parents": [ "8e3f5662031f785930f997d713fc1730b101e5bb", "a08c7195558726a2c3abd3bf9167ff4deae7d9e1" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Feb 12 17:31:14 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 12 17:31:14 2024 +0100" }, "message": "Merge changes from topic \"mp/dma_isolation\"\n\n* changes:\n test: exercise DMA isolation for secure access to ns memory\n fix: specify properties to corresponding memory region nodes\n" }, { "commit": "8e3f5662031f785930f997d713fc1730b101e5bb", "tree": "ee4e3153b8563f3a46e0e845fdce0492307645d0", "parents": [ "51e153663b5b31c3d4f7dcdef266a431111d4bad", "7b51dbe9d4739f622f332fd232a3068b99c2bb50" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Feb 08 17:08:05 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 08 17:08:05 2024 +0100" }, "message": "Merge \"refactor(smc_fuzz): performance enhancement\"" }, { "commit": "51e153663b5b31c3d4f7dcdef266a431111d4bad", "tree": "3a05dab054068d29e8b242f8f82daa4a864468e9", "parents": [ "fd35f0a4d6125bb1fa69a671a6d2d42628229609", "b027f5706308502152b5aade0ad509ba27370c42" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Feb 08 16:23:30 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 08 16:23:30 2024 +0100" }, "message": "Merge \"test(realm): add testcase for Synchronous external aborts\"" }, { "commit": "b027f5706308502152b5aade0ad509ba27370c42", "tree": "3a05dab054068d29e8b242f8f82daa4a864468e9", "parents": [ "fd35f0a4d6125bb1fa69a671a6d2d42628229609" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Jan 02 22:00:29 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Feb 08 12:14:31 2024 +0100" }, "message": "test(realm): add testcase for Synchronous external aborts\n\nAdd testcase to cause instruction or data abort in Realm by\naccessing addr with\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dEMPTY\n* HIPAS\u003dASSIGNED and RIPAS\u003dEMPTY\n* Unprotected IPA\n* Host injected SEA after Data abort\n\nChange-Id: I6be546c042b4983670fb7c27fca74649c68787be\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "a08c7195558726a2c3abd3bf9167ff4deae7d9e1", "tree": "3701dcb74085676d356e05b92f201e2e6800860b", "parents": [ "9fd0a9a2342668fa12cf2b15bc83be907899b8a4" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Oct 18 17:49:32 2023 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Feb 07 17:03:56 2024 -0600" }, "message": "test: exercise DMA isolation for secure access to ns memory\n\nThis test helps to validate a scenario where a secure stream\nbelonging to Cactus SP accesses non-secure IPA space.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I8085f2974d53b9cec9b3ae4a17fd328607b76e2b\n" }, { "commit": "9fd0a9a2342668fa12cf2b15bc83be907899b8a4", "tree": "83b8c02ba5029512d08168440629cf6ac7adceb0", "parents": [ "fd35f0a4d6125bb1fa69a671a6d2d42628229609" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Sep 11 15:46:50 2023 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Feb 07 17:03:56 2024 -0600" }, "message": "fix: specify properties to corresponding memory region nodes\n\nThe following properties must be specified in the memory region\nnodes for the corresponding address space to be visible to the\nupstream DMA device:\n1) stream-ids: identity of the streams generated by the device.\n2) smmu-id: identity of the SMMU IP that the device is upstream of.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Iaa894a0b0ac9b564bd2c822af6630f3207bf8e8c\n" }, { "commit": "fd35f0a4d6125bb1fa69a671a6d2d42628229609", "tree": "bf1c92d316299405b3751e62e904616f2f81e0a3", "parents": [ "69c9f363cb172788ef7e8d3fd711f56ddf481bf8", "e742ba89effefc4298fb4e406e0515a83db9c7e0" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Feb 07 17:22:13 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 07 17:22:13 2024 +0100" }, "message": "Merge changes from topic \"ja/spm_rme\"\n\n* changes:\n refactor: cactus to handle expect exception\n test(memory share): memory contents checks\n refactor(spm): clean-up after failed memory share\n test(spm): lend/donate realm memory\n test(spm): use all constituents of memory share\n test(spm): validate GPC with memory sharing\n test(memory share): leverage rme for lend/donate\n" }, { "commit": "69c9f363cb172788ef7e8d3fd711f56ddf481bf8", "tree": "e6c01f0aef5f40fb28fce239d095d9236e7fa762", "parents": [ "4984ea7561a8bc3daefb2971594e3ff59fa3177a", "8ea96f636ebc984f6f69144a6b6ca1f84aa03900" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Feb 07 14:14:51 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 07 14:14:51 2024 +0100" }, "message": "Merge changes from topic \"xlnx_versal_net_fix\"\n\n* changes:\n feat(versal-net): remove TSP tests from skip list\n fix(versal-net): correct core position function\n" }, { "commit": "4984ea7561a8bc3daefb2971594e3ff59fa3177a", "tree": "1c2b20b14f9bf6a1b43bbee538bcaf852e3d3e8b", "parents": [ "8469257f30b94e749c339d193a2f680ef701b380", "e68494eb130e2c8021ca4af626a9cb1df8d67dbd" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 07 11:16:36 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 07 11:16:36 2024 +0100" }, "message": "Merge changes Ic04c0dda,I350957ac,Idb838bd8\n\n* changes:\n test(realm): add testcase for REC exit due to Data/Instr abort\n fix(realm): fix realm destroy api\n test(realm): remove unwanted host_rmi_rtt_init_ripas\n" }, { "commit": "e742ba89effefc4298fb4e406e0515a83db9c7e0", "tree": "c3d9688ea07be06ac244e757faebdb1c76bb329b", "parents": [ "c2e32ed038aa54ae9c5d35362dc3c2fffc55fdb3" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 11 10:38:29 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Feb 06 19:27:38 2024 +0000" }, "message": "refactor: cactus to handle expect exception\n\nIn the test \u0027rl_memory_cannot_be_accessed_in_s\u0027, tftf\nshares memory to the SP that it changed to realm PAS.\n\nThe access from the SP should result in an exception.\nCactus receives an indication it should expect an\nexception on memory access via the arguments of the\n\u0027cactus_mem_send_cmd\u0027 request. This is used to avoid\nthe reads to check memory, which could return in an error\nresponse, which would make the test falsely fail.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ie220d4bab04c052a73e8b04c8667c9973b95a9e0\n" }, { "commit": "c2e32ed038aa54ae9c5d35362dc3c2fffc55fdb3", "tree": "449fb0a27b10806227d86762b9d27f53a8e35402", "parents": [ "b122eea5195b23c3e27fc8a28bc7dccf3623894a" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Dec 04 13:22:44 2023 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Feb 06 19:27:38 2024 +0000" }, "message": "test(memory share): memory contents checks\n\nIn RME enabled systems, the memory is expected to be\nscrubbed on PAS updates from S to NS. As well, it is likely\nthat the memory addresses are shadowed, and the contents are not\nvisible accross updates from the different address spaces.\nAs such, the SP shall not rely on memory content to be\nin any form. FFA_MEM_LEND/FFA_MEM_DONATE are thus considered\nfor memory allocation purposes.\n\nThis patch changes the memory sharing tests, to cater\nfor the correct assumptions.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I78ed47df789dda1d695e2e52b0df8c28b12658da\n" }, { "commit": "b122eea5195b23c3e27fc8a28bc7dccf3623894a", "tree": "e891429587f817ef4eae9329f5063466824bd886", "parents": [ "3be0efa1d92003476d89f448502927660d747b1a" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 11 16:59:46 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Feb 06 19:27:38 2024 +0000" }, "message": "refactor(spm): clean-up after failed memory share\n\nClean-up after failed memory share test, to allow for subsequent\ntests to still provide meaningful test results.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ic763fb64c0948c19e6b7d7f99119b20cc05fc83b\n" }, { "commit": "3be0efa1d92003476d89f448502927660d747b1a", "tree": "1822e848bd7dd29c2213d9955249686df23c8969", "parents": [ "72f002936b6978078674dd1ed69c622220c90196" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Oct 02 19:11:11 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Feb 06 19:27:38 2024 +0000" }, "message": "test(spm): lend/donate realm memory\n\nValidate if memory gets delegated to a realm PAS, it can\u0027t be used\nin FF-A memory lend/donate from NS to SWd.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I16c9b7193b4ae8f56b1182e3b28d13a742bfcd4e\n" }, { "commit": "72f002936b6978078674dd1ed69c622220c90196", "tree": "8a4c1f8adead9f77e0703a8e4c421d7b309919d5", "parents": [ "8083db2a0878011f16c549c7546331f255aa4658" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jan 08 11:31:45 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Feb 06 19:27:38 2024 +0000" }, "message": "test(spm): use all constituents of memory share\n\nOn memory sharing operation use all the constituents within the\ncomposite.\n\nExtended memory lend operation test to include multiple scattered\npages to make sure the update to security state is happening\nto all memory regions.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I2179df12ca63636bdb6489eea77e809422f95430\n" }, { "commit": "8083db2a0878011f16c549c7546331f255aa4658", "tree": "e9698ebfcb4185f174e05eaf57ff3721ceaf6074", "parents": [ "d39aa5b579411c1481efaf637ef44869831f7b7b" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jun 27 17:22:58 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Feb 06 19:27:38 2024 +0000" }, "message": "test(spm): validate GPC with memory sharing\n\nValidate during the lend/donate with the SWd, when RME\nis in the platform of test, if the NWd attempts to access\nthe memory it will trigger a fault due to Granule Protection\nChecks (GPC).\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ibab25e7e56abaa28ae077d8b8c2c7cd377ccf515\n" }, { "commit": "d39aa5b579411c1481efaf637ef44869831f7b7b", "tree": "bc3ed3c9b3ae43b5accb744060ac28d3f8907c0d", "parents": [ "8469257f30b94e749c339d193a2f680ef701b380" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 24 10:21:46 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Feb 06 19:27:38 2024 +0000" }, "message": "test(memory share): leverage rme for lend/donate\n\nAdd the memory sharing test suite to invalid-access, and rename\nit to memory-access.\nIn such configuration the TF-A is meant to provide services\naccessible via SMC, to update the security state of the memory\nlent/donated between NWd to SWd.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I4a6f2de612dbd9de2db757e3baf2613c47b8a09b\n" }, { "commit": "8469257f30b94e749c339d193a2f680ef701b380", "tree": "ef9fa2fa0f5db326312038d139822180486524d3", "parents": [ "bca7a3ab0f23de5b4c135eb21fa4b80209d86118", "1abd0d2332d79ef7e2889d648cd093bb90e10bf3" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Feb 06 14:59:48 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 06 14:59:48 2024 +0100" }, "message": "Merge changes from topic \"ja/cactus_ffa_console\"\n\n* changes:\n fix(spm): logs with errors in verbose builds\n refactor: first cactus SP to drop uart\n" }, { "commit": "8ea96f636ebc984f6f69144a6b6ca1f84aa03900", "tree": "a069544769f52840ff5d0a018bdde6a8da45a23b", "parents": [ "0137d4b08486ebb979ff0dfa5a41f25ef422f933" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Mon Feb 05 14:10:53 2024 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Tue Feb 06 15:58:49 2024 +0530" }, "message": "feat(versal-net): remove TSP tests from skip list\n\nAll of these tests are passing on the target, so removing\nthem from the skip list.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: Ieaba2634f0501e3815c1d6ef1503a37908bcfcc1\n" }, { "commit": "0137d4b08486ebb979ff0dfa5a41f25ef422f933", "tree": "6a189e1e18e9e025a62f93f43aaac0babfef219e", "parents": [ "bca7a3ab0f23de5b4c135eb21fa4b80209d86118" ], "author": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Thu Feb 01 09:55:56 2024 +0530" }, "committer": { "name": "Prasad Kummari", "email": "prasad.kummari@amd.com", "time": "Tue Feb 06 15:49:18 2024 +0530" }, "message": "fix(versal-net): correct core position function\n\nThe corrected calculation of core positions involves utilizing the\nlinear core and cluster IDs from an MPID register. The MPID register\ncomprises three affinity levels: Aff0 (bits 0 to 7), Aff1 (bits 8 to 15),\nand Aff2 (bits 16 to 23).\n\nIn the current implementation of platform_get_core_pos(), the function\nreads the MPIDR_AFF0_SHIFT (0 to 7 bits) for the core ID and\nMPIDR_AFF1_SHIFT (8 to 15 bits) for the cluster ID. For example, in\nthe output \"CPU #10 [MPID: 0x1020200],\" it incorrectly returns the\ncore position as 8 instead of the expected core position 10.\n\nIn the updated implementation of the platform_get_core_pos() function,\nthe core ID is determined by reading the bits corresponding to Affinity\nlevel 1 (MPIDR_AFF1_SHIFT), and the cluster ID is determined by reading\nthe bits corresponding to Affinity level 2 (MPIDR_AFF2_SHIFT).\n\nTo address this issue and obtain the correct core ID, it is necessary\nto read affinity level 1 bits. Additionally, affinity level 2 should\nbe read to determine the cluster ID. A check has been incorporated to\nverify the MT bit in MPIDR for enabled status, leading to a modification\nin cluster/core calculation. Additionally, it is necessary to define\nPLAT_MAX_PE_PER_CPU for the affinity test.\n\nSigned-off-by: Prasad Kummari \u003cprasad.kummari@amd.com\u003e\nChange-Id: I07573e82908ec6f2404423d61639646d411502cd\n" }, { "commit": "e68494eb130e2c8021ca4af626a9cb1df8d67dbd", "tree": "894c262fc0aa78dcbe3b28cc6b731df068a404b6", "parents": [ "daa6c795847b78692f522fd96f783a6d419aaec2" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Nov 06 11:04:57 2023 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 06 10:45:44 2024 +0100" }, "message": "test(realm): add testcase for REC exit due to Data/Instr abort\n\nAdd testcase to cause instruction or data abort in Realm by\naccessing addr with\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dDESTROYED\n* HIPAS\u003dASSIGNED and RIPAS\u003dDESTROYED\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dRAM\nVerify rec exit due to abort\n\nChange-Id: Ic04c0ddaf1b18ec0cfd71c28753c4ed7298302da\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "daa6c795847b78692f522fd96f783a6d419aaec2", "tree": "34ac7b861c0b9f264f21c1eeae2cdfc7cf8e52fd", "parents": [ "f33e3a6f851ef61d4271be6446278123bc6633a2" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 11 15:06:29 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 06 10:45:44 2024 +0100" }, "message": "fix(realm): fix realm destroy api\n\nAPI failed to destroy realms in new state,\nfix the assumption that no recs were created if realm is in new state\nDestroys all rec and realm properly.\n\nChange-Id: I350957acfa1ba1446a3028e6c277625ca76486b0\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "f33e3a6f851ef61d4271be6446278123bc6633a2", "tree": "206b6e67ebd432ff5383c8a8cabb14abb3536478", "parents": [ "bca7a3ab0f23de5b4c135eb21fa4b80209d86118" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Dec 22 13:52:37 2023 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 06 10:45:44 2024 +0100" }, "message": "test(realm): remove unwanted host_rmi_rtt_init_ripas\n\nRemove unwanted host_rmi_rtt_init_ripas\nfrom host_realm_map_protected_data API\n\nChange-Id: Idb838bd824ab663ded5d08ca08211e0116daa64d\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "bca7a3ab0f23de5b4c135eb21fa4b80209d86118", "tree": "93f5f0e23bdd2d023e518fcccff135b73ef01c4a", "parents": [ "7c38019d7272c296cba1f97316f296cb86e058b7", "d655d58c0c4791c10ad811a5f8bd66e0c1a8d989" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Feb 05 23:33:56 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 05 23:33:56 2024 +0100" }, "message": "Merge \"feat(cactus): add support for fake RAS handler command\"" }, { "commit": "7c38019d7272c296cba1f97316f296cb86e058b7", "tree": "0e7dd99555063ff7bf2d99a177d2e8a8587863cd", "parents": [ "0945e23153c06ed196756ac094c81ab8627d9a95", "a404b851f4fc008d3dde50bc872449e3e4489e29" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Feb 05 10:40:50 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 05 10:40:50 2024 +0100" }, "message": "Merge \"docs: update links to TF-A Tests issues tracker\"" }, { "commit": "7b51dbe9d4739f622f332fd232a3068b99c2bb50", "tree": "ec009a4479242e55a6a863d2dc6fb5b10966796b", "parents": [ "6eec0b422131e94e9c602e5560a432b36b97f703" ], "author": { "name": "mardyk01", "email": "mark.dykes@arm.com", "time": "Wed Jan 17 15:25:36 2024 -0600" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Feb 02 13:50:12 2024 -0600" }, "message": "refactor(smc_fuzz): performance enhancement\n\nAdd the ability to return integer rather than string from fuzzer\nfunction. This will improve performance especially for larger fuzz\nbased testing. This will work in tandem with the changes to the CI where\nthe script flows provide additional support for the change. Modifications\nto the device tree files have been made to prevent name clashes with\nthe function names.\n\nChange-Id: I95aaf23c95943f944d5837e2a8440514aafd6dde\nSigned-off-by: mardyk01 \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "1abd0d2332d79ef7e2889d648cd093bb90e10bf3", "tree": "720447f478c9e5ae6b5c1720419fed5c63da4b73", "parents": [ "f3ea1a8a01aa7e6181677c7d94654891903de9e4" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jan 17 11:31:57 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jan 31 19:18:57 2024 +0000" }, "message": "fix(spm): logs with errors in verbose builds\n\nFix few instances with verbose logs that contained\nbuild errors.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I08a2c23d831e5882939efce655c9c95485e2c9b9\n" }, { "commit": "f3ea1a8a01aa7e6181677c7d94654891903de9e4", "tree": "fb5d226cea3ebe002892b3c30abf7d4ba9c3213d", "parents": [ "0945e23153c06ed196756ac094c81ab8627d9a95" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jan 17 11:06:55 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jan 31 19:08:44 2024 +0000" }, "message": "refactor: first cactus SP to drop uart\n\nThe first cactus SP was using a uart device to\nserve as a validation for the device memory regions.\nCurrently, there are other uses that serve this test.\nAs such dropping the uart device from the manifest, and\nconfiguring SPs to always use FFA_CONSOLE_LOG.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I0ee35bfca7a885f5adc112964edeb627bb659fc0\n" }, { "commit": "d655d58c0c4791c10ad811a5f8bd66e0c1a8d989", "tree": "f23aa14968bf1100c987e8ebe351f96356acb1c9", "parents": [ "0945e23153c06ed196756ac094c81ab8627d9a95" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jan 16 14:45:39 2024 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jan 31 09:42:42 2024 -0600" }, "message": "feat(cactus): add support for fake RAS handler command\n\nThis command mimics handling a RAS error delegated by an EL3 logical\nsecure partition through a direct message.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I45e728880de1ee594e980667872e663309c83c22\n" }, { "commit": "0945e23153c06ed196756ac094c81ab8627d9a95", "tree": "7bc1e57bb77a4cf09cf18b75974e18e60711da53", "parents": [ "8f6b131f44bf5355d07b274f6a43490f968590b2", "16de81046dbffdfc19ca4a30524f170860eac178" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jan 31 08:48:35 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 31 08:48:35 2024 +0100" }, "message": "Merge \"test(fvp): Test trusted key certificate corruption\"" }, { "commit": "8f6b131f44bf5355d07b274f6a43490f968590b2", "tree": "b7dd4ac48efef7b9996e393b68081979c5baff87", "parents": [ "0f49af50669fa3484df3166e7db8a28c70d06329", "19626b492f1e6658e01ab11478cd779f7cf0ba88" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jan 30 12:47:29 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 30 12:47:29 2024 +0100" }, "message": "Merge changes from topic \"od/sme\"\n\n* changes:\n fix: replace platform get core pos usage\n refactor(spm): rename spm cpu_features to simd\n" }, { "commit": "16de81046dbffdfc19ca4a30524f170860eac178", "tree": "d70655f6090cd2e8befdae3a8270682f19f551ba", "parents": [ "84ad6157a4e83834fa925b80534ca5414c368586" ], "author": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Fri Aug 18 08:50:30 2023 -0500" }, "committer": { "name": "Jimmy Brisson", "email": "jimmy.brisson@arm.com", "time": "Mon Jan 29 13:10:08 2024 -0600" }, "message": "test(fvp): Test trusted key certificate corruption\n\nThis also includes a test framework for use with corrupting the\nroot of trust private key certificate in the boot FIP, found\nusing its UUID.\n\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\nChange-Id: I988c517637edcf6fdcaf271628eb650781c276f8\n" }, { "commit": "a404b851f4fc008d3dde50bc872449e3e4489e29", "tree": "cc6fd5a279414f49cdd48487aaf4a91be019f648", "parents": [ "0f49af50669fa3484df3166e7db8a28c70d06329" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 26 14:55:58 2024 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri Jan 26 15:07:55 2024 +0100" }, "message": "docs: update links to TF-A Tests issues tracker\n\ndeveloper.trustedfirmware.org is deprecated so we cannot use its issues\ntracker anymore. Instead, the project will now make use of the issues\ntracker associated with the project\u0027s Github mirror at [1].\n\nReflect this change in TF-A Tests documentation.\n\n[1] https://github.com/TrustedFirmware-A/tf-a-tests/issues\n\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\nChange-Id: I2aa1c3affe42dbc8812bbdd910820d06f4e853f3\n" }, { "commit": "19626b492f1e6658e01ab11478cd779f7cf0ba88", "tree": "b7dd4ac48efef7b9996e393b68081979c5baff87", "parents": [ "6bb3a506bf2c94a959735d03e2dd9f1e377c8451" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 21 18:29:05 2023 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Jan 26 12:01:29 2024 +0100" }, "message": "fix: replace platform get core pos usage\n\nIt is incorrect for secure partitions to use the platform_get_core_pos\nmacro. MPIDR_EL1 read from S-EL1 is the impdef virtual MPIDR value set\nby the SPMC on behalf of SP. The MPIDR value does not hold physical CPU\naffinity values, but the linear vCPU index for the currently running\nvCPU. Add an SPM helper to retrieve the vCPU index information and\nupdate call sites to use this helper.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ic9927acc5b64d25331cb61a83d9acbdc83173e2b\n" }, { "commit": "6bb3a506bf2c94a959735d03e2dd9f1e377c8451", "tree": "eb268bbc5ec9569193c661f481a91a70f117ed3c", "parents": [ "0f49af50669fa3484df3166e7db8a28c70d06329" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Oct 12 16:08:02 2023 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Jan 26 12:01:29 2024 +0100" }, "message": "refactor(spm): rename spm cpu_features to simd\n\ntest_spm_cpu_features.c is renamed test_spm_simd.c\ncactus_test_cpu_features.c is renamed cactus_test_simd.c\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Icc2d7deada0ff335436cf36c7f2d2dfbf2a0d9a3\n" }, { "commit": "0f49af50669fa3484df3166e7db8a28c70d06329", "tree": "e2f9e8154082fbca1aadedde2b579ae89f787829", "parents": [ "b78eb3e2e5728daae5a318f031a0c66e0ec77a7b", "6dd65d85e079ae31478316051ac1568214491a82" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jan 25 17:50:54 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 25 17:50:54 2024 +0100" }, "message": "Merge changes from topic \"memory_sharing\"\n\n* changes:\n test(memory share): enable hypervisor retrieve tests\n feat(memory share): verify receivers\n fix(memory share): arguments used in retrieve tests\n feat(memory share): add helper for getting receivers\n" }, { "commit": "b78eb3e2e5728daae5a318f031a0c66e0ec77a7b", "tree": "8b672170fe2274b845f0dff8372d578075a5dec1", "parents": [ "5517c09b42a412f29aa8a146fa6ec5b5bd33a2af", "dbb6634fa8a3b32c377db68d3e4de2ca99bcaf7f" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Jan 24 08:56:18 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 24 08:56:18 2024 +0100" }, "message": "Merge \"fix(xilinx): update test skip list\"" }, { "commit": "6dd65d85e079ae31478316051ac1568214491a82", "tree": "77ae85cddf2e6361df618f8fa8c370759383a674", "parents": [ "b744c9b49dc4af01e8af0a13b3c16d225cc05732" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 18 17:08:49 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jan 23 14:50:07 2024 +0000" }, "message": "test(memory share): enable hypervisor retrieve tests\n\nThe Hypervisor retrieve tests had been temporarily disabled,\nnow integration issues are expected to have been fixed.\nAs such, enable the tests.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I4a1f5a99a8b3259799280daf5d32702c16964e4d\n" }, { "commit": "b744c9b49dc4af01e8af0a13b3c16d225cc05732", "tree": "9c79638bb86409a8d440ff890f375558cc78c239", "parents": [ "f325331b86dd3f2ea31bbb20690b36538a8ead87" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 18 17:03:47 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jan 23 14:50:07 2024 +0000" }, "message": "feat(memory share): verify receivers\n\nAdded functions to validate the receivers list in the\nhypervisor retrieve request tests.\nLeverage them to validate receivers list.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I705f3ca9f0e540dce60f660ebf996f2462a51e3c\n" }, { "commit": "f325331b86dd3f2ea31bbb20690b36538a8ead87", "tree": "4237de4b195da4aab89edcacf6ed2f6667af2f82", "parents": [ "f0b3bd6c706da491eb589e0e8cbd3bc16a77113a" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 18 17:05:26 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jan 23 14:50:07 2024 +0000" }, "message": "fix(memory share): arguments used in retrieve tests\n\nFix a few small arguments that are used in the hypervisor\nretrieve request tests.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I9f6d2d10178331ffea6387a00c05002c07346bc6\n" }, { "commit": "f0b3bd6c706da491eb589e0e8cbd3bc16a77113a", "tree": "48383ded203667672828368c981e54bb049d9b1f", "parents": [ "5517c09b42a412f29aa8a146fa6ec5b5bd33a2af" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 18 17:01:37 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jan 23 14:50:07 2024 +0000" }, "message": "feat(memory share): add helper for getting receivers\n\nAdd helper for \u0027ffa_memory_region_get_receiver\u0027.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Id30a3cf58689ab8d6d23e851b6581fad53f1f6e9\n" }, { "commit": "5517c09b42a412f29aa8a146fa6ec5b5bd33a2af", "tree": "b38806323ed4a33d91d27b0f18d563c1635f8f7c", "parents": [ "6eec0b422131e94e9c602e5560a432b36b97f703", "a24f23a476578361aecd8a568191cc907c24240e" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jan 23 15:40:25 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 23 15:40:25 2024 +0100" }, "message": "Merge changes from topic \"db/emad\"\n\n* changes:\n feat(ff-a): add impdef field to ffa_memory_access\n feat(ff-a): update FF-A version for sp_test_ffa.c tests\n feat(ff-a): update FF-A version for memory sharing tests\n" }, { "commit": "a24f23a476578361aecd8a568191cc907c24240e", "tree": "b38806323ed4a33d91d27b0f18d563c1635f8f7c", "parents": [ "899dcedd9938549a19eb1a2ed474544c27f59520" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed Nov 15 18:23:40 2023 +0000" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Mon Jan 22 18:49:54 2024 +0000" }, "message": "feat(ff-a): add impdef field to ffa_memory_access\n\nAdd impdef field to the endpoint memory access descriptor as\nintroduced by FF-A v1.2.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ieb2808a5b4a8773cb4729c5aa10a6a0223ed8039\n" }, { "commit": "899dcedd9938549a19eb1a2ed474544c27f59520", "tree": "2236fca01ad4eb4ceeed0446d3909f66945b7540", "parents": [ "b34fe10c8ea998f3a1d8d9a40ba0f52ab5e30670" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jan 12 14:46:54 2024 +0000" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Mon Jan 22 18:49:54 2024 +0000" }, "message": "feat(ff-a): update FF-A version for sp_test_ffa.c tests\n\nThe version set during these test is the version the spmc sees\nthe secure partitions as for later tests. Therefore update these\nversions to v1.2 to allow the memory sharing test to pass once\nthe endpoint memory access descriptor is updated in the next patch.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: I86357c8b4f6c2f2465eced184ed617b05e7fa4bf\n" }, { "commit": "b34fe10c8ea998f3a1d8d9a40ba0f52ab5e30670", "tree": "c565a7445d6b0405317fd64ec559fa49d98e04e1", "parents": [ "6eec0b422131e94e9c602e5560a432b36b97f703" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed Jan 17 15:10:52 2024 +0000" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Mon Jan 22 18:49:49 2024 +0000" }, "message": "feat(ff-a): update FF-A version for memory sharing tests\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: I647ad7d5cac7942dd24f5c5cc339943225821be8\n" }, { "commit": "8ba06f324d4a1047aed7bc584e4c2ae635e197cc", "tree": "53362acfaff93d33931dfda2e0d023fc70de3188", "parents": [ "6eec0b422131e94e9c602e5560a432b36b97f703" ], "author": { "name": "Michal Simek", "email": "michal.simek@amd.com", "time": "Mon Jan 22 12:14:24 2024 +0100" }, "committer": { "name": "Michal Simek", "email": "michal.simek@amd.com", "time": "Mon Jan 22 12:16:51 2024 +0100" }, "message": "fix(xilinx): wire Xilinx platforms in docs\n\nWire Xilinx platform docs to fix build errors when\nmake DEBUG\u003d1 V\u003d1 doc is called.\n\nFixes: 30b8bc2aadb8 (\"docs(versal-net): add Versal NET documentation\")\nFixes: e52f311919f3 (\"docs(versal): add versal documentation\")\nSigned-off-by: Michal Simek \u003cmichal.simek@amd.com\u003e\nChange-Id: I52f4cf31bec2716a2f8b84a1f01335e387d39556\n" }, { "commit": "dbb6634fa8a3b32c377db68d3e4de2ca99bcaf7f", "tree": "26adad399deaa5a5e4bd37ade4c43c511a01884a", "parents": [ "6eec0b422131e94e9c602e5560a432b36b97f703" ], "author": { "name": "Akshay Belsare", "email": "akshay.belsare@amd.com", "time": "Thu Jan 18 06:25:52 2024 +0000" }, "committer": { "name": "Akshay Belsare", "email": "Akshay.Belsare@amd.com", "time": "Mon Jan 22 11:06:27 2024 +0100" }, "message": "fix(xilinx): update test skip list\n\nUnexpected errors are observed from the firmware for some test suites\ndue to conflict of SMC ID from those and SiP service SMC IDs.\n\nAdding the tests suites to the test skip list.\n\nChange-Id: I1e77fe4d12223f93bd335e3d7c438ef6bd374712\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\n" }, { "commit": "6eec0b422131e94e9c602e5560a432b36b97f703", "tree": "32af6d4c80b149691948c6e3e064b70a25fb9b4d", "parents": [ "93c3c3809933914a4f104c901aec7e6f9c54cd79", "13887ac63d4186a851ae2a916c112cb6229c6e63" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 18 14:36:04 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 18 14:36:04 2024 +0100" }, "message": "Merge \"feat(mpam): add MPAM system registers access test\"" }, { "commit": "93c3c3809933914a4f104c901aec7e6f9c54cd79", "tree": "309cebbf43a67056a2be4a918c1b122a24589053", "parents": [ "ea94738603d09be1399337f0976f89f951c35e6a", "0c0f0eb414a0b93888ec5e1bff68f90de071c1d2" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Jan 17 17:29:42 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 17 17:29:42 2024 +0100" }, "message": "Merge \"fix(spm): dropping hypervisor retrieve tests\"" }, { "commit": "0c0f0eb414a0b93888ec5e1bff68f90de071c1d2", "tree": "309cebbf43a67056a2be4a918c1b122a24589053", "parents": [ "ea94738603d09be1399337f0976f89f951c35e6a" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jan 17 14:08:52 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jan 17 14:08:52 2024 +0000" }, "message": "fix(spm): dropping hypervisor retrieve tests\n\nThe Hypervisor retrieve request tests have been merged\nand due to merging timing, missed capturing the failures\nintroduced with the hafnium changes [1].\n\nThis patches temporarily removes the hypervisor retrieve\nrequest tests, to unblock the ci.\nOnce we have fully fixed the issues we can re-insert\nthe tests.\n\n[1] https://review.trustedfirmware.org/q/topic:%22db/emad%22\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ic57d46e1fef3159b0d792667ede6afd98339a720\n" }, { "commit": "13887ac63d4186a851ae2a916c112cb6229c6e63", "tree": "e49867e623b38a26d977d84b2a21b1f382f523cf", "parents": [ "ea94738603d09be1399337f0976f89f951c35e6a" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jan 04 15:22:52 2024 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Jan 16 12:43:23 2024 -0600" }, "message": "feat(mpam): add MPAM system registers access test\n\nAdded a test which reads MPAM system registers to ensure that\nEL3 is giving permission to Non-secure EL2 to access these registers.\n\nChange-Id: Ie701a19c9682df6d6aeaec086954e275afff1843\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "ea94738603d09be1399337f0976f89f951c35e6a", "tree": "41b0b558a54f4e96a42ef4989d0910ea1f773fa1", "parents": [ "ec2eda8cf0faba3097570400ee4d07b736053efa", "028712b494ac24627f88e355af2864a54d81ba29" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jan 16 17:18:58 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 16 17:18:58 2024 +0100" }, "message": "Merge changes from topic \"km/test_hypervisor_retrieve_request\"\n\n* changes:\n test(memory share): fragmented hypervisor retrieve request\n feat(memory share): support sending fragmented messages.\n test(memory share): multiple receiver hypervisor retrieve request\n feat(memory share): send multiple receiver regions\n test(memory share): hypervisor retrieve request\n refactor(spm): `ffa_memory_access` constructors\n refactor(ffa_helpers): use bitfields for memory access bitmaps\n" }, { "commit": "028712b494ac24627f88e355af2864a54d81ba29", "tree": "2a7c9db438c29eb37773029975f30e8eedbebf1c", "parents": [ "0d4f5ffaeb91f57e37819d69092bdf38aeac13d0" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Dec 06 15:50:33 2023 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 11 16:08:18 2024 +0000" }, "message": "test(memory share): fragmented hypervisor retrieve request\n\nChecks that the hypervisor retrieve request from section 17.4.3 of FF-A\nv1.2 REL0 is supported, when the request does not fit in a single\nfragment.\n\nChange-Id: I34c24251e2ed131758ce692dc538de704746e488\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "0d4f5ffaeb91f57e37819d69092bdf38aeac13d0", "tree": "9336eb6404b034baf8b9a9ed76aa88744078f25f", "parents": [ "1f48892a72dc34dbdfc1d27ae4708a243150eef3" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Fri Oct 13 20:03:16 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 11 16:07:24 2024 +0000" }, "message": "feat(memory share): support sending fragmented messages.\n\nUpdates `memory_init_and_send` to allow sending memory share messages\nacross multiple fragments.\nTests for this functionality will be added in the next commit.\n\nChange-Id: I6a47735415a8fed1d15322499f1d08cc3e1fd6a2\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "ec2eda8cf0faba3097570400ee4d07b736053efa", "tree": "c20c42d734fc3dd1cfa4f69d3d840ecc44d6972b", "parents": [ "be4850c9345512f37da32c520367fc2a775303e7", "40134f85e03edebf147e03113c86582eefb6732d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jan 11 15:16:16 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 11 15:16:16 2024 +0100" }, "message": "Merge changes from topic \"od/rme-smmu\"\n\n* changes:\n docs(smmu): add smmu test engine header\n test(smmu): secure peripheral access prevented\n refactor(smmu): secure side DMA rand and memcpy\n" }, { "commit": "1f48892a72dc34dbdfc1d27ae4708a243150eef3", "tree": "7bba68b0223332faa26a4bbee16656a3f776db1e", "parents": [ "1331a8c0e861331e7ea9a140a2adea398988faaa" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Mon Dec 04 21:28:25 2023 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 11 14:08:37 2024 +0000" }, "message": "test(memory share): multiple receiver hypervisor retrieve request\n\nChecks that the hypervisor retrieve request from section 17.4.3 of FF-A\nv1.2 REL0 is supported, when specifying multiple recievers.\n\nChange-Id: I55e9f25aedaa408ab015115d5bab72bf17b22d25\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "1331a8c0e861331e7ea9a140a2adea398988faaa", "tree": "10fac1901bd460455d6ffa877666a8d5afff55f7", "parents": [ "3d879b8d66caf9d1f2b4e2a4c5333987bb74e4b8" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Sep 14 16:25:15 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 11 14:08:37 2024 +0000" }, "message": "feat(memory share): send multiple receiver regions\n\nUpdates `memory_init_and_send` to allow passing more than one receiver.\nTests for this functionality will be added in the next commit.\n\nChange-Id: I51d92d74f64bfebfa3d49ff6d5066050087b44ef\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "3d879b8d66caf9d1f2b4e2a4c5333987bb74e4b8", "tree": "f2e37b988b49f36f01acf13471cacc6b7c33e8a2", "parents": [ "367ff54c829a41e5b223683805e2cf80f8882201" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Fri Jun 16 10:32:08 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 11 14:08:36 2024 +0000" }, "message": "test(memory share): hypervisor retrieve request\n\nChecks that the hypervisor retrieve request from section 17.4.3 of FF-A\nv1.2 REL0 is supported.\n\nSpecifically, the tests:\n1. Sends a FFA_MEM_SHARE/FFA_MEM_LEND/FFA_MEM_DONATE message from the\n tftf target to the SPMC.\n2. Sends a hypervisor retrieve request from the tftf target to the SPMC.\n3. Verify the contents of the FFA_MEM_RETRIEVE_RESP message against the\n previously sent message.\n4. Invoke reclaim interface for SPMC to free memory owned by the handle.\n\nChange-Id: If27d8d5b515c5e468977ed4f5f4ddeb86e44c5df\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "40134f85e03edebf147e03113c86582eefb6732d", "tree": "c20c42d734fc3dd1cfa4f69d3d840ecc44d6972b", "parents": [ "a91f0d7e67846729f2c480d414819ff37e287d83" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Dec 21 16:56:27 2022 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 11 11:39:33 2024 +0100" }, "message": "docs(smmu): add smmu test engine header\n\nThis header is originated from the SMMUv3TestEngine component and added\nto the tree for documentation purposes. A possible future intent is to\nre-use this header in the SPM SMMU test cases implementation.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I563020aa02db888396ab8631d197c21e8d483fb8\n" }, { "commit": "a91f0d7e67846729f2c480d414819ff37e287d83", "tree": "b91550102b119bf5059d0da4626a25bee15ea4b4", "parents": [ "e71ec9c4923590f5732b6d5e647ea1f3cc895d36" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Oct 24 11:23:12 2023 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 11 11:39:31 2024 +0100" }, "message": "test(smmu): secure peripheral access prevented\n\nCheck a secure peripheral upstream to an SMMU cannot perform\ntransactions to a realm region.\n\nAdd an NS region to cactus SP, to be used as a placeholder for the DMA\ntest engine to perform a RAND48 operation.\nThe test scenario changes the NS buffer PAS into Realm. It then queries\na SP to initiate a secure DMA operation on this buffer through the SMMU.\nThe operation is expected to fail as a secure DMA transaction to a Realm\nregion fails SMMU GPC checks.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I5d061e5f0fc16cc9c14089f95e0ff5e49cb2a9cd\n" }, { "commit": "e71ec9c4923590f5732b6d5e647ea1f3cc895d36", "tree": "0475fb8e7e1a441df6319b60a215bc797655f078", "parents": [ "be4850c9345512f37da32c520367fc2a775303e7" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Feb 28 18:57:26 2022 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 11 11:36:11 2024 +0100" }, "message": "refactor(smmu): secure side DMA rand and memcpy\n\nAdd operation, source and size parameters to the cactus command\ninitiating an operation to the DMA test engine through the SMMU.\nAdd RAND48 operation support to the DMA test engine.\nRefactor to a common run_testengine helper exercised by MEMCPY\nand RAND48 SMMU operations.\nCactus SP dispatches either one of the operation based on the\noperation id passed from TFTF.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I2ca7c303e8fef6baf99fe4b64b33102546b9ff30\n" }, { "commit": "367ff54c829a41e5b223683805e2cf80f8882201", "tree": "3e3245f6b10fe26ca64dcafd8d67705705c299e0", "parents": [ "92aa770261f62af56268659db38fed9465953106" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Nov 01 15:05:37 2023 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Jan 09 12:33:42 2024 +0000" }, "message": "refactor(spm): `ffa_memory_access` constructors\n\nAdd `ffa_memory_access_init_permissions` and\n`ffa_memory_access_init_permissions_from_mem_func` helpers.\n\nChange-Id: I9a5bb09e7f230a65decff7f58a0c188aff3e7449\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "92aa770261f62af56268659db38fed9465953106", "tree": "db987ff7f7c9b03bbc1a5db68faffc0f32766a5d", "parents": [ "be4850c9345512f37da32c520367fc2a775303e7" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Oct 11 18:48:01 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Jan 09 12:26:42 2024 +0000" }, "message": "refactor(ffa_helpers): use bitfields for memory access bitmaps\n\nInstead of doing the bit-manipulation manually, these types can be\ndeclared as structs where the fields are given explicit bitwidths. The\ncompiler will generate the appropriate bit-manipulation automatically.\n\nChange-Id: I0d4754466b1e70d1b36cb039bfe9e7701ebbd60f\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "be4850c9345512f37da32c520367fc2a775303e7", "tree": "a73c69dcd51c898c95d30adb56d4aba5b96b564d", "parents": [ "94f19612d745152bc872b076ceb30cd411c2cbc2", "86f312a40a1aff596f6adfd18bebc8a28411c414" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jan 08 10:47:35 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 08 10:47:35 2024 +0100" }, "message": "Merge changes from topic \"rmm-1.0-eac4\"\n\n* changes:\n test(realm): testcase for multiple rec validations\n test(rmm): add testcase for multiple rec on multiple cpu\n" }, { "commit": "94f19612d745152bc872b076ceb30cd411c2cbc2", "tree": "61644a087b4d2e3685facdf96c1655b81eb69c13", "parents": [ "ec482824eba8020f9b36b6b7a563ac3c84064c23", "d4de7ed3487a229aed40938fdf365cc2932f7a88" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jan 05 20:39:47 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 05 20:39:47 2024 +0100" }, "message": "Merge \"fix: validate if FFA_SECONDARY_EP_REGISTER is supported\"" }, { "commit": "86f312a40a1aff596f6adfd18bebc8a28411c414", "tree": "1c42ed26352bf1425bc598f17e26a0647c83e555", "parents": [ "affbae8163ad25534cfe4dbc4bcda5a3372d0062" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Dec 21 11:33:03 2023 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 05 16:38:11 2024 +0100" }, "message": "test(realm): testcase for multiple rec validations\n\nAdded negative testcase for CPU_ON\nand PSCI_COMPLETE calls\n\nChange-Id: Ie14140825de6b00ca6dcf9d758ee9b68a427bf8a\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "affbae8163ad25534cfe4dbc4bcda5a3372d0062", "tree": "b75a233b78259620329179a4f6e3d8e3a3b18d79", "parents": [ "ec482824eba8020f9b36b6b7a563ac3c84064c23" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Aug 22 12:51:11 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 05 15:35:50 2024 +0000" }, "message": "test(rmm): add testcase for multiple rec on multiple cpu\n\nTest creates and enter 8 recs on different CPUs.\nExercises CPU_ON, CPU_OFF and PSCI_AFFINITY_INFO\nfrom realm.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Iecc58ea79bfde28f307d1df99680d707e57a1d80\n" }, { "commit": "ec482824eba8020f9b36b6b7a563ac3c84064c23", "tree": "de4d9353d2c7136ed6fe79d8a81556adca0d504c", "parents": [ "a0e46db319398df36e4bd3c49e391c814079b898", "ecb8a7689ff60a315b1413e640b6962f90ca9f42" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Jan 04 16:31:55 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 04 16:31:55 2024 +0100" }, "message": "Merge \"build: disable RWX segment warnings for the EL3 payload\"" }, { "commit": "ecb8a7689ff60a315b1413e640b6962f90ca9f42", "tree": "de4d9353d2c7136ed6fe79d8a81556adca0d504c", "parents": [ "a0e46db319398df36e4bd3c49e391c814079b898" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Jan 04 11:56:37 2024 +0000" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Jan 04 11:58:02 2024 +0000" }, "message": "build: disable RWX segment warnings for the EL3 payload\n\nThe EL3 payload is not currently linked with the RWX segment warning\ndisabled, which is causing it to fail some builds in the CI.\n\nChange-Id: I35815b721f027c226bcd932ed3177ee19caf318a\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "a0e46db319398df36e4bd3c49e391c814079b898", "tree": "f1310729aadb309b5efc5173fa9eaa0b3a1c4e7c", "parents": [ "84ad6157a4e83834fa925b80534ca5414c368586", "e15bc803ed76eee496f95cba2df45aa292500090" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Dec 20 15:28:23 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 20 15:28:23 2023 +0100" }, "message": "Merge \"feat(handoff): update register signature\"" }, { "commit": "84ad6157a4e83834fa925b80534ca5414c368586", "tree": "ee6e72c6abfc54d2d552754ee8bf16b2d3ba5ac7", "parents": [ "d616be5afd3a372b30dd34d572608ac56703fc13", "fef8621d2d5ce3ce67a4ba3013292b7382b92355" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Dec 19 16:07:10 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Dec 19 16:07:10 2023 +0100" }, "message": "Merge changes I6809fdab,I4da6c7d2,Ia57a0ddb\n\n* changes:\n test(realm): testcase for RMI_RTT_SET_RIPAS reject\n feat(realm): add support for RSI_IPA_STATE_GET/SET\n fix(realm): fix issue in rtt teardown\n" }, { "commit": "fef8621d2d5ce3ce67a4ba3013292b7382b92355", "tree": "3704d2a1a84205cedf36191c7f2ebb648ecce4a2", "parents": [ "bb772193864856ce5d0da9b3534316b7bc4fc3d3" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 17 12:15:38 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Dec 19 15:09:04 2023 +0200" }, "message": "test(realm): testcase for RMI_RTT_SET_RIPAS reject\n\nAdd testcase for realm to call rsi_ipa_state_set,\nhost will reject and call RMI_RTT_SET_RIPAS\nre-enter rec with response RSI_REJECT\n\nChange-Id: I6809fdabba580b23269aedc2aa844b15fbcce981\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "bb772193864856ce5d0da9b3534316b7bc4fc3d3", "tree": "c2ecde3c3eaea03acb70d6fa5166e178591a1fd2", "parents": [ "d5b30b42f36d9fc80d0a26c238129a2488f6a068" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 09 16:08:28 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Dec 19 15:08:13 2023 +0200" }, "message": "feat(realm): add support for RSI_IPA_STATE_GET/SET\n\nAdd support for realm API rsi_ipa_state_set, rsi_ipa_state_get\nAdd testcase for following\n* Realm calls rsi_ipa_state_set to change RIPAS\u003dRAM,\n* Host accepts and call RMI_RTT_SET_RIPAS\n* Realm verifies RIPAS change was successful\n\nChange-Id: I4da6c7d25faa62afde1d0f682510bac6c8445821\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "d616be5afd3a372b30dd34d572608ac56703fc13", "tree": "ca0730ea552687bea0f70fb6c5c58ac763d9876c", "parents": [ "f0da2001c7779ca7bc23dce4bab9bd314cdcb0e6", "f5b46352dbafdbca62b2cf10b4410213c62612c8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Dec 18 19:27:16 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Dec 18 19:27:16 2023 +0100" }, "message": "Merge changes Ic47879dd,Ic093aea6\n\n* changes:\n test(smc_fuzzing): add tsp testing\n refactor(smc_fuzzing): add multi cpu capability\n" }, { "commit": "e15bc803ed76eee496f95cba2df45aa292500090", "tree": "684b021e9625392ed31f006b559c1f103be4503c", "parents": [ "f0da2001c7779ca7bc23dce4bab9bd314cdcb0e6" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Dec 18 15:21:13 2023 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Dec 18 16:17:14 2023 +0000" }, "message": "feat(handoff): update register signature\n\nThe existing register signature was changed from 0x6ed0ff to account for\n0xff being a value that is regularly found in memory [1].\n\n[1] https://github.com/sjg20/firmware_handoff/commit/f70c184905607f6b1d074a5de9aa407a5d92344b\n\nChange-Id: Ib217f1b68df9e534fc61604c88eea4560ecb9dc2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "d5b30b42f36d9fc80d0a26c238129a2488f6a068", "tree": "24919472b3b2c4ddff3ec5e8ea61aa0bbe633986", "parents": [ "f0da2001c7779ca7bc23dce4bab9bd314cdcb0e6" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Oct 25 22:38:45 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 18 12:32:37 2023 +0000" }, "message": "fix(realm): fix issue in rtt teardown\n\nUse IPA WIDTH to decide if adr is protected\nor unprotected. Do not treat ripas empty as unprotected adr\n\nChange-Id: Ia57a0ddb12a76e4eec9a1c03e9302d959dd0ac31\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "f0da2001c7779ca7bc23dce4bab9bd314cdcb0e6", "tree": "7fa45077f184a0cfa9eb12a771e590ad046e2d92", "parents": [ "ac806965a1d44d1ef98919df8241a8d54141f7ca", "334217c012558149603f8909159a819ecaf71403" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Dec 18 12:54:33 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Dec 18 12:54:33 2023 +0100" }, "message": "Merge changes Id92d77d2,I1916cf5b\n\n* changes:\n test(realm): remove unwanted arg from realm API\n test(realm): fix realm_printf string\n" }, { "commit": "334217c012558149603f8909159a819ecaf71403", "tree": "7fa45077f184a0cfa9eb12a771e590ad046e2d92", "parents": [ "a276b20c477aab869c74f687484d480c4a289f0a" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 18 10:28:53 2023 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 18 12:53:06 2023 +0100" }, "message": "test(realm): remove unwanted arg from realm API\n\nRemove unwanted arg plat_mem_pool_size\nfrom host_create_realm_payload and\nhost_create_activate_realm_payload API\n\nChange-Id: Id92d77d2ed8944c0e038cb62459247f0d17e516c\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "a276b20c477aab869c74f687484d480c4a289f0a", "tree": "e3166fc186f557e471e3207b6602d17540adfb80", "parents": [ "ac806965a1d44d1ef98919df8241a8d54141f7ca" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 18 10:07:43 2023 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Dec 18 13:53:03 2023 +0200" }, "message": "test(realm): fix realm_printf string\n\nRemove extra Realm: string from realm printf\ncorrect the print format\n\nChange-Id: I1916cf5bda23aab2cdee59457872353c108148c7\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" } ], "next": "ac806965a1d44d1ef98919df8241a8d54141f7ca" }