)]}' { "log": [ { "commit": "2ba1e7812b494abdfb8f440a161f0ded24bee72a", "tree": "891b504323eff7bb91489d10ae33ed84613a15c3", "parents": [ "ab680e816552ea29184084482fdf63e2f94cd46a" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Mar 26 16:50:18 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Mar 26 17:15:06 2025 -0500" }, "message": "fix(errata_abi): update Cortex-A710 errata list\n\nThis patch updates the out-of-date parameter of Cortex-A710\u0027s\n2058056 erratum in Errata ABI test.\n\nChange-Id: I194eb7fea0504b532c2e15710fbe4b455b7e631b\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "ab680e816552ea29184084482fdf63e2f94cd46a", "tree": "8e10eed6f9d1169da2c006f4d017ebe4dcafa4ea", "parents": [ "9d84ad1ceb8256e942213537602c6434577b7bc0", "2bd104e2fc8bdf1355ae88ad3e16af9773c1541f" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Mar 25 05:17:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 25 05:17:06 2025 +0100" }, "message": "Merge \"fix(realm): Fix the LPA2 flag setting for BRBE test\"" }, { "commit": "2bd104e2fc8bdf1355ae88ad3e16af9773c1541f", "tree": "8e10eed6f9d1169da2c006f4d017ebe4dcafa4ea", "parents": [ "9d84ad1ceb8256e942213537602c6434577b7bc0" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Fri Mar 21 15:35:27 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Mar 25 04:49:16 2025 +0100" }, "message": "fix(realm): Fix the LPA2 flag setting for BRBE test\n\nThis patch fixes the LPA2 flag setting for BRBE test.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: Id7c53739cc92275a7018a44c2a3b8fdcf74ec25e\n" }, { "commit": "9d84ad1ceb8256e942213537602c6434577b7bc0", "tree": "f1069ac2c0ef008601b2892cae5960fba6665787", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "fb96b980c85d916b55c78b7d22e5b6d8e086ca54" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "message": "Merge changes from topic \"kc/fuzz\"\n\n* changes:\n test(fuzz): add FF-A fuzzing\n test(fuzz): Fix single feature testing\n" }, { "commit": "fb96b980c85d916b55c78b7d22e5b6d8e086ca54", "tree": "2a4c319dd3761099924e160acca59d4075bf749d", "parents": [ "2b6c140b52790beebbb921dd0311efefb0bb0c5c" ], "author": { "name": "Kathleen Capella", "email": "katcap01@u203721.austin.arm.com", "time": "Thu Apr 25 17:09:33 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Mar 11 12:10:59 2025 -0500" }, "message": "test(fuzz): add FF-A fuzzing\n\nAdd necessary components for FF-A calls to be used in fuzzing framework\nincluding bias tree, `run_ffa_fuzz` helper function, makefile additions,\nand initial SMC description file with FF-A smc calls.\n\nCan use ffa_smc_calls.txt to generate necessary header files.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ib19714342d31cacd818471686a7e4c8910fed5c3\n" }, { "commit": "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "tree": "a0ec5b6bff32d2fa1294f33af597c0d54558306e", "parents": [ "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "c8f5a2ee90f2b376da910f08170af4c4dc7396ae" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "message": "Merge \"test: test the save restore logic for brbcr_el1\"" }, { "commit": "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "tree": "62adf8c4bbb438943acb6e46b52170803509a17b", "parents": [ "3d43731d485b1405c5a224f65a7c2d381d46b093", "43980f9070347622ec9b9ff1b360357a954e96f2" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Sun Mar 09 01:28:21 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sun Mar 09 01:28:21 2025 +0100" }, "message": "Merge \"test(realm): Fix Realm tests marking all memory as RAM\"" }, { "commit": "2b6c140b52790beebbb921dd0311efefb0bb0c5c", "tree": "333ef24bffd0e8a85ea998f3ae2da4c3b8c83047", "parents": [ "3d43731d485b1405c5a224f65a7c2d381d46b093" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Mar 06 10:01:19 2025 -0600" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Fri Mar 07 15:57:39 2025 -0600" }, "message": "test(fuzz): Fix single feature testing\n\n This change fixes an issue where a user provides a new feature\nthat can be fuzzed independently of the current setup of fuzzing.\nCurrently compile fails will cause issues if single feature fuzzing\nis desired and the automated flow will disable sets that are not in\nthe SMC description file. There are some small changes to the source\nfiles to enable this behavior for both SDEI and Vendor. There is also\na change to the automated scripting.\n\nChange-Id: Ic768e9f1b285225f12f23c1e36acb668088ad129\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\n" }, { "commit": "43980f9070347622ec9b9ff1b360357a954e96f2", "tree": "64495265719ce7b62c47bc5f720d88eec5ee15e9", "parents": [ "90506fbda56864b578980bc2d433f2ba38207e61" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Mar 07 20:35:21 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Mar 07 20:35:21 2025 +0000" }, "message": "test(realm): Fix Realm tests marking all memory as RAM\n\nRealm tests only need access to part of DRAM.\nChange only required region RIPAS to RAM.\n\nChange-Id: Ia0120841e51726785062992e8a32dcd8a924a325\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "3d43731d485b1405c5a224f65a7c2d381d46b093", "tree": "c8d15de87f5a5155e57a145d43cbeb18c118f33f", "parents": [ "9b63fa56b4e21ecb87d409c6a95d1d3d5ee06376", "5668f34a89dfcee72c2a8e6aa443c7436f341d61" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "message": "Merge \"fix: add split workaround check in Errata ABI test\"" }, { "commit": "9b63fa56b4e21ecb87d409c6a95d1d3d5ee06376", "tree": "7fc7ec71d57eec9732f6793a5ed15d3e2b354824", "parents": [ "90506fbda56864b578980bc2d433f2ba38207e61", "55d5db87b83b6a073ed3c954d455b862e7b2e7fe" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Mar 07 11:06:37 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 07 11:06:37 2025 +0100" }, "message": "Merge changes Ic57f049d,Ifc98b8c6,I7e34a007,I20cbb9d0\n\n* changes:\n test(realm): extend ripas tests for planes\n test(realm): enhance realm memory exception tests for planes\n test(realm): add test for multi rec planes\n test(realm): validate NS EL1/EL2 context is preserved by RMM\n" }, { "commit": "c8f5a2ee90f2b376da910f08170af4c4dc7396ae", "tree": "625509a3d6d8838e0c31c9e89fbf23ed9361d15f", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Tue Feb 04 15:22:01 2025 -0600" }, "committer": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Mar 06 16:55:05 2025 -0600" }, "message": "test: test the save restore logic for brbcr_el1\n\nThis patch tests the save/restore logic by enabling\nbranch recording at NS-EL2. Additionally this\npatch also tests the trap logic when FEAT_FGT is enabled\nand a Realm tries to access any FEAT_BRBE related registers.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I176ea6feaf01d42cfd6231dc65a9470da8d1e37c\n" }, { "commit": "55d5db87b83b6a073ed3c954d455b862e7b2e7fe", "tree": "0019d75c61f3cbac06bc2f1e25d5944c8f9f3880", "parents": [ "7d3b999376c7416584639411f36bdadf877060d3" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Mar 03 12:56:04 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 21:08:59 2025 +0000" }, "message": "test(realm): extend ripas tests for planes\n\nTest that accessing page with RIPAS\u003dEMPTY from\nPlane N causes plane exit to P0.\n\nChange-Id: Ic57f049d0fa0140630aa7bfc0702a2dc729967a8\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "90506fbda56864b578980bc2d433f2ba38207e61", "tree": "b77200b91f6f52038c3754cc14fc2896d407f149", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120", "b3d451c3bb4b3b6c6a03aaaa8e1a785c5a4ca0a5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Mar 06 21:39:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 06 21:39:06 2025 +0100" }, "message": "Merge \"fix: add xpaci instruction to exception report\"" }, { "commit": "7d3b999376c7416584639411f36bdadf877060d3", "tree": "c22c6390ab2ec7977af1483c1d4dbf56bd2d388f", "parents": [ "bd729193dcdb19a5f5fa9b259770f1d1f365bad0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 25 15:39:55 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 19:50:15 2025 +0000" }, "message": "test(realm): enhance realm memory exception tests for planes\n\nExtend memory exception tests for planes.\n\nChange-Id: Ifc98b8c67e85b04b36a78f16971d17f05d6a87d2\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "5668f34a89dfcee72c2a8e6aa443c7436f341d61", "tree": "9a7778183d2dedaa383e4c517a4a17dae6a7fa49", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Mar 04 02:01:16 2025 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Mar 06 12:43:08 2025 -0600" }, "message": "fix: add split workaround check in Errata ABI test\n\nThis patch adds support to validate split workarounds\nas part of Errata ABI CPU Features testcase. It also\nimproves the test case, making sure it also\nruns on lead cpu.\n\nChange-Id: Ic21fffdf20714ad639e92ad0be96d2f154f37f04\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "bd729193dcdb19a5f5fa9b259770f1d1f365bad0", "tree": "00c47d7308aee2d02a16a3d4a5fbacaf7cf4407d", "parents": [ "78effaa2c47b04abd68273bdea4ebb4f6f9455c0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 24 17:02:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:57:56 2025 +0000" }, "message": "test(realm): add test for multi rec planes\n\nTest exercises SMC_PSCI_CPU_ON from aux plane.\nRequest is first routed to P0 and then to Host.\nHost enters P0 and then P1 on all CPUs.\n\nChange-Id: I7e34a0070ffa7305b97a0d93de62b64042771a18\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "78effaa2c47b04abd68273bdea4ebb4f6f9455c0", "tree": "9ffb7b9430ee5600da7f8e0cd5cd557752ea85fa", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 07 10:30:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:18:01 2025 +0000" }, "message": "test(realm): validate NS EL1/EL2 context is preserved by RMM\n\n- Test validates that NS EL1/EL2 registers are preserved while\n entering and exiting realm world.\n- Test validates that accessing s2por_el1 in realm causes data abort.\n\nChange-Id: I20cbb9d0d59474507f89ee7cf8e127fff4706610\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "992c62b427ad7fc425ec3c02e6c2f5e98e94d120", "tree": "1267fde5c9244b900105a5d2d073c4d938ef7e0d", "parents": [ "3e496b408634030405c5fa5fbcb8b8babcebfb30", "eb2dd23469c8a5f3624b60ce21fab8299785fe4e" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 05 20:46:05 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 05 20:46:05 2025 +0100" }, "message": "Merge changes from topic \"kc/stmm\"\n\n* changes:\n refactor: move StMM to cactus tertiary\n feat(hob): add boot-time prints for cactus-stmm HOB list\n refactor(cactus): map boot information regions\n feat(hob): add HOB definitions to TFTF\n feat(spm): add STMM cactus partition\n" }, { "commit": "b3d451c3bb4b3b6c6a03aaaa8e1a785c5a4ca0a5", "tree": "4f962c5a8e86e12e0bdd0526bbb59dda55efe9b7", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Feb 13 14:24:06 2025 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Mar 04 10:37:16 2025 -0600" }, "message": "fix: add xpaci instruction to exception report\n\nWhen reporting an exception with ENABLE_PAUTH\u003d\u003d1 calling xpaci\nbefore printing the ELR value will remove the PAC and make the\npointer readable.\n\nChange-Id: I45339dbb3396f403768ea3ee780d0c5010da44c4\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "3e496b408634030405c5fa5fbcb8b8babcebfb30", "tree": "730acf129621c21de4c680668a5b8391446f74b1", "parents": [ "6164898b4355bf1f311a78f0796a75baf7f50983", "dc26dfe297eaed205fdbf8a0f98706044a97032d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Feb 28 14:41:46 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 28 14:41:46 2025 +0100" }, "message": "Merge changes I701d7f7f,If85b8c4c\n\n* changes:\n test(realm): fix bug in RMI_RTT_SET_S2AP command helper\n test(realm): add support for s2poe/pie for planes\n" }, { "commit": "dc26dfe297eaed205fdbf8a0f98706044a97032d", "tree": "730acf129621c21de4c680668a5b8391446f74b1", "parents": [ "de01b5dd3ae940a16ad9f370ad1e734190553e73" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 25 16:12:48 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 28 13:01:34 2025 +0000" }, "message": "test(realm): fix bug in RMI_RTT_SET_S2AP command helper\n\npass correct rec adr to RMI_RTT_SET_S2AP command.\nRSI_MEM_SET_PERM_INDEX can be called from any rec.\n\nChange-Id: I701d7f7f9de80f305d10d2582c614b3090fc2ac5\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "de01b5dd3ae940a16ad9f370ad1e734190553e73", "tree": "9dcf2ef13e4449a8322e044da38a1ed94579e171", "parents": [ "6164898b4355bf1f311a78f0796a75baf7f50983" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 02 21:17:11 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 28 13:01:16 2025 +0000" }, "message": "test(realm): add support for s2poe/pie for planes\n\nAdd support for s2poe/pie for planes.\nUpdate planes test to run with s2poe/s2pie\nboth enabled and disabled.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If85b8c4cff9e8fe43978088beaf848fe4b2b9a40\n" }, { "commit": "6164898b4355bf1f311a78f0796a75baf7f50983", "tree": "858cebc6186fb65cc28fc02883dec4a112534603", "parents": [ "42dd088203e40911c67106d46cfccde58d55e1b5", "716c8cc0951fb6a3e212d4bd9b79ea0b6f9bdf9b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 26 13:15:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 26 13:15:06 2025 +0100" }, "message": "Merge \"fix(lib/pcie): bdf macro\"" }, { "commit": "716c8cc0951fb6a3e212d4bd9b79ea0b6f9bdf9b", "tree": "858cebc6186fb65cc28fc02883dec4a112534603", "parents": [ "42dd088203e40911c67106d46cfccde58d55e1b5" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Feb 25 18:22:45 2025 +0000" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Feb 26 11:33:37 2025 +0000" }, "message": "fix(lib/pcie): bdf macro\n\nThe existing PCIE_CREATE_BDF macro is a non standard way of deriving bdf\nvalue. This fix assigns 3 bits for function number, 5 bits for device\nnumber and 8 bits for bus. This bdf value is used as TDISP function id\nwhile passing it to DSM. Using a wrong bdf value results the TDISP\ncommand to fail.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I31301be4dfc9bd2409da73e54715f73079a921cb\n" }, { "commit": "42dd088203e40911c67106d46cfccde58d55e1b5", "tree": "48f1d07ae117eadadd1c0496cc0a8ad895abff3b", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd", "c779d0d0ac9faf894963675dcccb6110e3f0229a" ], "author": { "name": "Sandrine Afsa", "email": "sandrine.afsa@arm.com", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "message": "Merge changes from topic \"xlnx_fix_custom_inval_entry\"\n\n* changes:\n fix(versal): platform definition of invalid entry\n feat(tftf): new interface to get an invalid entrypoint address\n" }, { "commit": "eb2dd23469c8a5f3624b60ce21fab8299785fe4e", "tree": "5e4c4725690951c6339593a72f39466cf6eea1b6", "parents": [ "8808a945590fbc4138c0961717da75ddc383ede0" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Fri Feb 07 18:41:54 2025 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 23:05:23 2025 -0600" }, "message": "refactor: move StMM to cactus tertiary\n\nReuse existing cactus tertiary partition for StMM testing rather than\nadding an additional partition.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I0c40758cc8f5e7cb2239c80346ad785c0d6888e5\n" }, { "commit": "8808a945590fbc4138c0961717da75ddc383ede0", "tree": "992e6e95734b14bddb4dddc924c19122fccc6f69", "parents": [ "8ac4dd8ce81ba17121c62b4d39925ae6b62d7998" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Jan 07 15:45:39 2025 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 23:05:15 2025 -0600" }, "message": "feat(hob): add boot-time prints for cactus-stmm HOB list\n\nAt boot time, print HOB headers and contents.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ic634f045cacdbc8e318836eba85982a93f55fc0f\n" }, { "commit": "8ac4dd8ce81ba17121c62b4d39925ae6b62d7998", "tree": "3508ab1dc7469d12b9df34ab1e1a19f558a8910f", "parents": [ "bde3eab2e68bc0059b5ccfc83a13759287eb9cf4" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Dec 17 19:37:33 2024 +0000" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 13:52:45 2025 -0600" }, "message": "refactor(cactus): map boot information regions\n\nMap the boot contents regions and add optional mapping for boot info\ndescriptor contents depending on whether they will be accessed.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I3dcbff07e9ee33008fa7f64fc74b06a1c42aa5dd\n" }, { "commit": "bde3eab2e68bc0059b5ccfc83a13759287eb9cf4", "tree": "90acb838f69c8c620e7790409df205077a8fe65b", "parents": [ "e8a17a905ca1c20acb1b9248ac725ab847bddc42" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Dec 09 14:04:43 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Mon Feb 24 13:51:36 2025 -0600" }, "message": "feat(hob): add HOB definitions to TFTF\n\nAdd necessary HOB structure definitions and HOB library to TFTF.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I1a81cd99df52436a077a71030244ca642122497a\n" }, { "commit": "e8a17a905ca1c20acb1b9248ac725ab847bddc42", "tree": "4f6dd3a344ab642adacdbddd6d06a409ee356b8e", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Thu Dec 05 18:28:29 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Fri Feb 21 09:42:27 2025 -0600" }, "message": "feat(spm): add STMM cactus partition\n\nAdd another instance of cactus S-EL1 partition, using\nStMM manifest.\n\nThis is to validate HOB generation at build-time.\n\nThe manifest contains memory region nodes using the\nsame node names as in the StMM partition manifest,\nbut changed the ranges to align with memory map of\nbase FVP. The device region nodes have been dropped,\nas they didn\u0027t affect the creation of the HOB list.\n\nDefined the UUID for the partition in the test code,\nand refactored slightly some of the code paths,\nso it has an RXTX buffer and is able to do the basic\nFF-A setup tests.\n\nAlso added the cactus-stmm node to the sp_layout\nfile.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: I05971fc9d63f03bd7ea43b3bcaba5b6362a44ca0\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "c779d0d0ac9faf894963675dcccb6110e3f0229a", "tree": "66a0d99df1847e1ac663da0a378e4d92f3ba63bd", "parents": [ "1e4f7a064f08205a0a37922e660b238be04a8137" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:43:37 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:47 2025 +0000" }, "message": "fix(versal): platform definition of invalid entry\n\nAdd platform specific function to return custom entry address.\n\nChange-Id: I58785a8b7c197e4dae3ac9a29f8d23c29d5cb5e3\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "1e4f7a064f08205a0a37922e660b238be04a8137", "tree": "ccf0e6f9e63ee23a7b249eed564ceedafcee9035", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:40:56 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:16 2025 +0000" }, "message": "feat(tftf): new interface to get an invalid entrypoint address\n\nTFTF test for invalid entry address in cpu hotplug, validates\nfor default entry address 0x0 which doesn\u0027t account for platforms\nfor which 0x0 is a valid address. Added function to retrieve invalid\nentry address for default scenario and platform implementation to\nretrieve specific custom invalid entry address.\n\nChange-Id: I9f109acc8d0443dabd3088cb31852900e8e07853\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "2f2bd013021b4723d42c168f613c4c0ca37223bd", "tree": "968260569451b377582640305eea94d206d9a42c", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e", "af8934c8574fd64bef6ac4b0201c2144b78c8fd7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "message": "Merge \"test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\"" }, { "commit": "af821ebb6fa509f8036b2304c313883842d2c93e", "tree": "d1abf091b8992adae634a55a98ced19523f676f1", "parents": [ "b298a166f8490bb997b794ab404afa5eaae15fa1", "effca4c7db126c7e171256a8a85b60e599274c4d" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Feb 12 18:51:15 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 12 18:51:15 2025 +0100" }, "message": "Merge \"refactor(errata_abi): add Cortex-X925 and update Cortex-X4\"" }, { "commit": "effca4c7db126c7e171256a8a85b60e599274c4d", "tree": "d1abf091b8992adae634a55a98ced19523f676f1", "parents": [ "b298a166f8490bb997b794ab404afa5eaae15fa1" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 16:52:23 2025 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 19:03:22 2025 -0600" }, "message": "refactor(errata_abi): add Cortex-X925 and update Cortex-X4\n\nUpdate errate list for Cortex-X4 and add Cortex-X925\nerratum list and support.\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: Ib4e3324e7289d8e400e9a7f90e384d36cdd8bbcb\n" }, { "commit": "b298a166f8490bb997b794ab404afa5eaae15fa1", "tree": "a185504f6b740a4bfc63fc62f8ee8d91f08d4791", "parents": [ "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "5bccf1d188115e268101024018d26b710c86d3c9" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Feb 06 11:59:13 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 06 11:59:13 2025 +0100" }, "message": "Merge \"fix(realm): fix PMU save/restore registers\"" }, { "commit": "5bccf1d188115e268101024018d26b710c86d3c9", "tree": "a185504f6b740a4bfc63fc62f8ee8d91f08d4791", "parents": [ "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "message": "fix(realm): fix PMU save/restore registers\n\nRemove pmxevcntr_el0 and pmxevtyper_el0 registers\nfrom saving/restoring as aliases for pmevcntrN_el0\nand pmevtyperN_el0, selected by pmselr_el0.sel.\n\nChange-Id: I3def527c46d53c3203f7c3ebc565a2aaf282309c\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "tree": "010803c4d3fb8186d23cfd2f54f923c8271b45cd", "parents": [ "23ec8506918aff276b21b9543831d4825855906d", "82cd82e9868b1f381a5c8d84195657e1583cfca1" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "message": "Merge \"feat(rme): add tests for FEAT_MPAM on Realms\"" }, { "commit": "23ec8506918aff276b21b9543831d4825855906d", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658", "c398c8f7248e9aec29bbc41c94e41005d539863c" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 11:56:02 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 11:56:02 2025 +0100" }, "message": "Merge \"fix(realm): fix realm PMU tests\"" }, { "commit": "82cd82e9868b1f381a5c8d84195657e1583cfca1", "tree": "c7be244d493e784e55df370f501d8c3ba9275523", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jan 17 17:37:42 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Feb 04 15:01:14 2025 +0000" }, "message": "feat(rme): add tests for FEAT_MPAM on Realms\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6e138cbf121793bdaaa3a44824c0dbff74daced1\n" }, { "commit": "c398c8f7248e9aec29bbc41c94e41005d539863c", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jan 16 14:35:48 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Feb 04 11:38:28 2025 +0000" }, "message": "fix(realm): fix realm PMU tests\n\n- FEATURE_PMU_NUM_CTRS field in feature_flag was used\nto pass number of PMU event counters in realm creation.\nThe width of this field was set to 4, which was not\nenough to pass numbers \u003e 15 and was causing PMU tests\nfailures in FVP configuration with more than 15 event\ncounters implemented.\n- This patch removes all FEATURE_XXX macros for setting\nfeature_flag and replaces them with the corresponding\nRMI_FEATURE_REGISTER_0_XXX to match feature register 0.\n- In host_set_pmu_state() function was setting PMSELR_EL0\nto incorrect value 0 instead of 31 to select PMU cycle\ncounter for configurations with no event counters implemented.\n- Test host_realm_pmuv3_mul_rec() was running incorrectly\nwith number of event counters set to 0 or 31.\n- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0\ncan be constrained unpredictable depending on the\nvalue of PMSELR_EL0.SEL and number of accessible event\ncounters. See corresponding TF-RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573\nThis patch fixes host_set_pmu_state() and\nhost_check_pmu_state() functions to avoid unpredictable access\nto these registers.\nThis patch makes Realm PMU tests pass for all possible FVP\nconfigurations clusterN.pmu-num_counters\u003d[0...31].\n\nChange-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "f00a425e1592bd410ff249c1baab8f3b067b1658", "tree": "ec2b7f39414b02fb21446494409ae1729930aaa3", "parents": [ "042541196fbdd814a7c04ee4e24be94f1a2ab4ef", "cd46f276f845a4628982e85dfc38054fc94aa5c3" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Feb 03 15:46:20 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 03 15:46:20 2025 +0100" }, "message": "Merge \"feat: specify the secure partition package for an SP\"" }, { "commit": "042541196fbdd814a7c04ee4e24be94f1a2ab4ef", "tree": "0852b3939e094f0d2fd4b848f3ebb617bfa6efd0", "parents": [ "c8943ba881807922cb84e357461f5482475a47c3", "47078f35247dcb85f5a1ce8ea0bc52d3aee74451" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "message": "Merge changes I7c4ad397,I92e0aeef\n\n* changes:\n test(realm): fix multi rec PMU tests\n test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n" }, { "commit": "c8943ba881807922cb84e357461f5482475a47c3", "tree": "a951dd70d63e29f3616dc48935890f96c8b52fab", "parents": [ "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "message": "Merge changes from topic \"fuzzinit\"\n\n* changes:\n test(fuzz) adding fuzzing for vendor-el3 smccc calls\n test(fuzz) adding fuzzing for all SDEI calls\n test(fuzz): Capability for random inputs\n" }, { "commit": "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c", "tree": "fcf9d81e4b95ffd31ccf36df51df4e1bd0e19221", "parents": [ "0fa7d21bf97d14283ebf8c3df866cd05afaff91e" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jul 23 16:42:16 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 15:13:10 2025 -0600" }, "message": "test(fuzz) adding fuzzing for vendor-el3 smccc calls\n\nChange-Id: I4fd64c0a4c02de6d67a372c9c4bf86bcb9e4d091\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "0fa7d21bf97d14283ebf8c3df866cd05afaff91e", "tree": "b1927aea547dcd718dccc20301cbc301d986faec", "parents": [ "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jun 18 11:17:01 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 14:03:27 2025 -0600" }, "message": "test(fuzz) adding fuzzing for all SDEI calls\n\nadded constraints for all calls\nadded fuzzer feature to start at arbitrary call number\nadded fuzzer features for function exclusion, fuzzer starting/ending call\nworked on additional fuzzing for event_register\n\nChange-Id: I9814b8387ea9e0fb00b53adbdbe0f8429845924e\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "47078f35247dcb85f5a1ce8ea0bc52d3aee74451", "tree": "03562b94399c44ff32b0c1f81d1c8e35016d8e4f", "parents": [ "414346805fa6589643780f6f9ce181facf2e1271" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 16 18:54:24 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 17:44:19 2025 +0000" }, "message": "test(realm): fix multi rec PMU tests\n\n- set different values of PMU event counters for each rec\n- check PMU counters are preserved for each rec\n\nChange-Id: I7c4ad3971d4a10b4515be0dfe096bebf8d903c71\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "tree": "ff6e9cd81f0c19684cf5b58067d02d58f1738b19", "parents": [ "506b98f78e4bb38314129f85da27523f18dd8f8f", "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "message": "Merge changes I7a3b9103,I590fc5a1,Ie6924bcb,I484cbd32\n\n* changes:\n test(realm): add testcase to enter all planes\n test(realm): handle permission fault for planes\n test(realm): add support for planes shared buffer\n test(realm): add plane PSI interface\n" }, { "commit": "af8934c8574fd64bef6ac4b0201c2144b78c8fd7", "tree": "33c29f9b95a29b2b879fc8055d994787b5e79fce", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Fri Jul 26 14:51:14 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Jan 31 16:48:58 2025 +0000" }, "message": "test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\n\n* This patch adds a test that suspends to affinity level 2 with another\n CPU running in a different power domain.\n\n* Previously with the bug identified and resolved in commit (01959a1),\n the function \"psci_is_last_cpu_to_idle_at_pwrlvl\" checked only one\n power domain when suspending to level2. This meant that if there was\n a cpu running outside the power domain of the calling CPU, the suspend\n request would be allowed. But in this case, the request should be\n denied. This test case validates this behaviour and ensures the\n request is denied.\n\n* This patch also adds the following global variables to parameterise\n and reuse the existing functions for the new test.\n * test_should_suspend - an boolean array that allows you to leave\n some CPUs running.\n * test_should_deny - a boolean to specify if the suspend request\n should be denied.\n * cpu_finished - an array of events so that the running CPUs know\n when to terminate.\n\n* Additionally this patch also adds a function to get a CPU that is\n in a different cluster to the lead CPU.\n\nRefer to TF-A commit (01959a1) for more information on the bug.\n\nChange-Id: Ib163aa8d5347baeaa47d1ae6f59599f1c68c11a8\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb", "tree": "506eaf722681380325bde2a5a9de784697915ba9", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Mar 15 12:49:22 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 10:23:24 2025 -0600" }, "message": "test(fuzz): Capability for random inputs\n\nAdding model for random inputs to SMC calls using a\nconstraint mechanism with a multi tiered sanity\nmetric.\n\nChange-Id: Ia750fa57359baa424f1af273ba24483ae7330c38\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "506b98f78e4bb38314129f85da27523f18dd8f8f", "tree": "da255312e5288c911622d83ee21bf8f2cf790a83", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "43d421bb292984fdc56269fb3e87e619ca0892d3" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "message": "Merge \"test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\"" }, { "commit": "414346805fa6589643780f6f9ce181facf2e1271", "tree": "69b825442caff18f8b25d6eee80140c80832d176", "parents": [ "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Dec 05 14:57:48 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 14:53:41 2025 +0000" }, "message": "test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n\ntest for RSI_PLANE_REG_READ/WRITE command\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I92e0aeef48c9b2abe26e5d3b2ea62669a22d4f8b\n" }, { "commit": "158208e895d38d659d216c793d42d132ed90e598", "tree": "86cf20c9982b4b186bcc17944cd9f569701f6fe4", "parents": [ "a0736c3dbf83f3c00ca98c83534070be259fb822" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 10:12:41 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:23 2025 +0000" }, "message": "test(realm): add testcase to enter all planes\n\nTestcase creates realm with all 4 planes.\nEnters all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I7a3b9103e1fbcfe98117c02827624a2fc2d24fc2\n" }, { "commit": "a0736c3dbf83f3c00ca98c83534070be259fb822", "tree": "4ab625c28b93f9fe02b4072720ab05a342175b26", "parents": [ "69cae79515b85f13a3ee957474231e51e879c4d8" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 09:34:35 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:12 2025 +0000" }, "message": "test(realm): handle permission fault for planes\n\nAdd support for handling permission fault in planes.\nSet s2ap in RTTs.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I590fc5a1c43357b117fa5cb76e8c699c4c7eebad\n" }, { "commit": "69cae79515b85f13a3ee957474231e51e879c4d8", "tree": "80f41a9c19830d92bf024f5c9eabf65e2b505a5a", "parents": [ "9110508906774bb3949fa5609a5d767021a6a4e8" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 04:30:00 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:53:44 2025 +0000" }, "message": "test(realm): add support for planes shared buffer\n\n- Add support for per plane shared buffer.\n- Map shared buffer in all Aux RTT if\n realm uses multiple RTTs.\n- Support realm_printf for all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie6924bcb9e9bb3b8c368f796d33f84f4f6821935\n" }, { "commit": "9110508906774bb3949fa5609a5d767021a6a4e8", "tree": "8233efd6cb8467288ae76544c0682c4e89766dc2", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 05:29:55 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:53:25 2025 +0000" }, "message": "test(realm): add plane PSI interface\n\nAdd Plane service routine interface.\nAux plane can communicate with primary plane using PSI\nPSI uses hvc conduit from aux plane.\nAdd initial printf support for planes\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I484cbd32791970c6e22c5d63e13b43807f4f3c06\n" }, { "commit": "43d421bb292984fdc56269fb3e87e619ca0892d3", "tree": "2d0fe5cbece559a93ff6eb935d36bc0dadf2a4d8", "parents": [ "ff52ad6026cbbd688f9c381a48110148e01dcf45" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Sep 11 12:01:56 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jan 30 11:51:52 2025 -0600" }, "message": "test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\n\nTesting was conducted using FVP Version 11.26.11\non Cortex-X3, Cortex-X4, Neoverse-V2, Neoverse-V3\nand Cortex-X925. Additionally, negative testing\nwas performed on Cortex-X2.\n\nThis patch tests SMCCC_ARCH_WORKAROUND_4 [1] for CVE_2024_7881 [2]\n[1]: https://developer.arm.com/documentation/den0028/latest\n[2]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881\n\nChange-Id: I4c33b7a9372236ce3ef38f9d1786d5794bb7ddbc\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "tree": "05125c5f936c21bd2d9cc5915bf9544333182bd9", "parents": [ "079c37c7aaf219182d7061427e22c65aaa416b37", "ff2f1150099940a2767381df1701c9007eec8e68" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "message": "Merge changes from topic \"qemu_tests\"\n\n* changes:\n fix(test): compile error in test_irq_spurious_gicv2.c\n feat(timer): support PPI timer interrupts\n" }, { "commit": "079c37c7aaf219182d7061427e22c65aaa416b37", "tree": "31c1eabeaf17fcec944f87cee1464f62697ab5eb", "parents": [ "ff52ad6026cbbd688f9c381a48110148e01dcf45", "3fa036df6a185bcc50ef1c50b79b272e39fd7bc1" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jan 30 13:20:26 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 30 13:20:26 2025 +0100" }, "message": "Merge \"test(realm): fix compilation errors\"" }, { "commit": "3fa036df6a185bcc50ef1c50b79b272e39fd7bc1", "tree": "31c1eabeaf17fcec944f87cee1464f62697ab5eb", "parents": [ "ff52ad6026cbbd688f9c381a48110148e01dcf45" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 30 09:21:53 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 30 09:28:51 2025 +0000" }, "message": "test(realm): fix compilation errors\n\nFix compilation errors when LOG_LEVEL is verbose.\n\nChange-Id: Ic87a7ad901e1cd57a20d6ae14fbd4d8165e4e168\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "ff52ad6026cbbd688f9c381a48110148e01dcf45", "tree": "f6365f83d2b39cbfbe06fe6470fa4c970c226412", "parents": [ "1209ea4679769070dd7bf7c316354ce840060378", "6681b7a6fc142f8b1ba0f97d41d239fe6e874c37" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Jan 29 19:17:23 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 29 19:17:23 2025 +0100" }, "message": "Merge \"fix: skip CPU cycle allocation for SP vCPU to reach message loop\"" }, { "commit": "1209ea4679769070dd7bf7c316354ce840060378", "tree": "026fea5427fe5a749b88b201f0b988609420585f", "parents": [ "3e9115dc182c6240f9289912b6f528853b510e10", "7c193632dc959bb7070a667cdc1ad6171892cd35" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jan 28 17:32:05 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 28 17:32:05 2025 +0100" }, "message": "Merge \"feat(ff-a): add v1.2 fields to RXTX header\"" }, { "commit": "7c193632dc959bb7070a667cdc1ad6171892cd35", "tree": "026fea5427fe5a749b88b201f0b988609420585f", "parents": [ "3e9115dc182c6240f9289912b6f528853b510e10" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Jan 28 11:22:18 2025 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Jan 28 11:26:47 2025 +0000" }, "message": "feat(ff-a): add v1.2 fields to RXTX header\n\nAdd the new fields introduced in v1.2 to the partition message header.\nThis will fix the tests that were failing due to the `offset` being too small.\n\nChange-Id: I58ddd8f6897d0e46b7c7f754fde7ecddd012a0ca\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "6681b7a6fc142f8b1ba0f97d41d239fe6e874c37", "tree": "ce9e06d8cf11d20bfe42b02034bd2a7a2255f053", "parents": [ "3e9115dc182c6240f9289912b6f528853b510e10" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Nov 01 16:27:44 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jan 27 07:38:50 2025 -0600" }, "message": "fix: skip CPU cycle allocation for SP vCPU to reach message loop\n\nWith the support added in Hafnium SPMC for secondary CPU cold boot,\nsecondary execution contexts of SPs dont need a round of CPU cycles\nthrough ffa_run to reach the message loop.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ib02f51abb31d30329d43f0937ba30d721504bc53\n" }, { "commit": "cd46f276f845a4628982e85dfc38054fc94aa5c3", "tree": "de4c2033cf870b1646a0fda8fcae1520fdbad6ea", "parents": [ "4686bbfe1f0122f07aa65f2d9c11fca81557ec54" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Nov 25 11:18:34 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jan 13 13:34:53 2025 +0000" }, "message": "feat: specify the secure partition package for an SP\n\nSpecify the Transfer List format for the partitions:\n- cactus-secondary\n- cactus-tertiary\n- Ivy\n\nThe entrypoint offset changed when using TL as the package\nfor SPs.\n\nChange-Id: I044e3575861876ce108f0e65822d56d68bfdb427\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "3e9115dc182c6240f9289912b6f528853b510e10", "tree": "bb75b4c42e4b096554dacad9bc3b399284f04097", "parents": [ "4686bbfe1f0122f07aa65f2d9c11fca81557ec54", "5abab7674959cb2fa3211e5199ac3115e72e86dc" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jan 13 14:18:16 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 13 14:18:16 2025 +0100" }, "message": "Merge changes I62946a18,Ida808b9d,Ic71af8d0,I505a4a05\n\n* changes:\n test(realm): add support for RSI Planes ABI\n test(realm): add AUX RTT support for planes\n test(realm): allocate memory for multiple planes\n test(realm): add initial support for planes\n" }, { "commit": "5abab7674959cb2fa3211e5199ac3115e72e86dc", "tree": "86f2a0e558571dc8e5f616e31d1564f8fbf11d5a", "parents": [ "8f5dae9067e545618830abda9fc5f143c58e7c9f" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 04:57:53 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 10 16:39:05 2025 +0000" }, "message": "test(realm): add support for RSI Planes ABI\n\nAdd Planes RSI support.\nAdd helpers to setup initialize and enter planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I62946a185c47fe77a04f42751d0b0a467d41ceee\n" }, { "commit": "4686bbfe1f0122f07aa65f2d9c11fca81557ec54", "tree": "02bf7741ffc9dad822742b79fc90caa9839b9a7f", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c", "b24cc1347491fd4ac89212970eba80f3fae5438f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 09 13:57:14 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 09 13:57:14 2025 +0100" }, "message": "Merge changes from topic \"bk/smccc_feature\"\n\n* changes:\n fix(brbe): report BRBE support with later revisions\n test(SMCCC): test SMCCC_ARCH_FEATURE_AVAILABILITY\n refactor(SMCCC): use a macro to check for the SMCCC version\n feat: add register definitions needed for SMCCC_ARCH_FEATURE_AVAILABILITY\n" }, { "commit": "8f5dae9067e545618830abda9fc5f143c58e7c9f", "tree": "733dc1d8d0aeda4faae063a30dc7c46da1c1e96f", "parents": [ "31b2552f3cc950e1244377e9246a6c85467d59a0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 03:38:31 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 09 10:28:51 2025 +0000" }, "message": "test(realm): add AUX RTT support for planes\n\n- Add support for new RMI_RTT_AUX ABIs and helpers.\n- Create and destroy aux mappings for realm creation\n with multiple planes and multiple RTTs.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ida808b9d311e8a662587257e015b0f62c110ac3b\n" }, { "commit": "31b2552f3cc950e1244377e9246a6c85467d59a0", "tree": "2b2c7558cf3359fdff5b87b9c7c064d474d060b5", "parents": [ "1ea7a8612622a7f3baf14ef3bb94d59d898231b4" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 03:13:27 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 09 10:25:59 2025 +0000" }, "message": "test(realm): allocate memory for multiple planes\n\n- Update realm create helpers to allocate memory\n and copy multiple plane images.\n- Also allocate memory for multiple Aux RTTs.\n- Increase realm heap by 2 MB.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ic71af8d0b156ad60d8cb8c5bafe6f9b7df8280c7\n" }, { "commit": "1ea7a8612622a7f3baf14ef3bb94d59d898231b4", "tree": "2e0a208919dae9e7adfa2c7c95693bac3470fbca", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 02:36:40 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 09 09:52:07 2025 +0000" }, "message": "test(realm): add initial support for planes\n\n- Added changes to RMI feature register\n and RmiRealmParams for planes\n- Updated realm create helpers to support planes\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I505a4a05f222e2a28eed33bded3bae687fc29eec\n" }, { "commit": "b24cc1347491fd4ac89212970eba80f3fae5438f", "tree": "02bf7741ffc9dad822742b79fc90caa9839b9a7f", "parents": [ "7b7ca22f1b54632558663f5816d103105ce3aaec" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 28 10:35:35 2024 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "fix(brbe): report BRBE support with later revisions\n\nThere is BRBEv1p1 now, but the accessor reports the BRBE is not\nsupported altogether when that is present. The result is that the test\nis skipped. Fix the condition to return support with newer revisions\ntoo.\n\nChange-Id: Iab51b4016934d4b9eef125a6c4010ea419c99b81\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "7b7ca22f1b54632558663f5816d103105ce3aaec", "tree": "e3a9111c51ba449327eeeecbb638f03b5dab3cc6", "parents": [ "566f07da79dc559c405e79327be47740b7a66686" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 13:33:18 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "test(SMCCC): test SMCCC_ARCH_FEATURE_AVAILABILITY\n\nThis test calls the function with each valid argument and checks that\nevery bit is set if its relevant feature is present in the system. It\nalso fails the test if any set bit in the return value has not been\nchecked. This should serve as a reminder to update this test for every\nnew feature that is implemented.\n\nOnly feature that tfa supports are tested with the expectation that new\nones will be added in the future.\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I801326a49810bb76bfc3b9d06780d416dcc32a40\n" }, { "commit": "566f07da79dc559c405e79327be47740b7a66686", "tree": "02ce87e53805217055fd73771267ba2f8f9edac0", "parents": [ "4e282424143dbd73cd0248d470d03cccb9005f42" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 13:31:48 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "refactor(SMCCC): use a macro to check for the SMCCC version\n\nThis is similar to other macros that skip the test if a condition is failed.\n\nChange-Id: If8ff8b29473151edf1872636bce9ee0950851c42\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "4e282424143dbd73cd0248d470d03cccb9005f42", "tree": "b5da9ecc48fe84d374c9e04de6a0d3e2c7f8aa0d", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 14:34:13 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:16 2025 +0000" }, "message": "feat: add register definitions needed for SMCCC_ARCH_FEATURE_AVAILABILITY\n\nAlso slightly optimised some redundant feature functions\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I6dcc11060a2f3697a8aa41443e9cfc665b2b7c74\n" }, { "commit": "a4d7972176c2fdc3c66e6ba3347d24f65bac670c", "tree": "ca528cadd776c98afa91e1be5bd5b728b0c51b3c", "parents": [ "963872ed94fc063dc8597dc034ce7e45362e348f", "d1a7f4d2bd6b4867a71366b58b00759724ef99d1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Dec 20 10:03:31 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 20 10:03:31 2024 +0100" }, "message": "Merge \"feat: add tests to check SCTLR2, THE and D128 sysregs\"" }, { "commit": "d1a7f4d2bd6b4867a71366b58b00759724ef99d1", "tree": "7439900358c0026fe7c781e725e6ba0b1c3fd37b", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Tue Nov 26 12:50:47 2024 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 19 14:51:47 2024 +0000" }, "message": "feat: add tests to check SCTLR2, THE and D128 sysregs\n\nThis patch adds test cases for verifying that the system registers of\nFEAT_SCTLR2, FEAT_THE and FEAT_D128 (FEAT_SYSREG128) are working\ncorrectly by performing a series of reads and writes to the registers.\n\nChange-Id: I5c102daa358a7ec5d1801395bc875e9850e83939\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "963872ed94fc063dc8597dc034ce7e45362e348f", "tree": "4ac27884ec2a40c67d82cd00bc81675532521e19", "parents": [ "97925dae1fb8530102010a15f39aec568e75b9e9", "d8092a550b85c6369aabf96430c9b06cc8444298" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Dec 18 20:17:48 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 18 20:17:48 2024 +0100" }, "message": "Merge \"feat(mbedtls): update minimum version to latest MbedTLS v3.6.2\"" }, { "commit": "d8092a550b85c6369aabf96430c9b06cc8444298", "tree": "6303bdd1e607363980fa32b41205d1b71d3ed055", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Dec 17 09:14:50 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Dec 18 18:19:50 2024 +0200" }, "message": "feat(mbedtls): update minimum version to latest MbedTLS v3.6.2\n\nUse the latest MbedTLS version 3.6.2 as the minimum to stay in \nsync with TF-A.\n\nChange-Id: I4c70ec87805a99ba0cfaf2c23cfea51133d0daf7\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "97925dae1fb8530102010a15f39aec568e75b9e9", "tree": "c012e0e20c412bfb51f078c119f30017b7bca277", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38", "97dd9c3fe59af613c6dd7404a1f349abce3ec3d2" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Dec 18 14:08:37 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 18 14:08:37 2024 +0100" }, "message": "Merge \"fix: omit printing an error on mbedtls not cloned\"" }, { "commit": "97dd9c3fe59af613c6dd7404a1f349abce3ec3d2", "tree": "c012e0e20c412bfb51f078c119f30017b7bca277", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Dec 18 10:53:25 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Dec 18 11:00:21 2024 +0100" }, "message": "fix: omit printing an error on mbedtls not cloned\n\nUsing Makefile\u0027s wildcard statement in place of a shell find command to\nprevent the error message below when mbedtls submodule is not cloned:\n\n find: ‘ext/mbedtls/include’: No such file or directory\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I9677aa4e97485b597e00ba0bdf76967f9093afe9\n" }, { "commit": "5d10ae70d57bc836d417b7a7592ecc96a528bc38", "tree": "ebc140f0239edb16dfb4341f9d12ca33cd364cb2", "parents": [ "dc18ace1a36a4f684f1e4c7ef193a34c563d75c1", "1c06e7712d4fe6efe068f60ad8b177931dc346e8" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Dec 16 14:52:57 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Dec 16 14:52:57 2024 +0100" }, "message": "Merge \"fix(realm): rmi_realm_params structure is not zeroed upon realm creation\"" }, { "commit": "1c06e7712d4fe6efe068f60ad8b177931dc346e8", "tree": "ebc140f0239edb16dfb4341f9d12ca33cd364cb2", "parents": [ "dc18ace1a36a4f684f1e4c7ef193a34c563d75c1" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Dec 16 13:26:48 2024 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Dec 16 13:26:48 2024 +0000" }, "message": "fix(realm): rmi_realm_params structure is not zeroed upon realm creation\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I2513a6977625f98e7d81f9cb57ee3e724fcbff81\n" }, { "commit": "dc18ace1a36a4f684f1e4c7ef193a34c563d75c1", "tree": "49bb31a7dc6df8d5b09217a4e38f5e493ffa87d8", "parents": [ "a07460f4520b05d6f01624a857e6b6c0a6a41235", "1ab21e5e0f05680e5a30093fe6a7eff99fdcb150" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 12 22:42:25 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Dec 12 22:42:25 2024 +0100" }, "message": "Merge \"feat(fpmr): test FPMR register access\"" }, { "commit": "a07460f4520b05d6f01624a857e6b6c0a6a41235", "tree": "ae13a7c6fcfdd64db025b24b280d4127ac7df246", "parents": [ "d25c577499280db4b1923f924210b9590039ab0c", "425b45479fbe0b49d15ac1dfe8d8f1b532cd29e9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Dec 06 15:47:10 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 06 15:47:10 2024 +0100" }, "message": "Merge changes from topic \"od/fix-sri-handling\"\n\n* changes:\n fix(spm): handle ME in indirect msg tests\n fix(spm): omit enabling/disabling SRI physical interrupt\n fix(spm): fill TX buffer again after undelegate\n" }, { "commit": "425b45479fbe0b49d15ac1dfe8d8f1b532cd29e9", "tree": "ae13a7c6fcfdd64db025b24b280d4127ac7df246", "parents": [ "f93aef1e0ff8e8d11716c23c44f8cbc51060778a" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Nov 13 18:39:45 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 17:41:57 2024 +0100" }, "message": "fix(spm): handle ME in indirect msg tests\n\nFor the following tests involving FF-A indirect messaging:\ntest_ffa_indirect_message_sp_to_vm\ntest_ffa_indirect_message_sp_to_vm_rx_realm_fail\n\nSending an indirect message from the SP triggers the SRI NS interrupt\nwhile the SP runs and initiates a managed exit.\nBack in TFTF, add a handler for processing the SRI and resume the SP\nafter managed exit using the dedicated cactus command.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I95918fd78e9dec20470307d60c8dd31d6c5b5a7c\n" }, { "commit": "f93aef1e0ff8e8d11716c23c44f8cbc51060778a", "tree": "8dd46da9ae2a912839e164daeba4d01850f327fa", "parents": [ "6ab3fe91df8c0dd9d1589411d1ed168247ad8edf" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 15:41:34 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 16:17:27 2024 +0100" }, "message": "fix(spm): omit enabling/disabling SRI physical interrupt\n\nThe SPMC takes care of enabling the SRI physical SGI interrupt on all\ncores. Omit doing it from TFTF.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ie1a4bdc898213107959eaac912aae5c6058114f5\n" }, { "commit": "6ab3fe91df8c0dd9d1589411d1ed168247ad8edf", "tree": "48ee3ae83f90f8d2d8830b040baf3e3803e95322", "parents": [ "d25c577499280db4b1923f924210b9590039ab0c" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 11:46:28 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 14:23:07 2024 +0100" }, "message": "fix(spm): fill TX buffer again after undelegate\n\nSimilarly to the fix done in [1], the RME undelegate operation on TX\nbuffer scrubs its contents in test_ffa_memory_share_fragmented_tx_realm,\nso re-init the TX buffer again with the fragment after undelegate.\n\n[1] https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/30027\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I6a716d42f79474b8d884826a0a09eac01e487176\n" }, { "commit": "d25c577499280db4b1923f924210b9590039ab0c", "tree": "468fb7e0e6ff7d864f3483fe72c1c23d4edba18e", "parents": [ "67a3ffba147f4a5d996fa5e307fd59389925434e", "cc8543823e6104d67e74892cd6d84c52f3cc4a14" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 29 12:02:27 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 29 12:02:27 2024 +0100" }, "message": "Merge changes If007b517,I56a9f5c5\n\n* changes:\n feat(realm): call RMI_PDEV ABIs from host realm mgmt\n refactor(realm): define PCIe helpers\n" }, { "commit": "cc8543823e6104d67e74892cd6d84c52f3cc4a14", "tree": "468fb7e0e6ff7d864f3483fe72c1c23d4edba18e", "parents": [ "5929bfe75a40577efa77cf23a2fc4057ced92e7e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:29:13 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 18:10:28 2024 +0000" }, "message": "feat(realm): call RMI_PDEV ABIs from host realm mgmt\n\nInitial support to invoke RMI PDEV ABIs from host realm management. The\nPDEV management testcase host_test_rmi_pdev_calls does PDEV create, get\nstate, get aux count, communicate, set public key, stop, destroy calls.\nThese calls internally retrieve device certificate, extract public key,\nand establish a secure session with the PCIe device.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: If007b5170cbaa932c4f18a01a825a8dc0b752f26\n" }, { "commit": "5929bfe75a40577efa77cf23a2fc4057ced92e7e", "tree": "054341aebc883a57faab006f4d700d596c323203", "parents": [ "67a3ffba147f4a5d996fa5e307fd59389925434e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:28:00 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 18:10:28 2024 +0000" }, "message": "refactor(realm): define PCIe helpers\n\nThis patch refactors the existing PCIe and DOE\nhelpers to define generic helpers to make them\nreusable across more tests.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I56a9f5c59715c7916f3f737ed6d3af94b0e3679f\n" }, { "commit": "67a3ffba147f4a5d996fa5e307fd59389925434e", "tree": "d1330dfede15a22679f428e3aee6b66960038d99", "parents": [ "3e72cded39f20bebe6f22d31b4f9833f44b90128", "d49873af4a07659bbf8fd9c07119a7d85f9cda89" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 28 17:22:36 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 28 17:22:36 2024 +0100" }, "message": "Merge \"feat(neoverse_rd): add TFTF support for RD-V3 platform\"" }, { "commit": "3e72cded39f20bebe6f22d31b4f9833f44b90128", "tree": "dd9321d639bd4bc727e416fb15a6ebecf316fd96", "parents": [ "58a254ae181886efcf6e691789a67d5c145eecf4", "23788fa84220f873a21f8bca53d973e240ae8740" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 17:17:37 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 28 17:17:37 2024 +0100" }, "message": "Merge changes I0e386334,I744ef44e\n\n* changes:\n feat(lib): add mbedtls support\n feat(realm): add MbedTLS as submodule\n" }, { "commit": "23788fa84220f873a21f8bca53d973e240ae8740", "tree": "dd9321d639bd4bc727e416fb15a6ebecf316fd96", "parents": [ "c5f75b914824a6c3cb992596b44f1c2a116eb7d3" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 12:19:32 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 17:11:28 2024 +0200" }, "message": "feat(lib): add mbedtls support\n\nAdd support for compiling Mbed TLS from external source.\n\nThe Mbed TLS library is compiled from source pointed by MBEDTLS_DIR\nenvironment variable. Any TFTF test that includes mbedtls.mk will have\nsupport for mbedtls library. Note that by default the MBEDTLS_DIR will\npoint to the default submodule directory (ext/mbedtls).\n\nThis support is added for testing RMM capabilities related to\nDevice Assignment in RMM.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I0e386334078812e5ff5bdcffd4143732e0478b64\n" }, { "commit": "c5f75b914824a6c3cb992596b44f1c2a116eb7d3", "tree": "430308bdc5397e13e64366bbfefdde82c69bd47c", "parents": [ "58a254ae181886efcf6e691789a67d5c145eecf4" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 04:39:38 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:56:53 2024 +0000" }, "message": "feat(realm): add MbedTLS as submodule\n\nThis patch adds MbedTLS repository as a git submodule.\nThe version of MbedTLS added is v3.6.2.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I744ef44e61c85ade3d56920cfc1b8fd1a27bb045\n" }, { "commit": "d49873af4a07659bbf8fd9c07119a7d85f9cda89", "tree": "2b8e1f0c9e74cee68e382a53c12f085e6e76c2e6", "parents": [ "58a254ae181886efcf6e691789a67d5c145eecf4" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Thu Jul 25 13:45:13 2024 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Thu Nov 28 11:31:04 2024 +0000" }, "message": "feat(neoverse_rd): add TFTF support for RD-V3 platform\n\nAdd platform files to enable TFTF on RD-V3 platform.\n\nChange-Id: Icd6f512a01b1582e3251c8c0b242dc0999da0d15\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "58a254ae181886efcf6e691789a67d5c145eecf4", "tree": "5d5644927acc2f4a212ba18558c7ed57f3d1e07c", "parents": [ "ea43ac0daef913576cf214454cf81482d8cf109a", "2c2810f79e57e78d77899084b5439cbdd1aaa464" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 04:23:38 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 26 04:23:38 2024 +0100" }, "message": "Merge \"fix(realm): make PCIe tests default for testing\"" }, { "commit": "2c2810f79e57e78d77899084b5439cbdd1aaa464", "tree": "5d5644927acc2f4a212ba18558c7ed57f3d1e07c", "parents": [ "ea43ac0daef913576cf214454cf81482d8cf109a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 15 17:11:24 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 05:21:39 2024 +0200" }, "message": "fix(realm): make PCIe tests default for testing\n\nThis patch moves the PCIe DOE test to the default realm world\ntestsuite.\n\nAlso fixes some build issues and hardens the PCIe functions.\n\nNote that FVP_Base_RevC model needs to have the following\noptions enabled for the PCIe tests to work :\n\n -C pci.pcie_rc.ahci0.endpoint.doe_supported\u003d1\n -C pci.pcie_rc.ahci0.endpoint.ide_supported\u003d1\n\n\nChange-Id: Icfd6b68799b0bacb44299c6a3cf99a3c425f833d\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "ea43ac0daef913576cf214454cf81482d8cf109a", "tree": "92ec8ee102ec299ca25e55fac006d80139c28135", "parents": [ "0f744702ebd52d2efcf42db52613aee5b8991fd0", "ebce902b9f4088972070a10a3c63b168621b4588" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Nov 25 11:09:52 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 25 11:09:52 2024 +0100" }, "message": "Merge \"test(realm): add test for validating RTT calls\"" } ], "next": "0f744702ebd52d2efcf42db52613aee5b8991fd0" }