)]}' { "log": [ { "commit": "0fa7d21bf97d14283ebf8c3df866cd05afaff91e", "tree": "b1927aea547dcd718dccc20301cbc301d986faec", "parents": [ "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jun 18 11:17:01 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 14:03:27 2025 -0600" }, "message": "test(fuzz) adding fuzzing for all SDEI calls\n\nadded constraints for all calls\nadded fuzzer feature to start at arbitrary call number\nadded fuzzer features for function exclusion, fuzzer starting/ending call\nworked on additional fuzzing for event_register\n\nChange-Id: I9814b8387ea9e0fb00b53adbdbe0f8429845924e\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "3d8cd68cffa9709895f1758ea144046bf18b896a", "tree": "388308d2e41b5994b4d0931c0eded8f38094234d", "parents": [ "e95e53f8607b98d06afdd1302722d3f23dca3591" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Jul 23 14:28:15 2024 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Aug 13 12:03:07 2024 +0100" }, "message": "test(memory share): lend device memory region to sp\n\nAdd test to check that a device memory region can be successfully\nlent to an sp.\n\nThis requires some refactoring of the memory sharing test flow so\nas to use the correct memory type and cachebility attributes for\nthe memory being lent. Also limit the words being written to 1\nword for device memory so we only write to the data register of the\ndevice.\n\nAlso only map device regions from UART2 so that UART0 can be used\nby TFTF in the device sharing test.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: I9f31769679883f34e0444db75a873765776a85e9\n" }, { "commit": "1500a6f3cf9424c1f4e2d960fe6270bc664cf63e", "tree": "cc5d12ce55e72f6265fc2adc3c09d4a9f3ad3c39", "parents": [ "994e6956079c58766cefac29aaa0f97af10cd73c" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Jul 22 13:29:11 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Jul 22 13:37:30 2024 +0100" }, "message": "fix(realm): fix RMI commands arguments descriptions\n\nThis patch fixes descriptions of arguments and return\nvalues for RMI commands definitions in host_realm_rmi.h\naccording to RMM specification and TF-A RMM implementation.\nThis patch doesn\u0027t introduce any functional changes.\n\nChange-Id: I798ee57dac51ed8bbeb2fb4822788d6ae6ba2963\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "1abd8df96be1f7c5efd73ff38e8044bc5c1b6363", "tree": "e8a62fd453c65ef5ba08cca905bf74bf76535ef5", "parents": [ "b5103df4af352c9409fb0756579788d6c0732b87" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Mon Jul 01 10:03:18 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Mon Jul 01 10:12:30 2024 +0100" }, "message": "fix: fix call to `FFA_VERSION`\n\n`SKIP_TEST_IF_FFA_VERSION_LESS_THAN` was attempting to change the FF-A\nversion, when it only needed to query it. The recent change to\n`FFA_VERSION` means that attempting to change the version would fail.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: Id8572d1a4d61b17a85af44f96e3720230d35e698\n" }, { "commit": "7308b12df02634ca78f0e1ea6e4f758a8b3d8e2a", "tree": "5bd75867d077a40ebd30f5245ae7d5126524220f", "parents": [ "c884d6bf9e3aca4dc63d318eb99d6141c9353363" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Apr 16 14:02:25 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jun 27 10:57:30 2024 +0100" }, "message": "refactor: FFA_VERSION related refactors\n\n* Use an enum for FF-A versions.\n* Replace `MAKE_FFA_VERSION` macro with `make_ffa_version` function.\n* Add `ffa_version_is_valid` helper function.\n* Add `ffa_version_get_major` and `ffa_version_get_minor` helper\n functions.\n\nChange-Id: Icbc4b1fa16e826c2ec541add65aa7c14fb397f95\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "07f9671ac3f4b89bda1b9c058c60e7fc39470939", "tree": "a65a8925f6b949d4297c35da834c51e9813c1394", "parents": [ "6316e359865d3fd00f1c782c25089f974b852875", "a45649a48865a609ce854f3dda51b19517b4cbc0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jun 14 22:46:08 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 14 22:46:08 2024 +0200" }, "message": "Merge changes from topic \"ja/memory_share_64\"\n\n* changes:\n test(ff-a): add SMC64 abi to FFA_FEATURES\n test(memory share): use SMC64 rather than SMC32\n" }, { "commit": "7efea19cd6c832ea8a595ef5dc057cca721ca237", "tree": "5f387e91703069d63085e874b0c7727b15d2be80", "parents": [ "6d833ef005af59119dbbc9794a3bbfc191eb4f60" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Sep 19 16:07:09 2023 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Jun 13 13:17:35 2024 +0100" }, "message": "feat(rmi): add support for FEAT_LPA2 to the Realm Extension tests\n\nThis patch adds support to the current Realm Extension tests to\nenable and use 52 bit address size with 4KB granularity when\nFEAT_LPA2 is present.\n\nIn addition, this patch also introduces changes to support passing the\nstarting RTT level and the FEAT_LPA2 enable flag during realm creation\nso they can be used later to implement tests for FEAT_LPA2 on RMI.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I0a930735a44772e5e76d6608c969759f27129917\n" }, { "commit": "8984e729cce2c9a1ac8b87fe4e0df886a6ccd6c7", "tree": "1e2546ecd80740da5bfcb7d21bf1f03c2bdc50d2", "parents": [ "6d833ef005af59119dbbc9794a3bbfc191eb4f60" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 07 22:21:54 2024 +0100" }, "committer": { "name": "Joao Alves", "email": "joao.alves@arm.com", "time": "Tue Jun 11 14:52:02 2024 +0200" }, "message": "test(memory share): use SMC64 rather than SMC32\n\nThe SPMC supports memory sharing interfaces to use the\nSMC64 or SMC32 abis.\nThere was not functional change with this. However, making\nTF-A-Tests use SMC64 to validate that they both work.\nHafnium tests will remain using the SMC32 version of the\nABIs.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I31e275ca50973774928591eef0128f0cf0f5be8b\n" }, { "commit": "b324f4d2251094094b32c3138d9313addf443e6b", "tree": "78a6d6800935c6e1cda1a3156ab6facad65383aa", "parents": [ "6c0be80b887f8accf6908b39a7f7b41eda7327d1" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Feb 26 11:06:03 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue May 14 15:38:56 2024 +0200" }, "message": "test(realm): test for rtt_fold assigned\n\nTest for RTT_FOLD for assigned ram, assigned empty\nand assigned ns rtt entries\nFix helper to allow creating L1 block entry for unprotected IPA\n\nChange-Id: I77693f76722d60427edcb112ca58bf772c194b06\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "6c0be80b887f8accf6908b39a7f7b41eda7327d1", "tree": "267f467f11d91951f6a12ad2fae9b079f31ab3f5", "parents": [ "ecc32844365ca4745dfd92d1adeaab2f39fdeeb2" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 20 11:52:57 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue May 14 15:38:51 2024 +0200" }, "message": "test(realm): add test for rtt_fold unassigned\n\nAdd testcase for RMI_RTT_FOLD,\nfor protected IPA unassigned empty and unassigned ram RTTs.\nHost attempts to fold till max level permitted by Arch.\nFix helper to align with RMI call, remove unused code.\n\nChange-Id: Ib94efa7ba60e028bb9f765e769fe377c101a71fc\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "9668ba5730d9607609879667a19f3249a10f2c99", "tree": "812a321c9182243b86010e63d655769764e64b98", "parents": [ "b44b4753d698bb7b703198a458e78746cff0ed23" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 11:49:45 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 14:04:21 2024 +0100" }, "message": "fix(ff-a): tests for FFA_FEATURES\n\nThere are different expectations to the result to the FFA_FEATURES\ncall, provided the feature IDs for ME, SRI and NPI interrupt from\ntftf or cactus.\n\nThis patch refactors the test to keep the common part equal.\nFor the differences, locally define the expected test target\nfor the FFA_FEATURES call.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I96f18487c80d789cf4e10ceee0591786708bce51\n" }, { "commit": "3202b1a27c5316292c893be1af3cd9cee1bc8738", "tree": "2c201ceff7581f93a28f39746bb91dde9d5d472f", "parents": [ "5e44ee68b6cdce5a40137dac562906c7e43cde41", "e533478ae2a0374e25d1eaff68eb5381a33ed345" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri May 10 07:54:23 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 10 07:54:23 2024 +0200" }, "message": "Merge \"feat(smc): add test for pmf version check\"" }, { "commit": "ffdfafbd49bbe0c6212c00ca4fd910574cac538d", "tree": "d09165edc985faeeaa800aca2570d9a03843fa26", "parents": [ "807822927033f07e272eae2222f78a878a23bbb0" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Apr 09 12:07:11 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(ff-a): FFA_MSG_SEND2 helper with sender ID\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Idaf866a342f2127172b46f7a7a44a599723db7cf\n" }, { "commit": "58cc4dad0451ab4669072c654dbc0603932baa94", "tree": "71869e4f65f6e4f504a56a844205222a80e482ed", "parents": [ "907fcef5cc7b2c09679f7ebf99fd92426c544efc" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 05 14:17:35 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(cactus): ability to send indirect messages\n\nAdd cactus test command for it to send indirect message\nvia FFA_MSG_SEND2 to a designated target FF-A endpoint.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: If519c19dd0ff86252fdd1d749baa2308bf64b936\n" }, { "commit": "907fcef5cc7b2c09679f7ebf99fd92426c544efc", "tree": "f33cc7fda4a2cd7fb4992e2956062ee474624691", "parents": [ "c6b92d5e73a19a9aeeb28d7ac8103cd2dc5adca8" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 08 17:32:58 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(indirect message): send and receive messages\n\nAdded helpers to receive and send indirect messages, respectively:\n- `receive_indirect_message`;\n- `send_indirect_message`;\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I396870f15172f841167627b14c18b1504e0efbee\n" }, { "commit": "c6b92d5e73a19a9aeeb28d7ac8103cd2dc5adca8", "tree": "ee1d3de9d246f6d5abc62170a7b01b656cad09aa", "parents": [ "779fba660d61c8d95adbc66cb5b7086d681e1eaf" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 05 14:16:00 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(ff-a): define framework notification helpers\n\nDefined the helpers to process framework notifiactions.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I979162363898b4f9bf1a3d57327078364883b896\n" }, { "commit": "779fba660d61c8d95adbc66cb5b7086d681e1eaf", "tree": "09298958223dd797fff83fb116e1c76557001137", "parents": [ "2921fba58bd4535f8e944620273ade51f69db63f" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 05 14:14:40 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:34 2024 +0100" }, "message": "feat(ff-a): add helpers for indirect message\n\nAdd the header structures for the rxtx buffers, other\nhelper macros, and the FFA_MSG_SEND2 ABI caller.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ie5c735aa0b33dbf0288b6494362b6e7dc84c6db7\n" }, { "commit": "e533478ae2a0374e25d1eaff68eb5381a33ed345", "tree": "610a7160c96b43e96c00fafcbf9f4676ad6c222c", "parents": [ "dfc4d7f46fb95441443066f60d1b855f7ef9c364" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed May 08 20:33:20 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed May 08 20:33:20 2024 -0500" }, "message": "feat(smc): add test for pmf version check\n\nPMF is moved under vendor specific EL3 range, part of this\nwe have introduced each sub-service have an version scheme[1].\n\nAdd a simple test to check if the sub-service version\nis probed.\n\n[1]:\nhttps://trustedfirmware-a.readthedocs.io/en/latest/components/ven-el3-service.html\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: I885cd1378a8025371172e5cd82fdd111d6832619\n" }, { "commit": "067daca6eea89d0ac95fcedc12750521ea09b952", "tree": "3372bfa2adc9c32b54417f547de0a78cb141909e", "parents": [ "dfc4d7f46fb95441443066f60d1b855f7ef9c364" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 08 17:31:54 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 07 15:46:16 2024 +0100" }, "message": "feat(ff-a): add helper FFA_RX_RELEASE with ID\n\nAdd the helper `ffa_rx_release_with_id` for TFTF\nto mimic the releasing of RX buffer from a hypervisor.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I1edcc1568fd84af72454f3b755ccf16eca321a17\n" }, { "commit": "dd8025c73f9c2f73c663629b30508b96f04194e1", "tree": "d476fff8d3bc87d11f8b132b4b55698638792f4a", "parents": [ "951d5fbe6641ed58747fed557e462dd3f3508ce4" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Mar 14 09:47:24 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Apr 24 13:29:10 2024 -0500" }, "message": "feat(smc): add test for vendor-specific service\n\nAdd test to check vendor-specific el3 service calls.\n\nChange-Id: I981d1cacec8690f57e51a5f05d51b6e437d1eb6a\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "f33112d50b18143421d3f3eac02a615f821ec284", "tree": "eacae716d87f7883d56bbdf8b533a8c068a0c00a", "parents": [ "3eb25fb886ece03d872eaba4bbd31cf80edda6af" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Feb 26 09:44:36 2024 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Apr 24 13:29:10 2024 -0500" }, "message": "refactor: make debugfs and pmf as vendor el3 services\n\nMove Debugfs and PMF support to vendor-specific el3 space.\nSMCCC 1.5 introduces vendor-specific el3 space.\n\nRef: https://developer.arm.com/docs/den0028/latest\n\nChange-Id: Ie6679dbb2ca2434ebd4fc19c2cc21cf5a84f97ab\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "3eb25fb886ece03d872eaba4bbd31cf80edda6af", "tree": "5de8b9d866ae31762bec44e6d2264ed47bc59d1e", "parents": [ "bbd609b99b23da41b997415980065be5849aeea9", "f2bb5d0f502955caf58192c6d9c9e0a051817b5d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 23 14:48:41 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Apr 23 14:48:41 2024 +0200" }, "message": "Merge \"test(ff-a): FFA_FEATURES returns max RXTX buffer size\"" }, { "commit": "bff9b3ca375d40753a3212dbf178bcdfc7784841", "tree": "d46e017d6c35e04582c340fbd1c433680fbc22c9", "parents": [ "e3e570653471af3506846f06b5fe0421970adce4" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 18 16:08:35 2024 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Fri Apr 12 17:24:23 2024 +0100" }, "message": "test(spm): tests for RXTX_MAP/RXTX_UNMAP\n\nTests to check that RXTX_MAP and RXTX_UNMAP properly unmap/map the RX\nand TX pages from the NWd stage 2 page tables.\nSpecifically:\n* RXTX_MAP should fail when using secure memory\n* RXTX_MAP should fail when using non-secure memory outside the regions\n specified in SPMC nodes\n* Memory sharing functions (lend, share, donate) should fail when using\n memory that has been mapped by RXTX_MAP\n* RXTX_UNMAP should fail when using different VM IDs\n* Forwarded RXTX_MAP should succeed when the region is not mapped\n* Two consecutive forwarded RXTX_MAPs should succeed when the regions\n don\u0027t overlap and the endpoint IDs are different\n* Forwarded RXTX_MAP should fail when the region is already mapped\n* Memory sharing functions (lend, share, donate) should fail when using\n memory that has been mapped by forwarded RXTX_MAP\n\nChange-Id: I006681ab54f5ff602e862ae09438d0d174c8d0b0\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "e3e570653471af3506846f06b5fe0421970adce4", "tree": "f1a6c8a23f0a06e442d058b2ad22034f6e0febb5", "parents": [ "52f0b0ac70de3701d642cd59044aa70ffa342e40" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 18 14:28:36 2024 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Fri Apr 12 17:16:00 2024 +0100" }, "message": "feat(ffa-svc): add `ffa_func_name` and `ffa_error_name`\n\nAdds helper functions for getting string representations of function\nidentifiers and error codes. This makes debug logs more readable than\nprinting the integer value.\n\nChange-Id: I9e74c197686dc08e0c71886f641c60829587bad6\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "b1b37926917b265ef8a3f6caf59b6a20fe8b636c", "tree": "41baf3e3f7d6ab325f673bb5bababe955713663f", "parents": [ "e3ee6e0a40b73baffd26563adb9cf49b040cbc30" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Sat Jan 13 21:49:04 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Mar 29 09:22:09 2024 +0100" }, "message": "test(realm): add test for enabling pmu with multiple rec\n\nTest creates realm with less number of pmu counters than available\nTest verifies that only programmed num of pmu counters are available in realm\n\nChange-Id: I479dd8949950357b9814576b1b6cef142d21c75f\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "f2bb5d0f502955caf58192c6d9c9e0a051817b5d", "tree": "578f200539be531f599a6d3989cc5894f2280f6f", "parents": [ "90d61cd1e36634597a71b86fcb9701b94741a553" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Feb 13 17:23:17 2024 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Mar 27 12:48:46 2024 +0000" }, "message": "test(ff-a): FFA_FEATURES returns max RXTX buffer size\n\nAdd testcase to check that a call to `FFA_FEATURES` with\n`FFA_RXTX_MAP_SMC64` returns a parameter explaining the maximum and\nminimum buffer size on v1.2 or greater.\n\nChange-Id: I03efc89655daf9f7c2eb9cf35d26c5a68690036a\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "f733a781ab7fdcb4e775a74005b2f23a313094ef", "tree": "3de60d072408b473bfdbb0ca912eccfafa6be9a9", "parents": [ "733f88170011df029477656c66b6959fdb91cf35" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Jan 03 22:33:10 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Mar 26 15:34:05 2024 +0100" }, "message": "test(realm) : add tests for PAS transitions\n\nadd tests for HIPAS and RIPAS changes at a\nProtected IPA which can occur when the\nRealm state is New and Active\n\nChange-Id: I0ad13d697e8b69e71e58197878d1d58a2f6ebff7\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "7bb1c84eca3a7dc46051b75b6b1cf13046b88c92", "tree": "1be17aeca48b145e8814b08be48637483268afe7", "parents": [ "44115698f07b73ce83fdcce4e26aafe701c49b1c" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Feb 15 14:14:59 2024 -0600" }, "committer": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Mar 14 16:30:45 2024 -0500" }, "message": "refactor(errata_abi): update the cpu structs for errata ABI\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I4650a88003db2ded9277b35c7fc521026fe4a5d7\n" }, { "commit": "2a5abadb8e841eedeaa1ff78b6f0da5f957b2ab8", "tree": "42755e1512d2cf0d6abf3f0baa01a289d2a69e46", "parents": [ "21a30ed1ae35a8b32d23e96cdc143702a27bda90" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Jan 17 13:48:44 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Feb 14 12:51:31 2024 +0100" }, "message": "test(realm): add test for FEAT_DIT\n\nAdd testcase to enable FEAT_DIT in realm.\nTest if DIT Bit is preserved across context switch RL/NS.\n\nChange-Id: I26cbaaf669b53ecba14a451955b6f847c45e0575\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "b027f5706308502152b5aade0ad509ba27370c42", "tree": "3a05dab054068d29e8b242f8f82daa4a864468e9", "parents": [ "fd35f0a4d6125bb1fa69a671a6d2d42628229609" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Jan 02 22:00:29 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Feb 08 12:14:31 2024 +0100" }, "message": "test(realm): add testcase for Synchronous external aborts\n\nAdd testcase to cause instruction or data abort in Realm by\naccessing addr with\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dEMPTY\n* HIPAS\u003dASSIGNED and RIPAS\u003dEMPTY\n* Unprotected IPA\n* Host injected SEA after Data abort\n\nChange-Id: I6be546c042b4983670fb7c27fca74649c68787be\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "fd35f0a4d6125bb1fa69a671a6d2d42628229609", "tree": "bf1c92d316299405b3751e62e904616f2f81e0a3", "parents": [ "69c9f363cb172788ef7e8d3fd711f56ddf481bf8", "e742ba89effefc4298fb4e406e0515a83db9c7e0" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Feb 07 17:22:13 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 07 17:22:13 2024 +0100" }, "message": "Merge changes from topic \"ja/spm_rme\"\n\n* changes:\n refactor: cactus to handle expect exception\n test(memory share): memory contents checks\n refactor(spm): clean-up after failed memory share\n test(spm): lend/donate realm memory\n test(spm): use all constituents of memory share\n test(spm): validate GPC with memory sharing\n test(memory share): leverage rme for lend/donate\n" }, { "commit": "e742ba89effefc4298fb4e406e0515a83db9c7e0", "tree": "c3d9688ea07be06ac244e757faebdb1c76bb329b", "parents": [ "c2e32ed038aa54ae9c5d35362dc3c2fffc55fdb3" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 11 10:38:29 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Feb 06 19:27:38 2024 +0000" }, "message": "refactor: cactus to handle expect exception\n\nIn the test \u0027rl_memory_cannot_be_accessed_in_s\u0027, tftf\nshares memory to the SP that it changed to realm PAS.\n\nThe access from the SP should result in an exception.\nCactus receives an indication it should expect an\nexception on memory access via the arguments of the\n\u0027cactus_mem_send_cmd\u0027 request. This is used to avoid\nthe reads to check memory, which could return in an error\nresponse, which would make the test falsely fail.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ie220d4bab04c052a73e8b04c8667c9973b95a9e0\n" }, { "commit": "e68494eb130e2c8021ca4af626a9cb1df8d67dbd", "tree": "894c262fc0aa78dcbe3b28cc6b731df068a404b6", "parents": [ "daa6c795847b78692f522fd96f783a6d419aaec2" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Nov 06 11:04:57 2023 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 06 10:45:44 2024 +0100" }, "message": "test(realm): add testcase for REC exit due to Data/Instr abort\n\nAdd testcase to cause instruction or data abort in Realm by\naccessing addr with\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dDESTROYED\n* HIPAS\u003dASSIGNED and RIPAS\u003dDESTROYED\n* HIPAS\u003dUNASSIGNED and RIPAS\u003dRAM\nVerify rec exit due to abort\n\nChange-Id: Ic04c0ddaf1b18ec0cfd71c28753c4ed7298302da\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "d655d58c0c4791c10ad811a5f8bd66e0c1a8d989", "tree": "f23aa14968bf1100c987e8ebe351f96356acb1c9", "parents": [ "0945e23153c06ed196756ac094c81ab8627d9a95" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jan 16 14:45:39 2024 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jan 31 09:42:42 2024 -0600" }, "message": "feat(cactus): add support for fake RAS handler command\n\nThis command mimics handling a RAS error delegated by an EL3 logical\nsecure partition through a direct message.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I45e728880de1ee594e980667872e663309c83c22\n" }, { "commit": "f325331b86dd3f2ea31bbb20690b36538a8ead87", "tree": "4237de4b195da4aab89edcacf6ed2f6667af2f82", "parents": [ "f0b3bd6c706da491eb589e0e8cbd3bc16a77113a" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 18 17:05:26 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jan 23 14:50:07 2024 +0000" }, "message": "fix(memory share): arguments used in retrieve tests\n\nFix a few small arguments that are used in the hypervisor\nretrieve request tests.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I9f6d2d10178331ffea6387a00c05002c07346bc6\n" }, { "commit": "f0b3bd6c706da491eb589e0e8cbd3bc16a77113a", "tree": "48383ded203667672828368c981e54bb049d9b1f", "parents": [ "5517c09b42a412f29aa8a146fa6ec5b5bd33a2af" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jan 18 17:01:37 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Jan 23 14:50:07 2024 +0000" }, "message": "feat(memory share): add helper for getting receivers\n\nAdd helper for \u0027ffa_memory_region_get_receiver\u0027.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Id30a3cf58689ab8d6d23e851b6581fad53f1f6e9\n" }, { "commit": "a24f23a476578361aecd8a568191cc907c24240e", "tree": "b38806323ed4a33d91d27b0f18d563c1635f8f7c", "parents": [ "899dcedd9938549a19eb1a2ed474544c27f59520" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed Nov 15 18:23:40 2023 +0000" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Mon Jan 22 18:49:54 2024 +0000" }, "message": "feat(ff-a): add impdef field to ffa_memory_access\n\nAdd impdef field to the endpoint memory access descriptor as\nintroduced by FF-A v1.2.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ieb2808a5b4a8773cb4729c5aa10a6a0223ed8039\n" }, { "commit": "ea94738603d09be1399337f0976f89f951c35e6a", "tree": "41b0b558a54f4e96a42ef4989d0910ea1f773fa1", "parents": [ "ec2eda8cf0faba3097570400ee4d07b736053efa", "028712b494ac24627f88e355af2864a54d81ba29" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jan 16 17:18:58 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 16 17:18:58 2024 +0100" }, "message": "Merge changes from topic \"km/test_hypervisor_retrieve_request\"\n\n* changes:\n test(memory share): fragmented hypervisor retrieve request\n feat(memory share): support sending fragmented messages.\n test(memory share): multiple receiver hypervisor retrieve request\n feat(memory share): send multiple receiver regions\n test(memory share): hypervisor retrieve request\n refactor(spm): `ffa_memory_access` constructors\n refactor(ffa_helpers): use bitfields for memory access bitmaps\n" }, { "commit": "0d4f5ffaeb91f57e37819d69092bdf38aeac13d0", "tree": "9336eb6404b034baf8b9a9ed76aa88744078f25f", "parents": [ "1f48892a72dc34dbdfc1d27ae4708a243150eef3" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Fri Oct 13 20:03:16 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 11 16:07:24 2024 +0000" }, "message": "feat(memory share): support sending fragmented messages.\n\nUpdates `memory_init_and_send` to allow sending memory share messages\nacross multiple fragments.\nTests for this functionality will be added in the next commit.\n\nChange-Id: I6a47735415a8fed1d15322499f1d08cc3e1fd6a2\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "1331a8c0e861331e7ea9a140a2adea398988faaa", "tree": "10fac1901bd460455d6ffa877666a8d5afff55f7", "parents": [ "3d879b8d66caf9d1f2b4e2a4c5333987bb74e4b8" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Sep 14 16:25:15 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 11 14:08:37 2024 +0000" }, "message": "feat(memory share): send multiple receiver regions\n\nUpdates `memory_init_and_send` to allow passing more than one receiver.\nTests for this functionality will be added in the next commit.\n\nChange-Id: I51d92d74f64bfebfa3d49ff6d5066050087b44ef\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "3d879b8d66caf9d1f2b4e2a4c5333987bb74e4b8", "tree": "f2e37b988b49f36f01acf13471cacc6b7c33e8a2", "parents": [ "367ff54c829a41e5b223683805e2cf80f8882201" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Fri Jun 16 10:32:08 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jan 11 14:08:36 2024 +0000" }, "message": "test(memory share): hypervisor retrieve request\n\nChecks that the hypervisor retrieve request from section 17.4.3 of FF-A\nv1.2 REL0 is supported.\n\nSpecifically, the tests:\n1. Sends a FFA_MEM_SHARE/FFA_MEM_LEND/FFA_MEM_DONATE message from the\n tftf target to the SPMC.\n2. Sends a hypervisor retrieve request from the tftf target to the SPMC.\n3. Verify the contents of the FFA_MEM_RETRIEVE_RESP message against the\n previously sent message.\n4. Invoke reclaim interface for SPMC to free memory owned by the handle.\n\nChange-Id: If27d8d5b515c5e468977ed4f5f4ddeb86e44c5df\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "e71ec9c4923590f5732b6d5e647ea1f3cc895d36", "tree": "0475fb8e7e1a441df6319b60a215bc797655f078", "parents": [ "be4850c9345512f37da32c520367fc2a775303e7" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Feb 28 18:57:26 2022 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 11 11:36:11 2024 +0100" }, "message": "refactor(smmu): secure side DMA rand and memcpy\n\nAdd operation, source and size parameters to the cactus command\ninitiating an operation to the DMA test engine through the SMMU.\nAdd RAND48 operation support to the DMA test engine.\nRefactor to a common run_testengine helper exercised by MEMCPY\nand RAND48 SMMU operations.\nCactus SP dispatches either one of the operation based on the\noperation id passed from TFTF.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I2ca7c303e8fef6baf99fe4b64b33102546b9ff30\n" }, { "commit": "367ff54c829a41e5b223683805e2cf80f8882201", "tree": "3e3245f6b10fe26ca64dcafd8d67705705c299e0", "parents": [ "92aa770261f62af56268659db38fed9465953106" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Nov 01 15:05:37 2023 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Jan 09 12:33:42 2024 +0000" }, "message": "refactor(spm): `ffa_memory_access` constructors\n\nAdd `ffa_memory_access_init_permissions` and\n`ffa_memory_access_init_permissions_from_mem_func` helpers.\n\nChange-Id: I9a5bb09e7f230a65decff7f58a0c188aff3e7449\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "92aa770261f62af56268659db38fed9465953106", "tree": "db987ff7f7c9b03bbc1a5db68faffc0f32766a5d", "parents": [ "be4850c9345512f37da32c520367fc2a775303e7" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Oct 11 18:48:01 2023 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Jan 09 12:26:42 2024 +0000" }, "message": "refactor(ffa_helpers): use bitfields for memory access bitmaps\n\nInstead of doing the bit-manipulation manually, these types can be\ndeclared as structs where the fields are given explicit bitwidths. The\ncompiler will generate the appropriate bit-manipulation automatically.\n\nChange-Id: I0d4754466b1e70d1b36cb039bfe9e7701ebbd60f\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "affbae8163ad25534cfe4dbc4bcda5a3372d0062", "tree": "b75a233b78259620329179a4f6e3d8e3a3b18d79", "parents": [ "ec482824eba8020f9b36b6b7a563ac3c84064c23" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Aug 22 12:51:11 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 05 15:35:50 2024 +0000" }, "message": "test(rmm): add testcase for multiple rec on multiple cpu\n\nTest creates and enter 8 recs on different CPUs.\nExercises CPU_ON, CPU_OFF and PSCI_AFFINITY_INFO\nfrom realm.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Iecc58ea79bfde28f307d1df99680d707e57a1d80\n" }, { "commit": "fef8621d2d5ce3ce67a4ba3013292b7382b92355", "tree": "3704d2a1a84205cedf36191c7f2ebb648ecce4a2", "parents": [ "bb772193864856ce5d0da9b3534316b7bc4fc3d3" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 17 12:15:38 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Dec 19 15:09:04 2023 +0200" }, "message": "test(realm): testcase for RMI_RTT_SET_RIPAS reject\n\nAdd testcase for realm to call rsi_ipa_state_set,\nhost will reject and call RMI_RTT_SET_RIPAS\nre-enter rec with response RSI_REJECT\n\nChange-Id: I6809fdabba580b23269aedc2aa844b15fbcce981\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "bb772193864856ce5d0da9b3534316b7bc4fc3d3", "tree": "c2ecde3c3eaea03acb70d6fa5166e178591a1fd2", "parents": [ "d5b30b42f36d9fc80d0a26c238129a2488f6a068" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 09 16:08:28 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Dec 19 15:08:13 2023 +0200" }, "message": "feat(realm): add support for RSI_IPA_STATE_GET/SET\n\nAdd support for realm API rsi_ipa_state_set, rsi_ipa_state_get\nAdd testcase for following\n* Realm calls rsi_ipa_state_set to change RIPAS\u003dRAM,\n* Host accepts and call RMI_RTT_SET_RIPAS\n* Realm verifies RIPAS change was successful\n\nChange-Id: I4da6c7d25faa62afde1d0f682510bac6c8445821\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "334217c012558149603f8909159a819ecaf71403", "tree": "7fa45077f184a0cfa9eb12a771e590ad046e2d92", "parents": [ "a276b20c477aab869c74f687484d480c4a289f0a" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 18 10:28:53 2023 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 18 12:53:06 2023 +0100" }, "message": "test(realm): remove unwanted arg from realm API\n\nRemove unwanted arg plat_mem_pool_size\nfrom host_create_realm_payload and\nhost_create_activate_realm_payload API\n\nChange-Id: Id92d77d2ed8944c0e038cb62459247f0d17e516c\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "941c99a298b8b09b94299d958fad1b74ef196ad9", "tree": "7b4a2916a30b148cc5ca2d52e33c18f1c252b174", "parents": [ "944016b3e7cd2f07e7e3e0db983fd08ba5b7553a" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Dec 15 02:10:55 2023 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Dec 15 19:28:06 2023 +0100" }, "message": "test(realm): add new api to create and activate realm\n\n* Add new API to create realm payload and activate realm.\n host_create_activate_realm_payload().\n* Also add API to create realm without activate.\n host_create_realm_payload(). Host will need to call\n host_realm_activate() separately prior to entering.\n\nChange-Id: I67c330c2672a02438cbb9a99c6c1741d3eda3cc3\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "e59296214e26da925521d927892544bcde009316", "tree": "df11d07fbfaefe40d96c60bc7a2971c1afccf954", "parents": [ "0386212b59003a4969acf26683f9d93774fa1031" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Nov 21 10:50:22 2023 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Dec 15 19:20:54 2023 +0100" }, "message": "test(realm): add support for multiple realm\n\nAdd support for creating multiple realm payloads\n* Layout change to reserve memory for two realm pools.\n* Change offset of shared memory region between host and realm.\n* Change API to get/set shared memory region for each realm\n\nChange-Id: If0d7d2e2697052387c2ddcc729ec3872fd5dd409\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "ec06083913d491f2d37a133155d172af2f495a9f", "tree": "2287df31b878166ec0f4fe850b4087c1277f8203", "parents": [ "43a50c3b4c1d33be07cf77fb674f7060dc93f601" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Nov 21 00:44:47 2023 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Dec 11 13:38:30 2023 +0200" }, "message": "test(realm): change realm create and execute api\n\nChange realm creation and execution API\nin preparation for multiple realm support.\n* API host_create_realm_payload needs pointer to\n realm structure.\n* API initializes structure on success.\n* API host_enter_realm_execute needs pointer to initialized\n realm structure.\n* modified sleep testcase to create/destroy realm iteratively.\n\nChange-Id: I196166e30aa7e77b90603e270ca250e2390ba066\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "12cee415ae010d0258f238b1a51c1af117b2e0e5", "tree": "bde8da4fe898eeafcae708688b0dc2bcb390e148", "parents": [ "fa605fe479ef69ce71c4b065134c4d6137b715d0" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Nov 20 11:51:23 2023 +0000" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Dec 04 19:01:44 2023 +0000" }, "message": "fix(rme): return value of host_enter_realm_execute call\n\nA failing realm command might be reported as pass if the exit reason\nis RMI_EXIT_HOST_CALL. For RMI_EXIT_HOST_CALL exit reason, return true\nonly when host_call_result is TEST_RESULT_SUCCESS.\n\nThis change also fixes the expected RmiRecExit reason for PMU tests.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I37789a2c2941eec83fe1ebc54a0107192fd2fc11\n" }, { "commit": "fa605fe479ef69ce71c4b065134c4d6137b715d0", "tree": "4c7eb90de20d5ff165fab27ca4c97d599d7ab31c", "parents": [ "53ff0ad786ce0a6218dc3c275b5b50f2e246b027", "75b4221efda572f56a44b94cad993ed97d11ea3d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Dec 04 18:17:38 2023 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Dec 04 18:17:38 2023 +0100" }, "message": "Merge changes from topic \"rmm_sme\"\n\n* changes:\n test(rme): use sve hint bit feature\n feat(smc): add SMCCCv1.3 sve hint bit support in tftf framework\n fix(cactus): replace tftf_smc with ffa_service_call\n" }, { "commit": "d0eff2aa0acf17013d675daca17524d340ee3fae", "tree": "dcd4e83b79629e954d6b40896eac541b765d25b1", "parents": [ "42b99719d5dde58bdde07712bcb70a20d87f9067" ], "author": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Fri Sep 29 18:21:51 2023 -0400" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Thu Nov 30 17:34:52 2023 +0100" }, "message": "feat(ff-a): update FF-A version to v1.2\n\nBump the required FF-A version in framework and manifests to v1.2 as\nupstream feature development goes.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Id00cdbd94466570a962d9c6956fda793758ee5d9\n" }, { "commit": "417edcad3eb332eca5d7ed70de51cac489a2dca4", "tree": "520dcd978d3d12003560fd56a66e1c0117521514", "parents": [ "bbf08c50aca569e517a52d2216c42e7244769a5e" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Sep 05 17:44:24 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Nov 30 16:27:24 2023 +0000" }, "message": "feat(smc): add SMCCCv1.3 sve hint bit support in tftf framework\n\nTFTF smc library uses SVE field in trap register to represent SVE\nhint flag.\n\nTestcase has to explicitly set this bit using the helper routine\ntftf_smc_set_sve_hint(). When set to true, denotes absence of SVE\nspecific live state on the CPU that implements SVE. Once set to true,\nSVE will be disabled in trap register and any SMC made using tftf_smc()\nwill set FUNCID_SVE_HINT in the SMC function ID.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I13055fe4102cc4e35af1d7091e88327a21778835\n" }, { "commit": "1768e59c3a6ac8d727ac012719b4b09947c8400d", "tree": "cc6ad04618bb60fb861bf3e7e4da2538c1a5cf42", "parents": [ "5b68e20b2a0c9ac70caa2dd833d48f5fd49aa581" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue May 23 13:28:38 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Oct 31 13:56:54 2023 +0000" }, "message": "feat(rme): add tests to check NS SME ID registers and configurations\n\nThese tests checks the functionality of RMM for NS SME support.\n- Create Realm and test ID registers specific to SME\n- Check if Realm gets undefined abort when it accesses SME\n- Check whether RMM preserves NS SMCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Ia8ffd0188297a74c095dbadfb389add50c548e10\n" }, { "commit": "40de8ec10f4d9925c24d2b9dd22822e0c8fd4224", "tree": "30347a76b3f2429f8ab3d0f124526d860ee77503", "parents": [ "6bb95105b289a4d9015d74af7cb7254455b2344e" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Oct 12 21:45:12 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "feat(rmm-eac5): update RSI_VERSION, RMI_VERSION\n\nThis patch adds necessary support for RMI_VERSION\nand RSI_VERSION commands.\nMacro SMC_RSI_ABI_VERSION renamed to SMC_RSI_VERSION.\n\nNote.\nThis patch sets both RSI and RMI version numbers to\n1.0 as per RMM Specification 1.0-eac5.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If4eb14d93f657388e2fe64ceefee002403cc4ae8\n" }, { "commit": "6bb95105b289a4d9015d74af7cb7254455b2344e", "tree": "faf71d64251c88b5aa5caa5512a76eff62601851", "parents": [ "24597d136cc199d8399be2291fda2efb0a652741" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 02 13:21:37 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "feat(rmm) : add api for rec force exit\n\nadd api to force exit a rec\nadded testcase for force exit rec\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I56c70234e236c7d3615237d11c773bdb970012e3\n" }, { "commit": "24597d136cc199d8399be2291fda2efb0a652741", "tree": "686e70f45e398155a42fc811e6abad9eb2a84254", "parents": [ "a29e811d596794b5e135904be9033e9a1662507e" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 02 10:40:19 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 31 02:57:53 2023 +0000" }, "message": "test(rmm-eac4): add testcase for CPU_ON denied\n\n- Testcase creates multiple rec\n- Host receives CPU_ON request from realm\n- Host calls PSCI_CCMPLETE with denied status\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie89b7a3b9603916275913a273751210350075e96\n" }, { "commit": "f369717f93ee8d7e2c12460e71d335bc702e37b4", "tree": "ff959de9f2e05c711dae73bedf2e5b8a34d56f2b", "parents": [ "6e587999a0b2f3055d14e08b7bbcfa5735db9891" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Sep 04 15:04:46 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 15:07:15 2023 +0100" }, "message": "test(rme): check various SIMD state preserved across NS/RL switch\n\nThie test case verifies whether various SIMD related registers like\nQ[0-31], FPCR, FPSR, Z[0-31], P[0-15], FFR are preserved by RMM during\nworld switch between NS world and Realm world.\n\nRandomly verify FPU registers or SVE registers if the system supports\nSVE. Within SVE, randomly configure SVE vector length.\n\nThis testcase runs on below configs:\n* with SVE\n* without SVE\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I3fc755f75bdcdc8c24af0440d8a5f094beafca73\n" }, { "commit": "035899729133080ffff3ed691ba65664c34f75ca", "tree": "02a0b07c127329297d5c28e0683352357c8c0d8a", "parents": [ "73949a20b61def813b3265c2a6a330656bd001af" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Aug 30 11:04:51 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:15:59 2023 +0100" }, "message": "fix(sve): represent sve Z0-31 registers as array of bytes\n\nCurrently each Z register is type defined as sve_vector_t but the helper\nroutine to write or read Z registers works based on current vector\nlength.\n\nIf test case defines \u0027sve_vector_t zregs[32]\u0027 and reads all Z registers\nusing sve_read_vector_regs() then zregs[n] might not corresponds to Zn\nregister unless the vector length is set to max value.\n\nThis patch also renames sve_vector_length_get() to sve_rdvl_1()\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I42955f8009bdd7f40d74c5a8d21d7c16ce6d761e\n" }, { "commit": "73949a20b61def813b3265c2a6a330656bd001af", "tree": "ab41f5043a87d13fcccbc8bf0473bc2817fa13a4", "parents": [ "cbfec24f12c205a8c827604864e2c51f7d419b33" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon Jun 05 12:01:05 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Oct 25 14:15:55 2023 +0100" }, "message": "test(rme): check if non SVE realm gets undefined abort\n\nThis test checks whether a non SVE realm receives undefined abort upon\naccessing SVE register state or instructions.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I2785488b1344cc4d59dde75e38d9e0d6f856af61\n" }, { "commit": "52b5f02cf50a79efdaf7bd6682e40a069dec04b7", "tree": "62b0019e05420486a64cfd7507fb4f2437fd4735", "parents": [ "699cd4feef98deb1e1d3bc95adc42a16da40052d" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Oct 12 22:02:29 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(rmm) : use shared data buf to pass arg to rec\n\nHost can pass arguments to rec using\nper rec shared buffer.\n\nChange-Id: Ic34acf6253031b3b5f184669084f15460b0fc5fd\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "8ce3053050bc37f5cfccadefd575a597ac86dd95", "tree": "bd9c9d8e6eeba40a81702f88e8cb3bcbb44b9abf", "parents": [ "550e3e88891507cd514fbd8f27d6ba6b8c5a3162" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 16 15:58:38 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(realm): add host call to flush realm prints\n\nadd new host call to push out realm print buffer\nbuffer is flushed after every print statement\n\nChange-Id: I6efa92a7c75ab7df4615a432802426de39d0032c\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "550e3e88891507cd514fbd8f27d6ba6b8c5a3162", "tree": "81485909f1376913447c3480d640f9717bb61de0", "parents": [ "cdf525212326f8b453f22122dddc9d8bf0725981" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Aug 16 13:20:11 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Oct 23 19:34:54 2023 +0200" }, "message": "feat(rmm): add support for multiple rec and cpu\n\nChanges to support creating and\nexecuting multiple rec on multiple cpus.\nAdded per REC shared buffer between Host and Rec.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ib6dbd814ee9f68df4a53f9cfdc8b7f9c905c35fe\n" }, { "commit": "cdf525212326f8b453f22122dddc9d8bf0725981", "tree": "cb2921b3cfa538802547572d0e8ea360bc0eb309", "parents": [ "9b2f7db4f52d6f144641761b2d2b01644b2b6684", "9e267a0f899d699cb840572eb8fc12936ac49d03" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 20 18:49:36 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 20 18:49:36 2023 +0200" }, "message": "Merge \"test: exercise secure espi interrupt handling\"" }, { "commit": "9e267a0f899d699cb840572eb8fc12936ac49d03", "tree": "869431e9ca81b7a20027416704453766d7c10f56", "parents": [ "2f13adbc1ac240bdee4c901cbd0e09119f17fce4" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 11 21:25:26 2022 -0700" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 13 12:04:15 2023 -0500" }, "message": "test: exercise secure espi interrupt handling\n\nHafnium/SPMC added support for enabling interrupts in the extended SPI\nrange. With the help of an SiP SMC call that can pend an interrupt,\nthis patch adds a test to trigger an espi interrupt when cactus is\nrunning and ensure it is handled.\n\nAdditionally, a dummy device region node representing a fake\nperipheral has been added to the Cactus SP manifest. It is used to\nspecify properties of the interrupt in the extended SPI range used\nfor the above test scenario.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ief932c40e3abd33d619f2b144e61cae449147b27\n" }, { "commit": "5e07e7eb18d5b21e1e356b1d040fc9008b8ad221", "tree": "2340fad9f8c4ec95fc92dd649b1896f70241ffba", "parents": [ "d13d760570e9d0f640e8bd83bcfbc21240949156" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 14:36:09 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:08:49 2023 +0100" }, "message": "feat(cactus): use security state attribute\n\nCactus uses security attribute from memory transaction\ndescriptor in the shared memory related tests.\n\nChange-Id: I7c4f3ef2c72e36236d23e5a061e27a2ea60fa2d6\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "d13d760570e9d0f640e8bd83bcfbc21240949156", "tree": "a0b70191908599e7242033b0629d97c14c6ce5b6", "parents": [ "7043e2a82e3b271552744b46fd180c4bc011ccc3" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri May 05 14:19:03 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Oct 13 14:08:49 2023 +0100" }, "message": "feat(ff-a): define memory security state attribute\n\nFF-A v1.1rel0 defines the security state attribute for the\nmemory transaction descriptor. Add respective definition\nto ffa_helpers.h.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Iefb510f5272587bc9faa96731af0159e2379576b\n" }, { "commit": "6e5c99643b199e064f1e8090d963671965ced1d7", "tree": "c5079b4d7de61ed810e5241021b5005d35990ba7", "parents": [ "92b99ee435ebafa5e503b19dce753079ad35218d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Oct 06 16:38:13 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Oct 10 14:31:18 2023 +0100" }, "message": "fix(rme): append realm.bin at end of tftf.bin\n\nCurrently realm.bin is appended to tftf.bin at offset of 10 MB.\nThis patch removes this dependency by reserving empty sections\nfor realm image and dependencies, in tftf binary after\nall loadable sections (end of binary),\nand append realm.bin at end of tftf.bin later in build process.\n\nThe patch removes the need for TFTF to map memory corresponding\nto Realm payload dynamically at runtime.\n\nChange-Id: Iead2dc62ff2965cf7bb03e61c93e76df218da973\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "afffe3a45076fa46a8cd73b0923e06874c8ab135", "tree": "d751b1c0856b93b8e7730c825c614c64b444bad4", "parents": [ "6d8721db1753e0b9fc4252308186d5eb152252a8" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Sep 22 17:14:52 2023 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Sep 28 15:15:38 2023 +0100" }, "message": "fix(spm): instruction permissions on memory sharing\n\n- FFA_MEM_SHARE the instruction access to be used shall be NX,\nhowever both sender and the borrower should leave it not specified.\n- FFA_MEM_LEND/FFA_MEM_DONATE the lender must specify the instruction\npermissions it wishes to receive on the retrieve request.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I0c6e49c30cbbca513644b592695f853bbdf1994b\n" }, { "commit": "4550b49db8ddf98e4445fdd121d3e2bed466b034", "tree": "040deae47b58fde8636d6e6b2e0d350eaaa8545f", "parents": [ "35b0fa999146f9b1fe12abb237f9eecec42030c8" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Jul 14 12:07:56 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:50:15 2023 +0100" }, "message": "fix(rme): remove RIPAS_UNDEFINED definition\n\nThis patch removes RIPAS_UNDEFINED definition\nand matches RMM-TF patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21987\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I26d6c5e6f7c1053d1b2a7688118e6175985be029\n" }, { "commit": "35b0fa999146f9b1fe12abb237f9eecec42030c8", "tree": "39051ad40d5b1f3415349f9c8a5998c7525380e9", "parents": [ "4067f8610d0d9e89bac0499f09bcbd89d904ff36" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Jul 04 16:24:14 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:50:00 2023 +0100" }, "message": "feat(rme): use RIPAS/HIPAS EAC 2 definitions\n\nThis patch:\n- Modifies HIPAS/RIPAS definitions\n as per RMM Specification 1.0-eac2. It matches\n the changes introdiced by TF-A RMM code patch\n https://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21822\n- Return value of host_realm_destroy_undelegate_range()\n changed from void to u_register_t to report errors in\n the code flow.\n- In \u0027struct rtt_entry\u0027 types of \u0027state\u0027 and \u0027ripas\u0027 fields\n changed from \u0027unsigned int\u0027 to \u0027u_register_t\u0027 to match\n the size of values returned by RMI_RTT_READ_ENTRY command.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ied80fb6e1cd4b2da392514ace33201ffd9fc1da9\n" }, { "commit": "4067f8610d0d9e89bac0499f09bcbd89d904ff36", "tree": "e8f75c7f51dbd6d4237c327a63641df9920b5eaa", "parents": [ "f81345ce2cd13d59cb6efa5847ec02baf54cd489" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Jun 12 12:22:37 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:49:49 2023 +0100" }, "message": "feat(rme): support for PMU as per RMM Specification 1.0-eac2\n\nThis patch introduces PMU changes as per RMM\nSpecification 1.0-eac2:\n- pmu_ovf, pmu_intr_en and pmu_cntr_en fields in RmiRecExit\nare replaced with a synthetic single-bit field pmu_ovf_status\nwhich reports the level of the virtual PMU input to the GIC.\nThis field also includes the state of PMU Enable bit PMCR_EL0.E.\nThese changes match RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/21434\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I4135c62927e8156931af9a43a665a19d0e90b342\n" }, { "commit": "f81345ce2cd13d59cb6efa5847ec02baf54cd489", "tree": "ca115e7029fc8f338a96f41ce044583aafa3bc2f", "parents": [ "cd04e41b418decee80a03d25eb7598e7a6b8da95" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Jun 07 17:30:10 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:49:37 2023 +0100" }, "message": "feat(rme): add Realm SVE tests for EAC1\n\nThis patch adds SVE tests for RMM EAC1.\nThe \u0027feature_flag\u0027 parameter passed to\n\u0027host_create_realm_payload()\u0027 function is modified\nto contain \u0027sve_vl\u0027, \u0027num_bps\u0027, \u0027num_wps\u0027 and\n\u0027pmu_num_ctrs entries\u0027. This allows to pass values\nwhich can exceed these fields in feature_register_0\nfor testing. It makes possible to pass\n\u0027Create SVE Realm with invalid VL\u0027 which was\nskipped originally, when SVE was configured with\nthe maximum supported vector length value.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Icd5e57c1bb0cb8dee27b7ace5643aec597e036c1\n" }, { "commit": "1e44db50fb7d1f04c072865e879e7cd5b44a02b8", "tree": "456759fe83f4c0f99e90697dc3af29a52a4576ee", "parents": [ "81025b4c9789e0721db8efcacb7632946d2d108c" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Apr 19 17:26:51 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:45:23 2023 +0100" }, "message": "feat(rme): update API of data/rtt functions\n\nThis patch modifies API of host functions calling\nRMI_DATA_DESTROY, RMI_RTT_DESTROY and RMI_RTT_FOLD\ncommands according to RMM Specification 1.0-eac1.\nIt matches changes in RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20604\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I4410ea1cdbc093359b22a0a9495167efbe443c85\n" }, { "commit": "81025b4c9789e0721db8efcacb7632946d2d108c", "tree": "3f27881f023ff485cd6c90d81741565aad4fad86", "parents": [ "ac174ab64b45ee0d943c1e9c60edae5a0e294c77" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Apr 18 11:55:04 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:43:33 2023 +0100" }, "message": "feat(rme): remove RMI_VALID_NS status\n\nThis patch removes RMI_VALID_NS s2tte status as per\nRMM Specification 1.0-eac1, it matches RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/20581\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Idcf4f421ec8d4d89d441986f50694c82877b3755\n" }, { "commit": "ac174ab64b45ee0d943c1e9c60edae5a0e294c77", "tree": "f4f637dfcea9bf6c14cfb9de626a4abef8f85963", "parents": [ "3d3dea2c3712b9b3f6b69b1690a6c73aeefc9a3e" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 16:35:22 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 13 09:43:21 2023 +0100" }, "message": "feat(rme): remove RMI_ERROR_IN_USE error code\n\nThis patch removes RMI_ERROR_IN_USE error code,\nas per RMM Specification 1.0-eac1, no functional\nmodifications are made.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ia911f9ba07b69d384bbd910f4b4dd3b68646c98a\n" }, { "commit": "44927c3293c656b878ef1c93e1c8cc4dc92944af", "tree": "1bc325c1ab0b86418f58b3c5159a66066709e719", "parents": [ "b69eae0e22dde3487cc0edcf0c8d2e092f54cf13" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 15:17:13 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Sep 12 16:55:14 2023 +0100" }, "message": "feat(rme): pass RD pointer in arg0 register X1\n\nThis patch makes changes according to RMM Specification\n1.0-eac1 for passing RD pointer in arg0 for RMI_DATA_CREATE,\nRMI_DATA_CREATE_UNKNOWN, RMI_REC_CREATE and RMI_RTT_CREATE\ncommands.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: Ia19baaf59209b2de06d63cd392c53e3ee19e3ec9\n" }, { "commit": "b69eae0e22dde3487cc0edcf0c8d2e092f54cf13", "tree": "19a9dc33bef7c68b8de1efe361bbd1f7b30434ef", "parents": [ "8f6d559b99acc7bb347d3f214c0812e562477a41" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Apr 06 10:27:58 2023 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Sep 08 12:24:42 2023 +0200" }, "message": "feat(rmm): modify rmi_realm_params structure\n\nThis patch modifies rmi_realm_params structure\naccording to definition of RmiRealmParams in\nRMM Specification 1.0-eac1.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I63c3097290004de90cd2222b24419aef517d9b49\n" }, { "commit": "9f864523cb2a5a3581b7f5a0b99410838b7cb9bd", "tree": "f8c0446f05fe4e4664f375b846b3952f29473a0b", "parents": [ "ab5321a53201619be2be50b9b0d14cd2fee51299" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Sun Apr 23 16:19:10 2023 -0700" }, "committer": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 03 07:08:20 2023 -0700" }, "message": "test: add discovery of el3 spmd logical partitions\n\nThis patch adds a test to query the presence of an SPMD logical\npartition and also tests basic functionality using the\nffa_partition_info_get_regs abi. Note that the register based discovery\nreports the presence of el3 spmd logical partitions whereas the memory\nbased discovery interface does not report the el3 spmd logical\npartitions. To that end, the patch adds helper functions to use the\nregister based discovery, and also refactors code that can be shared\nbetween the register and memory based interfaces.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nChange-Id: I755ffe4098c635de2c6aeb0ebe73eb16c3acd206\n" }, { "commit": "ab5321a53201619be2be50b9b0d14cd2fee51299", "tree": "2b15c3c77a8dac037f83b588ce4c9680ac5c7abc", "parents": [ "868c623c786b9c403df1eb57515c828e0b2e8982" ], "author": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Sun Apr 23 16:14:28 2023 -0700" }, "committer": { "name": "Raghu Krishnamurthy", "email": "raghu.ncstate@gmail.com", "time": "Thu Aug 03 07:08:20 2023 -0700" }, "message": "feat(ff-a): partition information via registers\n\nThis patch enables basic support for getting partition information via\nthe ffa_partition_info_get_regs abi. This interface can be used to query\npartition information in the absence of rx/tx buffer or when using\nmemory is inconvenient (such as early boot loaders etc). The patch adds\nthe required calls, a few helper functions and enables the use of x8-x17\nas return values, that is required for this abi to work.\n\nSigned-off-by: Raghu Krishnamurthy \u003craghu.ncstate@gmail.com\u003e\nChange-Id: I70ed78e809a5bf77d77a49e5bc122c1989303ebb\n" }, { "commit": "229d8a4c5d118db288325e3390278bc17d2f25ef", "tree": "74b83622d50166d19c842b0db9eaab4f64782b43", "parents": [ "84986d5d9f95d6a300339f94e05003267a743e02", "82bf339c9e178e8200f763146f2f21abee9410ea" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 01 15:54:46 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 01 15:54:46 2023 +0200" }, "message": "Merge \"fix(spm): stop spm from being built for in aarch32\"" }, { "commit": "82bf339c9e178e8200f763146f2f21abee9410ea", "tree": "d37718c9f321f866fbe0480ea758fb5175a5c032", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jul 28 18:32:27 2023 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Mon Jul 31 16:59:23 2023 +0100" }, "message": "fix(spm): stop spm from being built for in aarch32\n\nHafnium does not support Aarch32 therefore we do not want to build\nin this case. Move spm related test helpers into their own file\nand add FF-A tests to the aarch32_tests_to_skip.txt file\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ic5a83ddf4aae2b7dd4b1c30e4cc76b0447e5b405\n" }, { "commit": "9d0cfe88aedc34f1b61a51ff18013743c56e2fbc", "tree": "b5b65d1a477d3d46aacfb69bd3dff348a2136ce4", "parents": [ "85d58f31f121445225c2b9e6ee94c8589cc36669" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Apr 17 10:57:26 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Jul 25 17:00:33 2023 +0100" }, "message": "test(tftf): test PAuth in Realm\n\n- Enable PAuth in Realm RL1 by default.\n- Check if PAuth keys are accessible in Realm RL1.\n- Check if Realm PAuth keys are preserved across RMM entry/exit.\n- Check if NS PAuth keys are preserved across RMM entry/exit.\n- Generate PAuth fault by cloberring LR.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I85d8e03ec604c96117555e7aa866453cb2745cfe\n" }, { "commit": "5270d01e968b1b0a8b853a9263e767a467e541b9", "tree": "ac67959df7b5d536b4c662ed1f0a0e2f19970980", "parents": [ "c1136a849fc21470313e4e852a22ae4b9db50440" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 19 14:53:42 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed May 24 13:40:42 2023 +0100" }, "message": "tftf(rme): check if RMM doesn\u0027t leak Realm contents in SVE registers\n\nThis test verifies that the Realm contents in SVE registers are not\nseen by NS world once the Realm returns back to the host. This test\nperforms the below steps:\n\n1. Set NS world SVE VQ to max and write a known pattern.\n2. Set NS world ZCR_EL2 with VQ as 0 (128 bits).\n3. Create Realm with max SVE VQ\n4. Call Realm to fill in Z registers\n5. Once Realm returns, NS sets ZCR_EL2 with max VQ and reads the\n Z registers.\n6. The upper bits of Z registers must be either 0 or the old values\n filled by NS world at step 1.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I8205190d1ce9c37b99d35cf5b15df21ca9b838c3\n" }, { "commit": "c1136a849fc21470313e4e852a22ae4b9db50440", "tree": "b6b5e8854589497f4e2d2c159f0bd2e590dcd8c5", "parents": [ "d179ddcc64cac3b319b301cfe6c1bc32c1ea0eaf" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 12 15:24:44 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed May 24 13:40:42 2023 +0100" }, "message": "tftf(rme): intermittently switch to Realm while doing NS SVE ops\n\nInterleave NS SVE operations with Realm SVE operations and check whether\nSVE vectors are not affected.\n\nThis test also configures SVE op array and SVE vector length with random\nvalue in NS and Realm for test each iteration.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7a9ba4bd0d298f187baa3048ec622eb97ec3d99f\n" }, { "commit": "0bbdc2dff449036aa65e4c53cd351d01484e0d23", "tree": "60f35abe7f72ade6409b3ffcd46262502a9b6885", "parents": [ "ed7cdc8b28137ab15d9f263825674d156b3c2b30" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Apr 05 15:30:18 2023 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu May 18 16:08:39 2023 +0100" }, "message": "feat(rme): add SVE Realm tests\n\nVerifies Realm with SVE support. Below tests are added\n- Check whether RMI features reports proper SVE VL\n- Create SVE Realm and check rdvl result\n- Create SVE Realm with invalid VL and check if it fails\n- Create SVE Realm and test ID registers\n- Create non SVE Realm and test ID registers\n- Create SVE Realm and probe all supported VLs\n- Check RMM preserves NS ZCR_EL2 register\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I98a20f34ce72c7c1a353ed13678870168fa27c48\n" }, { "commit": "073842171ae9d91b3bdc2031905faafabc7abe57", "tree": "d1b64e32752d2bd8ca31004cb2ee7955f4b7d6ad", "parents": [ "83fe74900c440b2728c458efd8b1c57be20ba039" ], "author": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Mon Nov 28 13:19:11 2022 -0600" }, "committer": { "name": "Sona Mathew", "email": "SonaRebecca.Mathew@arm.com", "time": "Mon May 08 18:19:04 2023 -0500" }, "message": "Add tests for Errata management firmware interface.\n\nAdd tests to confirm that the em_version, em_features and\nem_cpu_erratum_features calls conform to the errata abi spec.\n\nSigned-off-by: Sona Mathew \u003cSonaRebecca.Mathew@arm.com\u003e\nChange-Id: I8395026acc004a10d8c2c17ec689f4e0752143d8\n" }, { "commit": "369955abac0a083f57bfb787eeda82a511eb8fc0", "tree": "54a35fd1b033a708569c91f2dfb1e1516d690cec", "parents": [ "38133fa69bfefab6e3d1d7461b42c806d36ae33b" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Apr 19 18:05:56 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri May 05 13:56:12 2023 +0100" }, "message": "test(tftf): test FPU state registers context is preserved in RL/SE/NS\n\nTest that FPU/SIMD state are preserved during a randomly context switch\nbetween secure/non-secure/realm(R-EL1)worlds.\nFPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers,\nthe test runs for 1000 iterations with random combination of:\nSECURE_FILL_FPU, SECURE_READ_FPU, REALM_FILL_FPU, REALM_READ_FPU,\nNONSECURE_FILL_FPU, NONSECURE_READ_FPU commands,to test all possible\nsituations of synchronous context switch between worlds, while the\ncontent of those registers is being used.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I6da5fd334777000111924bb1239b77123a3dcea6\n" }, { "commit": "38133fa69bfefab6e3d1d7461b42c806d36ae33b", "tree": "3a4ff89fad7a2c24f9d61c1cf28e0d073310ea05", "parents": [ "27479ee85d80268db99f77eea033a691a0bfda56" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Apr 19 17:00:38 2023 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri May 05 13:55:50 2023 +0100" }, "message": "refactor(tftf): move SIMD/FPU save/restore routine to common lib\n\n- Move FPU routines to common lib\n- FPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers\n- Test that FPU/SIMD state are preserved during a context switch\n between secure/non-secure.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I88f0a9f716aafdd634c4eae5b885f839bb3deb00\n" }, { "commit": "cd66846bce520895b901fa384d61157d70902944", "tree": "ba6abe80cb997cd79bbdb9f777e300aebcdd0db8", "parents": [ "eb95d1a202832e834d231c9a40ec6bd628d0590f" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Sun Nov 06 15:29:44 2022 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Apr 24 14:10:10 2023 +0100" }, "message": "test(tftf): test Secure interrupt can preempt Realm EL1\n\n- Send a direct message request command to first Cactus SP to start the\n trusted watchdog timer.\n- Create and execute a busy loop to sleep the PE in the realm world for\n REALM_TIME_SLEEP ms.\n- Trusted watchdog timer expires during this time which leads to secure\n interrupt being triggered while cpu is executing in realm world.\n- Realm EL1 exits to host, but because the FIQ is still pending,\n the Host will be pre-empted to EL3.\n- Once the SP handles the interrupt, it returns execution back to normal\n world\n- TFTF parses REC\u0027s exit reason(FIQ in this case)\n- TFTF sends direct message request command to first Cactus SP to query\n last serviced interrupt and verifies it is Trusted watchdog interrupt.\n- TFTF disables watchdog and destroys Realm payload on exit.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: I6f4cfd334777000d33924bb1239b77182a3dcea6\n" }, { "commit": "eb95d1a202832e834d231c9a40ec6bd628d0590f", "tree": "8b5a4b63a345ccca05bfbf1e9577a537d51af90b", "parents": [ "cd6fdd5c6b8fe046ac43438577ae88269205f956" ], "author": { "name": "nabkah01", "email": "nabil.kahlouche@arm.com", "time": "Sun Nov 06 15:18:06 2022 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Apr 18 02:35:34 2023 +0100" }, "message": "refact(twdog): move trusted wdog API to spm_common\n\nOther tests cases need same API to enable/disable twdog,\nso we need to move them to common place.\n\nSigned-off-by: Nabil Kahlouche \u003cnabil.kahlouche@arm.com\u003e\nChange-Id: Ie54cfdf44777000dda924bb1239b77182a3dced9\n" }, { "commit": "b42d17f3028e759bb38e2e09430dd2b8a7ad1c34", "tree": "a89bfc7eb19d812ae18f728bcc19d6a353b69c3c", "parents": [ "79fc9196228a9aa2fd6832b1cd4275932871d95c" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 04 12:42:13 2022 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Apr 13 09:43:33 2023 +0100" }, "message": "feat(ff-a): memory share bump to v1.1 EAC0\n\nHafnium was updated to match FF-A v1.1 EAC0 [1].\nThis is the equivalent change for FF-A memory sharing\ntests.\n\n[1] https://review.trustedfirmware.org/c/hafnium/hafnium/+/15012\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ibf39ac35e1c7e336843be848fb389401dd792516\n" }, { "commit": "79fc9196228a9aa2fd6832b1cd4275932871d95c", "tree": "9a8416096f7b636165244ad0e6bbc2b8d0877c49", "parents": [ "fc5e23eb867be79cca7200314f9937baf14b80c8", "31b81775100595e7345fc836d5c83b4d7422f8f8" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Apr 05 09:19:44 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Apr 05 09:19:44 2023 +0200" }, "message": "Merge \"feat(memory share): FFA_FEATURES(FFA_MEM_RETRIEVE_REQ)\"" }, { "commit": "31b81775100595e7345fc836d5c83b4d7422f8f8", "tree": "4e1231d2af58033bf108eb310e8b52c73b8f3020", "parents": [ "957863b79430bc89c0894a677190b3a78855515b" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Mar 14 15:38:17 2023 +0000" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Mon Apr 03 13:07:52 2023 +0100" }, "message": "feat(memory share): FFA_FEATURES(FFA_MEM_RETRIEVE_REQ)\n\nUpdates tests to pass when built against\nhttps://review.trustedfirmware.org/c/hafnium/hafnium/+/18909\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: Ic6c39ca6916b9f9298d7668021963fec287b72c8\n" }, { "commit": "fc5e23eb867be79cca7200314f9937baf14b80c8", "tree": "45b69e1ca06d393b1f58d9cd4b16f86bde8a65c5", "parents": [ "8371bb91c1a039e01454cbb4e98bfdb564a8fc16", "cb88add07daff59486f850be6b4cd4750f94d97c" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Sat Apr 01 16:22:24 2023 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Apr 01 16:22:24 2023 +0200" }, "message": "Merge \"test(psci): add tests for OS-initiated mode\"" }, { "commit": "2f30f1030f186760b20cd06b59832e332b2bdd0a", "tree": "e06899ba1be405650b4a15603429900dac67ccc2", "parents": [ "2eb601b98a245df8a31e670a7dc322c2e8f153cf" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Mar 13 19:37:46 2023 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Mar 31 11:41:56 2023 +0200" }, "message": "feat(rme): add PMU Realm tests\n\nThis patch adds Realm PMU payload tests with\nPMU interrupt handling.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2\n" }, { "commit": "cb88add07daff59486f850be6b4cd4750f94d97c", "tree": "3737ad2a8a2aa4c4d9e8d4eea54720009ca4e94a", "parents": [ "e0400c6d2b0372d742cd2cda9aaa7c5cf4741c4a" ], "author": { "name": "Wing Li", "email": "wingers@google.com", "time": "Sat Oct 29 02:32:06 2022 +0100" }, "committer": { "name": "Wing Li", "email": "wingers@google.com", "time": "Thu Mar 23 19:37:52 2023 -0700" }, "message": "test(psci): add tests for OS-initiated mode\n\nChange-Id: I33e135f659aea600f71e053ac3db57eb0172e22b\nSigned-off-by: Wing Li \u003cwingers@google.com\u003e\n" }, { "commit": "c21694de5a14d1b4d32f0fd56cc6cf67750912de", "tree": "206ab841c46c74c2911c34384f8dc8cb3578e214", "parents": [ "17df525fd6be6db49f48f01c5cf26fd2a1279231" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Dec 16 12:19:52 2022 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Dec 16 13:32:45 2022 +0100" }, "message": "fix(tftf): align with RMM bet0 return code\n\nUpdate test cases return codes according to\nRMM Bet0 Specification. These changes are based on\nhttps://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/17892\n\nThis patch also fixes failure of\n\u0027Access from a SP to a Root region\u0027 tests when SPMC\nis not present.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I340f2b3bcee2b072f3874fd6a9f211b48ddf882b\n" } ], "next": "953653743aaf56c979b71e211800cf1bee6c4e34" }