)]}' { "log": [ { "commit": "0fa7d21bf97d14283ebf8c3df866cd05afaff91e", "tree": "b1927aea547dcd718dccc20301cbc301d986faec", "parents": [ "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jun 18 11:17:01 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 14:03:27 2025 -0600" }, "message": "test(fuzz) adding fuzzing for all SDEI calls\n\nadded constraints for all calls\nadded fuzzer feature to start at arbitrary call number\nadded fuzzer features for function exclusion, fuzzer starting/ending call\nworked on additional fuzzing for event_register\n\nChange-Id: I9814b8387ea9e0fb00b53adbdbe0f8429845924e\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb", "tree": "506eaf722681380325bde2a5a9de784697915ba9", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Mar 15 12:49:22 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 10:23:24 2025 -0600" }, "message": "test(fuzz): Capability for random inputs\n\nAdding model for random inputs to SMC calls using a\nconstraint mechanism with a multi tiered sanity\nmetric.\n\nChange-Id: Ia750fa57359baa424f1af273ba24483ae7330c38\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "f44fdf4fc4867afa946b0c2bb644b744a50981f5", "tree": "42471b88543cc40597fb0fffdd306dbb362fac34", "parents": [ "47415f560939c3ddc5272816fdbe4b9a7f61d1ce", "3ca234295ae5802cd684ba56cdec018bde26d2d2" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Aug 20 22:30:25 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 20 22:30:25 2024 +0200" }, "message": "Merge changes from topic \"mp/simd_ctxt_mgmt\"\n\n* changes:\n feat: introduce a new test suite supported by EL3 SPMC\n feat: support Cactus SP to boot on EL3 SPMC\n fix(cactus): skip computing linear core id\n" }, { "commit": "3ca234295ae5802cd684ba56cdec018bde26d2d2", "tree": "42471b88543cc40597fb0fffdd306dbb362fac34", "parents": [ "6f7344b97ab42d045b7a2f502bf9c80100ae8a44" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jul 05 16:26:12 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 19 11:25:51 2024 -0500" }, "message": "feat: introduce a new test suite supported by EL3 SPMC\n\nA new test suite is being created which is supported by Cactus SP. It\naims to exercise the SIMD context management support in EL3 SPMC.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I2a65da8c098b40858a2af0f9012cc225a24e6fcb\n" }, { "commit": "6f7344b97ab42d045b7a2f502bf9c80100ae8a44", "tree": "55dfa7d260bee6752f67d5098de73de612883add", "parents": [ "3b4e989a8c0dfbb3c44dfe3819feca89b6cee5a2" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jul 05 16:21:26 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 19 11:25:51 2024 -0500" }, "message": "feat: support Cactus SP to boot on EL3 SPMC\n\nEL3 SPMC has a limited set of FF-A functionality and does not support\nall the features built into the current Cactus SP implementation.\n\nHence, this patch introduces a build option to strip out few features\nfrom Cactus SP in order to boot it on EL3 SPMC.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I6319563adca67460015b79219ebc5c9468e3d54a\n" }, { "commit": "3b4e989a8c0dfbb3c44dfe3819feca89b6cee5a2", "tree": "951e6f25058090c88c1de8854a23dbf3e9266bec", "parents": [ "47415f560939c3ddc5272816fdbe4b9a7f61d1ce" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jul 05 16:18:34 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 19 11:25:51 2024 -0500" }, "message": "fix(cactus): skip computing linear core id\n\nOn a S-EL2 based SPMC, computing of linear core id is trivial as it\ncan be simply extracted from a read of MPIDR, which is virtualized\nthrough VMPIDR_EL2 register to return vcpu index, followed by a mask operation.\n\nHowever, on a non-SEL2 based SPMC, read of MPIDR by S-EL1 SP returns\nphysical MPIDR. Computing linear core id at this stage in early boot\nis complicated given the operations needed to interpret the various\nlevels of affinity which is platform dependent. Hence, rather than\ntrying to compute linear id from MPIDR, reuse the physical core id\npopulated by SPMC in x4 register.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I21f2fbbd71e8a67c851cb28f92ab5b8d39e0f644\n" }, { "commit": "47415f560939c3ddc5272816fdbe4b9a7f61d1ce", "tree": "f2103abf26962ecd3cbf2e55f450a1771772d333", "parents": [ "8e88c675ce720c443dbb593adc0bf10bfa8840ed", "ccd82702aeb079cc5c20ef4227726c576a731fa9" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Aug 19 16:32:09 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 19 16:32:09 2024 +0200" }, "message": "Merge changes from topic \"tftf_refactor\"\n\n* changes:\n refactor(neoverse_rd): introduce flash and ros macros\n refactor(neoverse_rd): introduce timer and watchdog macros\n refactor(neoverse_rd): define naming convention for CSS macros\n refactor(neoverse_rd): remove deprecated header files\n refactor(neoverse_rd): refactor header files for second gen platforms\n refactor(neoverse_rd): refactor header files for first gen platforms\n" }, { "commit": "ccd82702aeb079cc5c20ef4227726c576a731fa9", "tree": "150279b593dbce693f96454daeae1090720f75b5", "parents": [ "4ccb1ef774f03e2d1cc74fdb93aa53088c1073c6" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Jul 31 16:27:23 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:35 2024 +0200" }, "message": "refactor(neoverse_rd): introduce flash and ros macros\n\nAs part of the refactoring for TFTF on the first and second\ngeneration of platforms, introduce flash related memory layout\nmacros to be added in nrd_ros_def1.h and nrd_ros_def2.h files.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I01929bbd465d777e827c3eb547bb973339bd4308\n" }, { "commit": "4ccb1ef774f03e2d1cc74fdb93aa53088c1073c6", "tree": "32e6cd47416c4032b5a49e200d597c61eb732384", "parents": [ "2d20ac071513593961e7ddd9033eae70b36aaf83" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Wed Jul 31 13:28:08 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:31 2024 +0200" }, "message": "refactor(neoverse_rd): introduce timer and watchdog macros\n\nAs part of the refactoring for TFTF on the first and second\ngeneration of platforms, introduce timer and watchdog related\nmemory layout macros to the nrd_css_def1.h and nrd_css_def2.h\nfiles.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: Iabe4c310ed4297d71cf53869a68d45c5c589fce2\n" }, { "commit": "2d20ac071513593961e7ddd9033eae70b36aaf83", "tree": "90c6981aa04a1f1856d646ab7be335bb595fc69f", "parents": [ "3a426d6d89621fdc7e913e11dc2614742b86a584" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Jul 29 15:35:07 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:24 2024 +0200" }, "message": "refactor(neoverse_rd): define naming convention for CSS macros\n\nAs part of the refactoring for TFTF on the first and second generation\nof platforms, introduce a naming convention for macros within\nnrd_css_def*.h and nrd_css_fw_def*.h. All CSS related macros must adhere\nto the format NRD_CSS_\u003cname\u003e.\n\nChange-Id: I756c46688dd66dfc6b1d89159ebcd39d68c8f91c\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "3a426d6d89621fdc7e913e11dc2614742b86a584", "tree": "69e36c1da8305418047bd698ae17cbcdf75a07cd", "parents": [ "b79a256cfe2419ccc8c48a78a89e7b7735330fe0" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Jul 29 13:11:53 2024 +0100" }, "committer": { "name": "Jerry.Wang4", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 16:14:14 2024 +0200" }, "message": "refactor(neoverse_rd): remove deprecated header files\n\nTF-A underwent a major rehaul in directory structure. This change\ndeals with removal of the previous common include files that are\nnow deprecated.\n\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\nChange-Id: I0c77ee262b26f7bd5d8660b481f19aab8d721246\n" }, { "commit": "b79a256cfe2419ccc8c48a78a89e7b7735330fe0", "tree": "27fb1c3e3ac16344f8cf96eb269a50967e475a74", "parents": [ "61b321e9f8f3a3cd8398b65e5f733abc5577d1a4" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Jul 29 13:07:55 2024 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Mon Aug 19 15:13:10 2024 +0100" }, "message": "refactor(neoverse_rd): refactor header files for second gen platforms\n\nTF-A underwent a major rehaul in directory structure. This change\ndeals with refactoring the header files for second generation platforms\ngrouped as nrd2 in TFTF to a structure that aligns with that of TF-A.\n\nChange-Id: I263a91e768644b491a0dc2b706e7c88d6b65e8a9\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "8e88c675ce720c443dbb593adc0bf10bfa8840ed", "tree": "0ee43633643d2dc742b5bb60e5993a980417afe2", "parents": [ "33d3d3365e2bfe6d912379266c90ff9d33b1418a", "e4f2eaa6f626646cfa3e439086966ac114540cbc" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Aug 19 11:56:08 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 19 11:56:08 2024 +0200" }, "message": "Merge changes from topic \"ar/asymmetricSupport\"\n\n* changes:\n feat: introduce asymmetric feature testing for feat_spe\n feat: skip TRBE extension test if ERRATA applies\n feat: test if errata 2938996 and 2726228 workaround is applied\n feat: skeleton for asymmetric feature testing capability\n" }, { "commit": "33d3d3365e2bfe6d912379266c90ff9d33b1418a", "tree": "8ae11cb64740d350a5a5b459ae8b9e072226e6dc", "parents": [ "cea63b2bbd871a6664b54af325f6a739e8746ff7", "66ee63286f790f61c56dfb8765b5668ccd8991aa" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 16 20:11:45 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 16 20:11:45 2024 +0200" }, "message": "Merge \"fix: cactus_mm is too verbose on some tests\"" }, { "commit": "e4f2eaa6f626646cfa3e439086966ac114540cbc", "tree": "ebb5c60c417e4393c160b78f1c31b780a3c48d2f", "parents": [ "eeac9d97edaf45041b7325f9aade1ad7bfeb6828" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Mon Aug 12 17:59:54 2024 +0100" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 12:07:48 2024 -0500" }, "message": "feat: introduce asymmetric feature testing for feat_spe\n\nChange-Id: Ide9bda1b5f1cabc63241f42b93a672d8e04b8119\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "eeac9d97edaf45041b7325f9aade1ad7bfeb6828", "tree": "3cd50819f0a22bcc8ad0d8d8271f9a29dc3ccf2b", "parents": [ "8191621885dfc65789a19ef0eb590b8639ed87d1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Aug 16 12:34:58 2024 +0100" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 09:08:00 2024 -0500" }, "message": "feat: skip TRBE extension test if ERRATA applies\n\nFor Cortex-A520(2938996) and Cortex-X4(2726228) erratums TRBE feature is\ndisabled by EL3.\n\nCheck and skip TRBE test if the core is affected.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Iaa394ae79dec38d0b369012e149abbc65b0cf0f8\n" }, { "commit": "8191621885dfc65789a19ef0eb590b8639ed87d1", "tree": "8fbbf09517a4e7de5976e8912a594be10cfb1f04", "parents": [ "0145ec3459750f35a6546b3f015906356b7dc6cd" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Aug 15 15:08:23 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Aug 16 09:07:55 2024 -0500" }, "message": "feat: test if errata 2938996 and 2726228 workaround is applied\n\nThis patch confirms if access to trbe el1 register generates an undef\ninjection in affected cores. If a core is affected by errata 2938996/\n2726228 and it generates an undef injection on access to trbe el1 register then\nthe test passes. If it is an unaffected core then the test passes , but\nwhen undef injection doesn\u0027t happen in affected core, the test fails.\n\nChange-Id: I515a9aa4613c6d99ee73e579206089ebf89ffae8\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "0145ec3459750f35a6546b3f015906356b7dc6cd", "tree": "4cb24cf11b7177ae3af728007d27a328f5c636df", "parents": [ "cea63b2bbd871a6664b54af325f6a739e8746ff7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Aug 12 17:59:54 2024 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Aug 16 11:39:26 2024 +0100" }, "message": "feat: skeleton for asymmetric feature testing capability\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I6da831043c9485de00ba29a22ebaea6e9cdb5f57\n" }, { "commit": "cea63b2bbd871a6664b54af325f6a739e8746ff7", "tree": "32fa54ead3a7fb903e1cdb9a2772074a91a96a86", "parents": [ "e4690a01f06e3b67a5afef3644adc1e4db2f5bdb", "7a3c1dc2dc559814882ebf47265e57c31bf05afc" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Aug 15 21:02:33 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 15 21:02:33 2024 +0200" }, "message": "Merge \"refactor(memory share): use UART macro in device mem share\"" }, { "commit": "e4690a01f06e3b67a5afef3644adc1e4db2f5bdb", "tree": "9bb01b8e891c30166a720023001f28a1ae4e6f48", "parents": [ "5dd2a3812bd24b9526dfbaa00a0c3dc3aeb24659", "ea9524006bad4917f1f897be83972ebd18e521a4" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Aug 15 09:05:34 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 15 09:05:34 2024 +0200" }, "message": "Merge \"fix(memory share): undeclared device macro for tc\"" }, { "commit": "ea9524006bad4917f1f897be83972ebd18e521a4", "tree": "9bb01b8e891c30166a720023001f28a1ae4e6f48", "parents": [ "5dd2a3812bd24b9526dfbaa00a0c3dc3aeb24659" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed Aug 14 14:22:12 2024 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed Aug 14 17:56:14 2024 +0100" }, "message": "fix(memory share): undeclared device macro for tc\n\nA previous patch added the PLAT_CACTUS_DEVICE_BASE and\nPLAT_CACTUS_DEVICE_SIZE macro for mapping memory regions during\ncactus boot but did they were not added to the tc platform causing\nbuild issues. This patch adds them.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Icfe9f48b9e0a10a5f3965cd7f383fccc48ad9357\n" }, { "commit": "7a3c1dc2dc559814882ebf47265e57c31bf05afc", "tree": "85926f08919ea8e44916e0c7da67835cd85275d0", "parents": [ "5dd2a3812bd24b9526dfbaa00a0c3dc3aeb24659" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed Aug 14 10:34:03 2024 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Wed Aug 14 10:37:16 2024 +0100" }, "message": "refactor(memory share): use UART macro in device mem share\n\nRemove hard coded UART address in the device memory sharing\ntest by using the PLAT_ARM_UART_BASE macro.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: Ie83e2ff7a41379361018e44d4c6f71198c07e15a\n" }, { "commit": "5dd2a3812bd24b9526dfbaa00a0c3dc3aeb24659", "tree": "24d9365f7ceedcdf76b8835305849e34cd78d74b", "parents": [ "e72df7abe9ef13765b12d97ba814133bea636e3d", "3d8cd68cffa9709895f1758ea144046bf18b896a" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Aug 13 16:42:23 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 13 16:42:23 2024 +0200" }, "message": "Merge \"test(memory share): lend device memory region to sp\"" }, { "commit": "66ee63286f790f61c56dfb8765b5668ccd8991aa", "tree": "80caffd44347692647c2b0ca6c87d8df88055c8a", "parents": [ "e95e53f8607b98d06afdd1302722d3f23dca3591" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 07 14:44:56 2024 +0100" }, "committer": { "name": "Joao Alves", "email": "joao.alves@arm.com", "time": "Tue Aug 13 14:58:47 2024 +0200" }, "message": "fix: cactus_mm is too verbose on some tests\n\nChanging logs printed with \"INFO\"/\"NOTICE\" to\n\"VERBOSE\".\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I89ff56fb631b1a1f393b6d3cdc59bbc7c43cee0a\n" }, { "commit": "3d8cd68cffa9709895f1758ea144046bf18b896a", "tree": "388308d2e41b5994b4d0931c0eded8f38094234d", "parents": [ "e95e53f8607b98d06afdd1302722d3f23dca3591" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Jul 23 14:28:15 2024 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Aug 13 12:03:07 2024 +0100" }, "message": "test(memory share): lend device memory region to sp\n\nAdd test to check that a device memory region can be successfully\nlent to an sp.\n\nThis requires some refactoring of the memory sharing test flow so\nas to use the correct memory type and cachebility attributes for\nthe memory being lent. Also limit the words being written to 1\nword for device memory so we only write to the data register of the\ndevice.\n\nAlso only map device regions from UART2 so that UART0 can be used\nby TFTF in the device sharing test.\n\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\nChange-Id: I9f31769679883f34e0444db75a873765776a85e9\n" }, { "commit": "e72df7abe9ef13765b12d97ba814133bea636e3d", "tree": "b7972649db7e45af03e983df78929d13fce81e0f", "parents": [ "e95e53f8607b98d06afdd1302722d3f23dca3591", "367154e32d6d362691f6dd6499151dd1afa88800" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Aug 08 15:22:54 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 08 15:22:54 2024 +0200" }, "message": "Merge \"fix(ff-a): ivy doesn\u0027t support NPI\"" }, { "commit": "367154e32d6d362691f6dd6499151dd1afa88800", "tree": "b7972649db7e45af03e983df78929d13fce81e0f", "parents": [ "e95e53f8607b98d06afdd1302722d3f23dca3591" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 18:01:02 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Aug 06 16:13:51 2024 +0100" }, "message": "fix(ff-a): ivy doesn\u0027t support NPI\n\nDon\u0027t expect the NPI ID to be reported over the\nFFA_FEATURES interface for calls from EL0.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I59227cc5c144478d053e2bfc33f4ceb3cfa0ca08\n" }, { "commit": "61b321e9f8f3a3cd8398b65e5f733abc5577d1a4", "tree": "863f915c79985c36554a565fb1daa4bffd17d566", "parents": [ "e95e53f8607b98d06afdd1302722d3f23dca3591" ], "author": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Fri Jul 05 10:59:33 2024 +0100" }, "committer": { "name": "Jerry Wang", "email": "Jerry.Wang4@arm.com", "time": "Tue Aug 06 16:06:29 2024 +0100" }, "message": "refactor(neoverse_rd): refactor header files for first gen platforms\n\nTF-A underwent a major rehaul in directory structure. This change\ndeals with refactoring the header files for first generation platforms\ngrouped as nrd1 in TFTF to a structure that aligns with that of TF-A.\n\nChange-Id: I0931f369ff390ae000f49c021a8c9dfc17f34b97\nSigned-off-by: Jerry Wang \u003cJerry.Wang4@arm.com\u003e\n" }, { "commit": "e95e53f8607b98d06afdd1302722d3f23dca3591", "tree": "3466ed6a27f7f27af1d248754a93a73a20a92ef6", "parents": [ "aab060a2db942a9b3ca3b7ff467174e4cadaa174", "1500a6f3cf9424c1f4e2d960fe6270bc664cf63e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Aug 01 17:52:02 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 01 17:52:02 2024 +0200" }, "message": "Merge \"fix(realm): fix RMI commands arguments descriptions\"" }, { "commit": "aab060a2db942a9b3ca3b7ff467174e4cadaa174", "tree": "0bef58a1a1ac541c6d73fe59773d8f9701f87f93", "parents": [ "d0704f69f4824d6100faabd19522e0205c926e92", "6043eaf8e2aad4727f6e3f7199e88b59787d3ad4" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jul 31 19:23:33 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 31 19:23:33 2024 +0200" }, "message": "Merge changes from topic \"od/sme\"\n\n* changes:\n feat(spm): probe SVL for SME related tests\n test(spm): add three SME related tests\n refactor(spm): rename FF-A SIMD test suite\n refactor(spm): test_sve_vectors_preserved\n test(spm): check processor feature regs\n" }, { "commit": "6043eaf8e2aad4727f6e3f7199e88b59787d3ad4", "tree": "0bef58a1a1ac541c6d73fe59773d8f9701f87f93", "parents": [ "277925bbfc6bd1caf47f573dd17569b9a30d7844" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Mar 08 14:14:12 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:22:31 2024 +0200" }, "message": "feat(spm): probe SVL for SME related tests\n\nFor world switch SPM tests checking the SME context, probe the possible\nSVL values in streaming SVE and run tests with each possible SVL.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I5157fc896168f7ea2df131a86acdb1d1f1bb795e\n" }, { "commit": "277925bbfc6bd1caf47f573dd17569b9a30d7844", "tree": "919efe209c396822e0049ce4a02cac8121769047", "parents": [ "e713f655c81cd293ed03211437281c00da444171" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Oct 12 14:56:14 2023 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:22:28 2024 +0200" }, "message": "test(spm): add three SME related tests\n\nSME enter SPMC with SSVE enabled.\nSME enter SPMC with ZA enabled.\nSME enter SPMC with SSVE+ZA enabled.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I092c7618e8de22125b3e957ed557e8177acc2b1f\n" }, { "commit": "e713f655c81cd293ed03211437281c00da444171", "tree": "2ec8d0258d90be8bf17449431855e84078e8f7a4", "parents": [ "57b94c4410d3568754feb1aede059ad794a345a7" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Mar 27 17:09:53 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:21:28 2024 +0200" }, "message": "refactor(spm): rename FF-A SIMD test suite\n\nRename \"SIMD,SVE Registers context\" test suite to \"SIMD context\nswitch tests\".\nRename test case \"Check that SIMD registers context is preserved\" to\n\"Check that Adv. SIMD registers context is preserved\".\nUpdate platform tests_to_skip files accordingly.\nRemove redundant \"SIMD,SVE Registers context\" instance from\ntftf/tests/aarch32_tests_to_skip.txt\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ida5f46a8d0ec822a6629b660c41dfcf9c7e200e7\n" }, { "commit": "57b94c4410d3568754feb1aede059ad794a345a7", "tree": "9c844f15c0f074ac84cc1b27d5f2ccb12873efaa", "parents": [ "2661ba526090e7217d8a334f6f7280c56296f37b" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed May 17 16:41:47 2023 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:21:28 2024 +0200" }, "message": "refactor(spm): test_sve_vectors_preserved\n\nRefactor test_sve_vectors_preserved to probe the possible vector length\nthat the platform implements.\nPerform normal/secure world switches and check that SVE state is\npreserved for all possible vector lengths.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I90f56d9ae97624ceaaae5a4818045922961e5066\n" }, { "commit": "2661ba526090e7217d8a334f6f7280c56296f37b", "tree": "116bda475946441b4c19c87ed211a85e0d8dd32a", "parents": [ "d0704f69f4824d6100faabd19522e0205c926e92" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Feb 19 18:50:53 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 30 14:21:27 2024 +0200" }, "message": "test(spm): check processor feature regs\n\nFor cactus secure partitions, check ID registers report:\n-FPU/Adv. SIMD supported.\n-SVE/SME not supported.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Iba3508d57a8bcb1f554adddef97c4c83f4118a03\n" }, { "commit": "d0704f69f4824d6100faabd19522e0205c926e92", "tree": "cbc56389b7c54fe0021fcfab729b9f5c48f9c5d2", "parents": [ "65442a9ca6fd1062f0eb34c4ac9f62f781dcf352", "c3cf2daed819a9d01feba31832544309c9da8d70" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Jul 29 18:54:59 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 29 18:54:59 2024 +0200" }, "message": "Merge \"feat(amu): test AMU counter restriction (RAZ)\"" }, { "commit": "65442a9ca6fd1062f0eb34c4ac9f62f781dcf352", "tree": "7c4a6528edfddbbcfa4513549244e6e759b16e19", "parents": [ "3d88db7691467351726d05b20d629b94c1fb1b59", "b47ccd0519d2b26fb89bd3434113a17b97e9cc05" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 24 20:04:49 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 24 20:04:49 2024 +0200" }, "message": "Merge \"test(handoff): fix register convention value on test_firmware_handoff()\"" }, { "commit": "3d88db7691467351726d05b20d629b94c1fb1b59", "tree": "10f847b91327aae17ae91a2d6a5342b0a1575e03", "parents": [ "b1ab5854ad384dd1e3abbe760a6b35d6cae9a0bc", "94963d4e739f3fb1accefddd4105cf9140989889" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 24 17:26:44 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 24 17:26:44 2024 +0200" }, "message": "Merge \"feat(fgt): add support for FEAT_FGT2 testing\"" }, { "commit": "b1ab5854ad384dd1e3abbe760a6b35d6cae9a0bc", "tree": "6a8146d2ef87f4c5a0f72f84b850e1577c57a4a4", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6", "cd6c94b20e7450e27254856a82008ca0595d84d1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jul 23 16:00:45 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 23 16:00:45 2024 +0200" }, "message": "Merge \"feat(ls64): add a test for 64byte loads/stores instructions\"" }, { "commit": "cd6c94b20e7450e27254856a82008ca0595d84d1", "tree": "6a8146d2ef87f4c5a0f72f84b850e1577c57a4a4", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Feb 15 17:19:05 2022 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jul 23 14:06:14 2024 +0100" }, "message": "feat(ls64): add a test for 64byte loads/stores instructions\n\nThis patch adds a test to verify the 64 byte load and store\ninstructions introduced by FEAT_LS64.\nThe test primarily executes instructions:\n1. LD64B\n2. ST64B\nand ensures that the NS-EL2 has no dependency on EL3 while\nrunning them.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I7a4ca0ee4a2c18bf0de030c72e35eb218bc6364c\n" }, { "commit": "94963d4e739f3fb1accefddd4105cf9140989889", "tree": "904e5a3428384fae10f4cae54fd91589fc47da8c", "parents": [ "72b56754be783ab84ae57a867a6495a4cbfcace6" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jun 13 17:19:56 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Mon Jul 22 16:21:01 2024 -0500" }, "message": "feat(fgt): add support for FEAT_FGT2 testing\n\nThis patch adds testcase that validates FEAT_FGT2 support\nby reading Fine-grained trap registers that are part of FEAT_FGT2.\nThese registers are only present when FEAT_FGT2 is implemented\n\nChange-Id: Ifc1106d12dbe03b956310d364600368d3f035491\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "72b56754be783ab84ae57a867a6495a4cbfcace6", "tree": "eb7299d596c722a140043073a7cade7d9f50e852", "parents": [ "994e6956079c58766cefac29aaa0f97af10cd73c", "2f2c959871723c303a833778271cd923910deaca" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jul 22 18:08:11 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 22 18:08:11 2024 +0200" }, "message": "Merge \"feat(debugv8p9): test if EL3 has properly enabled FEAT_Debugv8p9\"" }, { "commit": "1500a6f3cf9424c1f4e2d960fe6270bc664cf63e", "tree": "cc5d12ce55e72f6265fc2adc3c09d4a9f3ad3c39", "parents": [ "994e6956079c58766cefac29aaa0f97af10cd73c" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Jul 22 13:29:11 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Mon Jul 22 13:37:30 2024 +0100" }, "message": "fix(realm): fix RMI commands arguments descriptions\n\nThis patch fixes descriptions of arguments and return\nvalues for RMI commands definitions in host_realm_rmi.h\naccording to RMM specification and TF-A RMM implementation.\nThis patch doesn\u0027t introduce any functional changes.\n\nChange-Id: I798ee57dac51ed8bbeb2fb4822788d6ae6ba2963\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "b47ccd0519d2b26fb89bd3434113a17b97e9cc05", "tree": "81c6baf940af8d9cb028aad04265d872b3cd48ae", "parents": [ "994e6956079c58766cefac29aaa0f97af10cd73c" ], "author": { "name": "Levi Yun", "email": "yeoreum.yun@arm.com", "time": "Wed Jul 10 16:18:47 2024 +0100" }, "committer": { "name": "Levi Yun", "email": "yeoreum.yun@arm.com", "time": "Mon Jul 22 12:03:28 2024 +0100" }, "message": "test(handoff): fix register convention value on test_firmware_handoff()\n\nAccording to recently firmware handsoff spec [1]\u0027s \"Register usage at handoff\nboundary\", Transfer List\u0027s signature value was changed from 0x40_b10b\n(3 bytes) to 4a0f_b10b (4 bytes).\n\nAs updating of TL\u0027s signature, register value of x1/r1 should be:\n\nIn aarch32\u0027s r1 value should be\n R1[23:0]: set to the TL signature (4a0f_b10b -\u003e masked range value: 0f_b10b)\n R1[31:24]: version of the register convention \u003d\u003d 1\nand\nIn aarch64\u0027s x1 value should be\n X1[31:0]: set to the TL signature (4a0f_b10b)\n X1[39:32]: version of the register convention \u003d\u003d 1\n X1[63:40]: MBZ\n(See the [2] and [3]).\n\nTherefore, it requires to separate mask and shift value for register\nconvention version field when sets each r1/x1.\n\nCurrently, TRNASFER_LIST test runs only in aarch64.\nSo, change the assert value in test_firmware_handoff() as\naarch64\u0027s x1 value when transfer list deliver.\n\nLink: https://github.com/FirmwareHandoff/firmware_handoff [1]\nLink: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]\nLink: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]\n\nChange-Id: Ibc86963cc5abda3aae4cb8fe34533be250e3dd95\nSigned-off-by: Levi Yun \u003cyeoreum.yun@arm.com\u003e\n" }, { "commit": "994e6956079c58766cefac29aaa0f97af10cd73c", "tree": "ab3c2ed5b796e99da0c12ebb8264935f193d6baf", "parents": [ "de531d27a8cf9222463fa564fa8cbc39ba5d907d", "09d34fc7045099a04fc3b5a16b1a6ff7249f0f77" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jul 18 16:48:34 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jul 18 16:48:34 2024 +0200" }, "message": "Merge \"fix(rme): tests pass with trp but not with rmm\"" }, { "commit": "09d34fc7045099a04fc3b5a16b1a6ff7249f0f77", "tree": "ab3c2ed5b796e99da0c12ebb8264935f193d6baf", "parents": [ "de531d27a8cf9222463fa564fa8cbc39ba5d907d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jul 17 14:35:26 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Jul 17 14:51:54 2024 +0100" }, "message": "fix(rme): tests pass with trp but not with rmm\n\nThe newly added tests to validate the SPMC can recover\nfrom a GPF are passing with TRP but not with RMM.\n\nThe tests are:\n1- initialising memory descriptors;\n2- changing the TX buffers to realm PAS;\n3- causing SPMC to handle GPF;\n4- check it returned expected error code;\n5- reset the TX buffer PAS;\n6- invoking the FF-A call that failed priorly, expecting\nit would this time pass.\n\nStep 6 was failing because the content of the descriptor in\n1 was not preserved, due RMM sanitising them.\nAdding the reinitialisation of the descriptors before\nstep 6.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ic80151c8782cd360eeac1775429b68a1310e1259\n" }, { "commit": "de531d27a8cf9222463fa564fa8cbc39ba5d907d", "tree": "0f59873f9a6d366fe95fe693952cfc257600a001", "parents": [ "8a8536e4d55459f835625d305300d7ba234f8801", "06f430a8d5b52c4b5a176c150acabcad8c4df529" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jul 15 17:58:14 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 15 17:58:14 2024 +0200" }, "message": "Merge changes from topic \"ja/rxtx_protect\"\n\n* changes:\n test(memory share): hypervisor retrieve request fails\n test(memory share): relinquish fails if TX is in realm\n test(memory share): hypervisor\u0027s RX is realm on retrieve\n test(memory share): hypervisor\u0027s TX is realm on retrieve\n test(memory share): retrieve request from VM\n test(memory share): make TX buffer realm\n" }, { "commit": "06f430a8d5b52c4b5a176c150acabcad8c4df529", "tree": "fd3999753c86d8e728d1606a512f81a1c3dc2697", "parents": [ "4e6fa5b68bbf0ae3be536ec90022db38eb3d4012" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 26 19:09:33 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 16:12:15 2024 +0100" }, "message": "test(memory share): hypervisor retrieve request fails\n\nTest that an hypervisor retrieve request fails smoothly\nif either the TX or the RX buffer are in the realm PAS.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I07e4aa2e07cfd1b5132e82bfbf5a2f76a6f34c14\n" }, { "commit": "4e6fa5b68bbf0ae3be536ec90022db38eb3d4012", "tree": "689338a6be4c08c2eaf7bc980c6c0ab0f6d74df8", "parents": [ "8d6843a473dbd32b80c9b9abfdb4b45341a94033" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 26 16:24:07 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 16:12:15 2024 +0100" }, "message": "test(memory share): relinquish fails if TX is in realm\n\nTest that if there is a GPF when the SPMC copies the relinquish\ndescriptor from Hypervisor\u0027s TX buffer, the handling fails\nsmoothly with error FFA_ERROR_ABORTED.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I45b41a6bdd0efa1f0b01645c944d482ecf993a73\n" }, { "commit": "8d6843a473dbd32b80c9b9abfdb4b45341a94033", "tree": "36324135b3e89f2a632f139f9a435e7f3403eeef", "parents": [ "14c4a326e24ccf2563554d7ea0f282c97cef2ae7" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Apr 25 14:17:52 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 16:11:19 2024 +0100" }, "message": "test(memory share): hypervisor\u0027s RX is realm on retrieve\n\nThe test validates that the SPMC is able to recover from a trapped\naccess to a realm RX buffer during the retrieve response. The\ncall to FFA_MEMORY_RETRIEVE_REQ should return FFA_ERROR_ABORTED.\n\nFollowing, reset the RX buffer\u0027s PAS back to NS, and repeat the\nretrieve request. This time the operation should succeed.\nRelinquish the memory to allow the reclaim.\n\nAt the end of the operation, the sender shall still be able to reclaim\nas the retrieve request should have failed to update any of the structures.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I5d0f2a3e5716a3ed27dda4b6592682c34841ed63\n" }, { "commit": "14c4a326e24ccf2563554d7ea0f282c97cef2ae7", "tree": "cc0dd28c1ccb60507544c3f397e8bb6f3a6400d8", "parents": [ "3aa08bc358d4fde60879a652963d5c394b375286" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Apr 25 13:57:09 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 16:11:03 2024 +0100" }, "message": "test(memory share): hypervisor\u0027s TX is realm on retrieve\n\nRecreate a memory share with multiple borrowers, in which one of the\nborrowers is a VM. The Hypervisor\u0027s TX buffer was moved into realm PAS.\nThe retrieve request is expected to fail with FFA_ERROR_ABORTED.\nReset the TX buffer\u0027s PAS back to non-secure, and redo the retrieve\noperation.\nThis time around, the test is expected to pass.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Id60f17804df4e200533dc1cd8066e64121e04dfd\n" }, { "commit": "3aa08bc358d4fde60879a652963d5c394b375286", "tree": "9132e6a44d4c328d9eda4d6ccfd4efde21106ae2", "parents": [ "d8e2fcd3d125f0d49a59d5db8cfc54c32b89602d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Apr 24 22:20:23 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 15 14:32:40 2024 +0100" }, "message": "test(memory share): retrieve request from VM\n\nThe SPMC supports the case in which the hypervisor doesn\u0027t\ntrack the operation. This is usable for multiple borrower operations,\nwith a VM. In this case, hypervisor/OS Kernel shall forward the\nrequests to retrieve memory into the SPMC. This patch adds such\ncase, as we lost this coverage in the Hafnium tests.\n\nChange-Id: Ia217ababd6e4ae0a82bed781b6f217a52a0909e0\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "8a8536e4d55459f835625d305300d7ba234f8801", "tree": "4c570f3632ddb08a2c376055d9c518a1ec5e19d2", "parents": [ "c95644b4802477edceec51af85c9b12d00ac3a98", "f1738b386adba8369bb7ef9344fabac9b5cd1aab" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Jul 12 15:03:52 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jul 12 15:03:52 2024 +0200" }, "message": "Merge \"test(realm): unify SIMD test cases\"" }, { "commit": "d8e2fcd3d125f0d49a59d5db8cfc54c32b89602d", "tree": "55015474b85830d668de9edeabe2ab36245ac76d", "parents": [ "c95644b4802477edceec51af85c9b12d00ac3a98" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Mar 28 15:53:51 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Jul 08 14:23:28 2024 +0100" }, "message": "test(memory share): make TX buffer realm\n\nTest case scenario in which the NWd changes the PAS of the TX\nbuffer to realm, and invokes FFA_MEM_SHARE ABI.\nSPMC should be able to recover and return FFA_ERROR_ABORTED.\n\nChange-Id: I0f0d833f6a7dcf019deaa5ac661f12060c3427c2\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "f1738b386adba8369bb7ef9344fabac9b5cd1aab", "tree": "4c570f3632ddb08a2c376055d9c518a1ec5e19d2", "parents": [ "c95644b4802477edceec51af85c9b12d00ac3a98" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Oct 11 14:09:46 2023 +0200" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jul 04 12:36:06 2024 +0100" }, "message": "test(realm): unify SIMD test cases\n\nThere are two testcases host_realm_fpu_access_in_rl_ns_se and\nhost_and_realm_check_simd which verifies SIMD state across different\nworld switch. This change unifies both these testcases to one test case\nhost_realm_swd_check_simd so that new enhancements or fixes can be done\nin one place.\n\nThis change also increases the code coverage by removing the restriction\non the need for both secure partition and realm payload as a\nprerequisite.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I210acdff9e584cb392a2f1919dce04971fd2fc7a\n" }, { "commit": "c95644b4802477edceec51af85c9b12d00ac3a98", "tree": "15c6d82c45833c621caefd8cdd937537cc51f299", "parents": [ "b5103df4af352c9409fb0756579788d6c0732b87", "33a7ea4c7e1b31569dbc00768e61784dc54df221" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jul 03 22:36:55 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 03 22:36:55 2024 +0200" }, "message": "Merge changes from topic \"km/ffa_version\"\n\n* changes:\n fix: remove `test_ffa_partition_info_v1_0`\n fix: fix test_smccc_callee_preserved\n fix: fix call to `FFA_VERSION`\n" }, { "commit": "33a7ea4c7e1b31569dbc00768e61784dc54df221", "tree": "15c6d82c45833c621caefd8cdd937537cc51f299", "parents": [ "2a426e74d71bd82c360ac4bdd77c8c164b50ac16" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jul 03 15:11:41 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jul 03 15:11:41 2024 +0100" }, "message": "fix: remove `test_ffa_partition_info_v1_0`\n\nThe test `test_ffa_partition_info_v1_0` relies on being able to change\nthe FF-A version after it has been negotiated. That is no longer\nallowed, so the test will fail. It will be moved to the Hafnium test\nframework, where each test runs in its own session.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I377b40b88d26246e9a584d65c7e12bab3050fde7\n" }, { "commit": "2a426e74d71bd82c360ac4bdd77c8c164b50ac16", "tree": "45de78974518c59f994c4a89df562f786e320e30", "parents": [ "1abd8df96be1f7c5efd73ff38e8044bc5c1b6363" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jul 03 15:03:45 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jul 03 15:03:45 2024 +0100" }, "message": "fix: fix test_smccc_callee_preserved\n\nThe `test_smccc_callee_preserved` test was calling `FFA_VERSION` with an\nold FF-A version, which is no longer allowed. Fix it by calling\n`FFA_VERSION` with the current version.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I85b7c2c1bf54719f84fb737fce770f7f5073580b\n" }, { "commit": "1abd8df96be1f7c5efd73ff38e8044bc5c1b6363", "tree": "e8a62fd453c65ef5ba08cca905bf74bf76535ef5", "parents": [ "b5103df4af352c9409fb0756579788d6c0732b87" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Mon Jul 01 10:03:18 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Mon Jul 01 10:12:30 2024 +0100" }, "message": "fix: fix call to `FFA_VERSION`\n\n`SKIP_TEST_IF_FFA_VERSION_LESS_THAN` was attempting to change the FF-A\nversion, when it only needed to query it. The recent change to\n`FFA_VERSION` means that attempting to change the version would fail.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: Id8572d1a4d61b17a85af44f96e3720230d35e698\n" }, { "commit": "2f2c959871723c303a833778271cd923910deaca", "tree": "a3b777765c3959ea183de411cbe73d18e45578b1", "parents": [ "b5103df4af352c9409fb0756579788d6c0732b87" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jun 06 16:34:28 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Fri Jun 28 14:55:27 2024 -0500" }, "message": "feat(debugv8p9): test if EL3 has properly enabled FEAT_Debugv8p9\n\nWhen FEAT_Debugv8p9 is not enabled, access to MDSELR_EL1\ntraps to EL3. Access to FEAT_DEBUGV8P9 control registers\nmust be explicitly enabled in EL3,\n\nThis testcase uses this behavior to test if\nFEAT_Debugv8p9 is enabled or not.\n\nChange-Id: I2f9a0158e9f38eaffac2e27c40d44d3c520d508d\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "b5103df4af352c9409fb0756579788d6c0732b87", "tree": "5bd75867d077a40ebd30f5245ae7d5126524220f", "parents": [ "435177b16708fe4df5692e11c1a4963cfe33a6fa", "7308b12df02634ca78f0e1ea6e4f758a8b3d8e2a" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 27 22:54:08 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 27 22:54:08 2024 +0200" }, "message": "Merge changes from topic \"km/ffa_version\"\n\n* changes:\n refactor: FFA_VERSION related refactors\n feat: print file and line number if `expect` fails\n" }, { "commit": "7308b12df02634ca78f0e1ea6e4f758a8b3d8e2a", "tree": "5bd75867d077a40ebd30f5245ae7d5126524220f", "parents": [ "c884d6bf9e3aca4dc63d318eb99d6141c9353363" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Apr 16 14:02:25 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Thu Jun 27 10:57:30 2024 +0100" }, "message": "refactor: FFA_VERSION related refactors\n\n* Use an enum for FF-A versions.\n* Replace `MAKE_FFA_VERSION` macro with `make_ffa_version` function.\n* Add `ffa_version_is_valid` helper function.\n* Add `ffa_version_get_major` and `ffa_version_get_minor` helper\n functions.\n\nChange-Id: Icbc4b1fa16e826c2ec541add65aa7c14fb397f95\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "c884d6bf9e3aca4dc63d318eb99d6141c9353363", "tree": "9cdc4517af71f3bcf852d1ae8b497e70a0215623", "parents": [ "435177b16708fe4df5692e11c1a4963cfe33a6fa" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Tue Apr 16 14:01:10 2024 +0100" }, "committer": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jun 19 15:20:56 2024 +0100" }, "message": "feat: print file and line number if `expect` fails\n\nThis makes debugging a failed expect easier.\n\nChange-Id: I53a2b3cd1866c14f3983a2e36b94707a94f12ef3\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\n" }, { "commit": "435177b16708fe4df5692e11c1a4963cfe33a6fa", "tree": "14a2c57f6af3ce5453e364e35490c115feba89cf", "parents": [ "07f9671ac3f4b89bda1b9c058c60e7fc39470939", "11f6ee85b015635021083db0f494a2c2957566ef" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jun 18 21:15:44 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 18 21:15:44 2024 +0200" }, "message": "Merge \"fvp: skip cpu cluster power-on check\"" }, { "commit": "11f6ee85b015635021083db0f494a2c2957566ef", "tree": "14a2c57f6af3ce5453e364e35490c115feba89cf", "parents": [ "07f9671ac3f4b89bda1b9c058c60e7fc39470939" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Jun 04 14:15:17 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Jun 18 14:13:19 2024 +0200" }, "message": "fvp: skip cpu cluster power-on check\n\nOn newer FVP models there is known issue which would report\ncluster power-on check with incorrect bits causing this test to\nfail.\n\nSo skip this test for FVP, the issue is expected to fixed in 11.27\nFVP models we could enable it back then.\n\n\nChange-Id: I7f4e7ba1f4b7473736276958663622a9436fcadb\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "07f9671ac3f4b89bda1b9c058c60e7fc39470939", "tree": "a65a8925f6b949d4297c35da834c51e9813c1394", "parents": [ "6316e359865d3fd00f1c782c25089f974b852875", "a45649a48865a609ce854f3dda51b19517b4cbc0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jun 14 22:46:08 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 14 22:46:08 2024 +0200" }, "message": "Merge changes from topic \"ja/memory_share_64\"\n\n* changes:\n test(ff-a): add SMC64 abi to FFA_FEATURES\n test(memory share): use SMC64 rather than SMC32\n" }, { "commit": "6316e359865d3fd00f1c782c25089f974b852875", "tree": "fac0fc93aaadd6a30030a514bb6d958bfc1b7e66", "parents": [ "6d833ef005af59119dbbc9794a3bbfc191eb4f60", "9eb1eaa78ba579295df8876a2480274392ffaa6a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jun 14 10:30:56 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 14 10:30:56 2024 +0200" }, "message": "Merge changes from topic \"lpa2-support\"\n\n* changes:\n feat(rmi): add specific tests for FEAT_LPA2 on RMI tests\n feat(rmi): add support for FEAT_LPA2 to the Realm Extension tests\n" }, { "commit": "9eb1eaa78ba579295df8876a2480274392ffaa6a", "tree": "fac0fc93aaadd6a30030a514bb6d958bfc1b7e66", "parents": [ "7efea19cd6c832ea8a595ef5dc057cca721ca237" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Sep 19 16:07:09 2023 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Jun 13 23:09:38 2024 +0100" }, "message": "feat(rmi): add specific tests for FEAT_LPA2 on RMI tests\n\nThis patch also adds four new tests for RMM:\n\n * Test realm creation with no FEAT_LPA2 and -1 RTT starting level\n * Test realm creation with no FEAT_LPA2 and S2SZ \u003e 48 bits\n * Test creating a realm with FEAT_LPA2 disabled but\n FEAT_LPA2 is present on platform\n * Test creating a realm with FEAT_LPA2 enabled but FEAT_LPA2\n is not present on platform.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c017a16cb5511977bb37f5e146afd5e60b06b97\n" }, { "commit": "7efea19cd6c832ea8a595ef5dc057cca721ca237", "tree": "5f387e91703069d63085e874b0c7727b15d2be80", "parents": [ "6d833ef005af59119dbbc9794a3bbfc191eb4f60" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Sep 19 16:07:09 2023 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Thu Jun 13 13:17:35 2024 +0100" }, "message": "feat(rmi): add support for FEAT_LPA2 to the Realm Extension tests\n\nThis patch adds support to the current Realm Extension tests to\nenable and use 52 bit address size with 4KB granularity when\nFEAT_LPA2 is present.\n\nIn addition, this patch also introduces changes to support passing the\nstarting RTT level and the FEAT_LPA2 enable flag during realm creation\nso they can be used later to implement tests for FEAT_LPA2 on RMI.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I0a930735a44772e5e76d6608c969759f27129917\n" }, { "commit": "a45649a48865a609ce854f3dda51b19517b4cbc0", "tree": "e8f1d835a7974b2215da25148981e9c7d48bfe49", "parents": [ "8984e729cce2c9a1ac8b87fe4e0df886a6ccd6c7" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 08 17:55:35 2024 +0100" }, "committer": { "name": "Joao Alves", "email": "joao.alves@arm.com", "time": "Tue Jun 11 14:52:11 2024 +0200" }, "message": "test(ff-a): add SMC64 abi to FFA_FEATURES\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I387f4fd100462235ecbd298d3921ebab1a004d79\n" }, { "commit": "8984e729cce2c9a1ac8b87fe4e0df886a6ccd6c7", "tree": "1e2546ecd80740da5bfcb7d21bf1f03c2bdc50d2", "parents": [ "6d833ef005af59119dbbc9794a3bbfc191eb4f60" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 07 22:21:54 2024 +0100" }, "committer": { "name": "Joao Alves", "email": "joao.alves@arm.com", "time": "Tue Jun 11 14:52:02 2024 +0200" }, "message": "test(memory share): use SMC64 rather than SMC32\n\nThe SPMC supports memory sharing interfaces to use the\nSMC64 or SMC32 abis.\nThere was not functional change with this. However, making\nTF-A-Tests use SMC64 to validate that they both work.\nHafnium tests will remain using the SMC32 version of the\nABIs.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I31e275ca50973774928591eef0128f0cf0f5be8b\n" }, { "commit": "6d833ef005af59119dbbc9794a3bbfc191eb4f60", "tree": "d821c8d868522feab30123300dd9429ecfd3412d", "parents": [ "de0e8be6dc2d4209544bcd423f735527b7d486c6", "042e96065620549d413c78ca29323f9156764d50" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu May 30 17:27:39 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 30 17:27:39 2024 +0200" }, "message": "Merge \"test(realm): fix pauth exception test\"" }, { "commit": "042e96065620549d413c78ca29323f9156764d50", "tree": "d821c8d868522feab30123300dd9429ecfd3412d", "parents": [ "de0e8be6dc2d4209544bcd423f735527b7d486c6" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu May 30 13:55:11 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu May 30 17:26:59 2024 +0200" }, "message": "test(realm): fix pauth exception test\n\nPauth exception tests fail when FEAT_PAUTH2 is enabled.\nFix error, return success if exception handler is hit,\nremove PAC fields check since the PAC fields can vary based\non the configuration of the system.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Id6312c7ebb7202302d8465f772deb176e419bded\n" }, { "commit": "de0e8be6dc2d4209544bcd423f735527b7d486c6", "tree": "bcc467514b5c46aa049234246d5f69f051f19d51", "parents": [ "fd053b75cde9c2aa1a5b979a2b544890510d4f52", "b324f4d2251094094b32c3138d9313addf443e6b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu May 23 17:51:58 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 23 17:51:58 2024 +0200" }, "message": "Merge changes I77693f76,Ib94efa7b\n\n* changes:\n test(realm): test for rtt_fold assigned\n test(realm): add test for rtt_fold unassigned\n" }, { "commit": "fd053b75cde9c2aa1a5b979a2b544890510d4f52", "tree": "9501450441d97d929f649ca1e72a2edbb390e86b", "parents": [ "ecc32844365ca4745dfd92d1adeaab2f39fdeeb2", "5a1f7bf995ebda9a00012d419bd531618dde49fb" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu May 23 13:51:46 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 23 13:51:46 2024 +0200" }, "message": "Merge \"docs(release): changelog for v2.11 release\"" }, { "commit": "5a1f7bf995ebda9a00012d419bd531618dde49fb", "tree": "9501450441d97d929f649ca1e72a2edbb390e86b", "parents": [ "ecc32844365ca4745dfd92d1adeaab2f39fdeeb2" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Sat May 18 22:14:41 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Wed May 22 19:12:04 2024 -0500" }, "message": "docs(release): changelog for v2.11 release\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Idcfd80ea3fa8b6abb66ca1b9502b7cde44c42a8f\n" }, { "commit": "b324f4d2251094094b32c3138d9313addf443e6b", "tree": "78a6d6800935c6e1cda1a3156ab6facad65383aa", "parents": [ "6c0be80b887f8accf6908b39a7f7b41eda7327d1" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Feb 26 11:06:03 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue May 14 15:38:56 2024 +0200" }, "message": "test(realm): test for rtt_fold assigned\n\nTest for RTT_FOLD for assigned ram, assigned empty\nand assigned ns rtt entries\nFix helper to allow creating L1 block entry for unprotected IPA\n\nChange-Id: I77693f76722d60427edcb112ca58bf772c194b06\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "6c0be80b887f8accf6908b39a7f7b41eda7327d1", "tree": "267f467f11d91951f6a12ad2fae9b079f31ab3f5", "parents": [ "ecc32844365ca4745dfd92d1adeaab2f39fdeeb2" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 20 11:52:57 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue May 14 15:38:51 2024 +0200" }, "message": "test(realm): add test for rtt_fold unassigned\n\nAdd testcase for RMI_RTT_FOLD,\nfor protected IPA unassigned empty and unassigned ram RTTs.\nHost attempts to fold till max level permitted by Arch.\nFix helper to align with RMI call, remove unused code.\n\nChange-Id: Ib94efa7ba60e028bb9f765e769fe377c101a71fc\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "ecc32844365ca4745dfd92d1adeaab2f39fdeeb2", "tree": "812a321c9182243b86010e63d655769764e64b98", "parents": [ "caff038b3f0b261b1fcc14f7918a80fa515202c1", "9668ba5730d9607609879667a19f3249a10f2c99" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon May 13 15:21:50 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon May 13 15:21:50 2024 +0200" }, "message": "Merge changes from topic \"ja/fix_ffa_feat\"\n\n* changes:\n fix(ff-a): tests for FFA_FEATURES\n fix(ff-a): check for presence of SPMC\n" }, { "commit": "9668ba5730d9607609879667a19f3249a10f2c99", "tree": "812a321c9182243b86010e63d655769764e64b98", "parents": [ "b44b4753d698bb7b703198a458e78746cff0ed23" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 11:49:45 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 14:04:21 2024 +0100" }, "message": "fix(ff-a): tests for FFA_FEATURES\n\nThere are different expectations to the result to the FFA_FEATURES\ncall, provided the feature IDs for ME, SRI and NPI interrupt from\ntftf or cactus.\n\nThis patch refactors the test to keep the common part equal.\nFor the differences, locally define the expected test target\nfor the FFA_FEATURES call.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I96f18487c80d789cf4e10ceee0591786708bce51\n" }, { "commit": "b44b4753d698bb7b703198a458e78746cff0ed23", "tree": "67f3fff875a629fa8d8f0d9778126fefb3430ee9", "parents": [ "caff038b3f0b261b1fcc14f7918a80fa515202c1" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 10:15:51 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon May 13 10:15:51 2024 +0100" }, "message": "fix(ff-a): check for presence of SPMC\n\nCheck for the presence of the SPMC in the setup before running\nthe tests.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I4faaf8a169f58a34dda910fd7e00a6844826c17e\n" }, { "commit": "c3cf2daed819a9d01feba31832544309c9da8d70", "tree": "d47120e316a97ea94409e1a61594ec6da1f5a71b", "parents": [ "caff038b3f0b261b1fcc14f7918a80fa515202c1" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Mon Apr 01 13:57:19 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri May 10 13:40:04 2024 -0500" }, "message": "feat(amu): test AMU counter restriction (RAZ)\n\nWhen using AMU counters, there is risk of exposing information to\nlower exception levels. In order to prevent this, counters are\nrestricted, so they are read as zero (RAZ) at a lower EL. This\ntest verifies that counters are read as zero after forcing counting\nthrough instructions that trigger MPMM \"gear shifting\" (e.g.: by\nexecuting SVE instructions).\n\nNote: This test applies to TC2 only, as it is the only platform that\n supports MPMM currently.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: Ic32ba19fa489cf479947d4467ddb84e6abd1b454\n" }, { "commit": "caff038b3f0b261b1fcc14f7918a80fa515202c1", "tree": "6b62c315921ae23374ba8eb6c1ad26dd7a9fd929", "parents": [ "3202b1a27c5316292c893be1af3cd9cee1bc8738", "0569cc02f6effc7e44f39844ef9ffb9b24a823ca" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri May 10 12:51:50 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 10 12:51:50 2024 +0200" }, "message": "Merge \"test(spm): test FFA_FEATURES with NPI, SRI, MEI\"" }, { "commit": "3202b1a27c5316292c893be1af3cd9cee1bc8738", "tree": "2c201ceff7581f93a28f39746bb91dde9d5d472f", "parents": [ "5e44ee68b6cdce5a40137dac562906c7e43cde41", "e533478ae2a0374e25d1eaff68eb5381a33ed345" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri May 10 07:54:23 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 10 07:54:23 2024 +0200" }, "message": "Merge \"feat(smc): add test for pmf version check\"" }, { "commit": "5e44ee68b6cdce5a40137dac562906c7e43cde41", "tree": "7857f66208e9a66d1af3b841f185c47fd2f46c6b", "parents": [ "ddcd122d04150bc035770c60055425a231cccbdc", "c83b17bcd0cfcb2dff8b64c8895bc9684f468b71" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu May 09 21:58:37 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 09 21:58:37 2024 +0200" }, "message": "Merge changes from topic \"ja/rxtx_protect\"\n\n* changes:\n test(indirect message): aborted send from vm to sp\n feat(ff-a): FFA_MSG_SEND2 helper with sender ID\n test(indirect message): aborted send from SP to VM\n fix(notifications): destroy VM\u0027s bitmap\n test(indirect message): request SP to message VM\n feat(cactus): ability to send indirect messages\n feat(indirect message): send and receive messages\n feat(ff-a): define framework notification helpers\n feat(ff-a): add helpers for indirect message\n chore: move test from xml file\n test(rme): rxtx buffers are in the realm PAS\n feat(ff-a): add helper FFA_RX_RELEASE with ID\n" }, { "commit": "c83b17bcd0cfcb2dff8b64c8895bc9684f468b71", "tree": "05cfb8d43bf7ecbe2c254c9bf4ef4dccfe3dffb9", "parents": [ "ffdfafbd49bbe0c6212c00ca4fd910574cac538d" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Apr 09 12:09:12 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "test(indirect message): aborted send from vm to sp\n\nThe SPMC shall copy the message from the VM\u0027s buffer into\nthe SP\u0027s when VM sends indirect message.\nTest that if TX buffer of the VM is added to the realm\nPAS, the operation fails smoothly with FFA_ERROR_ABORTED.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I375d1987429ed38349c25764262f386b6a4cde57\n" }, { "commit": "ffdfafbd49bbe0c6212c00ca4fd910574cac538d", "tree": "d09165edc985faeeaa800aca2570d9a03843fa26", "parents": [ "807822927033f07e272eae2222f78a878a23bbb0" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Apr 09 12:07:11 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(ff-a): FFA_MSG_SEND2 helper with sender ID\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Idaf866a342f2127172b46f7a7a44a599723db7cf\n" }, { "commit": "807822927033f07e272eae2222f78a878a23bbb0", "tree": "7742e64211e9d61a03a34eb2c66edc660a073400", "parents": [ "df2deb36bc477d46e70704e771061dedd64ae996" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 08 18:04:20 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "test(indirect message): aborted send from SP to VM\n\nTest that if the RX buffer of VM is put on the realm\nPAS and an SP attempts to send a message to it, the\noperation terminates smoothly.\n\nChange-Id: Ie7fd316a6256b1c3445dfb7cb8fe1bbd09fffb6e\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "df2deb36bc477d46e70704e771061dedd64ae996", "tree": "2b5e7872bf9a7a094b19c13e413150357290b381", "parents": [ "cd779f49d89524f5236f4f671e3d566c7d333166" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 22 15:17:45 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "fix(notifications): destroy VM\u0027s bitmap\n\nThe last test in the notifications test suite was not\ncleaning up after itself. This change makes the test destroy\nthe bitmap for the receiver VM in the SPMC.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ia96b8d6e680dd0af99a2c767cd35efe38cf10011\n" }, { "commit": "cd779f49d89524f5236f4f671e3d566c7d333166", "tree": "a132844b98b4c5a8865f9d621b01507446026058", "parents": [ "58cc4dad0451ab4669072c654dbc0603932baa94" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 22 14:31:06 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "test(indirect message): request SP to message VM\n\nAdd test for SP to message a normal world VM.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I4c2f3e8995163024453b6f51900599a5f6e60b19\n" }, { "commit": "58cc4dad0451ab4669072c654dbc0603932baa94", "tree": "71869e4f65f6e4f504a56a844205222a80e482ed", "parents": [ "907fcef5cc7b2c09679f7ebf99fd92426c544efc" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 05 14:17:35 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(cactus): ability to send indirect messages\n\nAdd cactus test command for it to send indirect message\nvia FFA_MSG_SEND2 to a designated target FF-A endpoint.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: If519c19dd0ff86252fdd1d749baa2308bf64b936\n" }, { "commit": "907fcef5cc7b2c09679f7ebf99fd92426c544efc", "tree": "f33cc7fda4a2cd7fb4992e2956062ee474624691", "parents": [ "c6b92d5e73a19a9aeeb28d7ac8103cd2dc5adca8" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 08 17:32:58 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(indirect message): send and receive messages\n\nAdded helpers to receive and send indirect messages, respectively:\n- `receive_indirect_message`;\n- `send_indirect_message`;\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I396870f15172f841167627b14c18b1504e0efbee\n" }, { "commit": "c6b92d5e73a19a9aeeb28d7ac8103cd2dc5adca8", "tree": "ee1d3de9d246f6d5abc62170a7b01b656cad09aa", "parents": [ "779fba660d61c8d95adbc66cb5b7086d681e1eaf" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 05 14:16:00 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:35 2024 +0100" }, "message": "feat(ff-a): define framework notification helpers\n\nDefined the helpers to process framework notifiactions.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I979162363898b4f9bf1a3d57327078364883b896\n" }, { "commit": "779fba660d61c8d95adbc66cb5b7086d681e1eaf", "tree": "09298958223dd797fff83fb116e1c76557001137", "parents": [ "2921fba58bd4535f8e944620273ade51f69db63f" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 05 14:14:40 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu May 09 13:48:34 2024 +0100" }, "message": "feat(ff-a): add helpers for indirect message\n\nAdd the header structures for the rxtx buffers, other\nhelper macros, and the FFA_MSG_SEND2 ABI caller.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Ie5c735aa0b33dbf0288b6494362b6e7dc84c6db7\n" }, { "commit": "ddcd122d04150bc035770c60055425a231cccbdc", "tree": "0523e57e331f29106a8e78149674fe9a6979d562", "parents": [ "dfc4d7f46fb95441443066f60d1b855f7ef9c364", "e538be68f9635e3919184b0ed307d40c7a00362e" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu May 09 10:32:12 2024 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 09 10:32:12 2024 +0200" }, "message": "Merge \"fix(lib): save and restore smcr_el2 when cpu suspend and resume\"" }, { "commit": "e533478ae2a0374e25d1eaff68eb5381a33ed345", "tree": "610a7160c96b43e96c00fafcbf9f4676ad6c222c", "parents": [ "dfc4d7f46fb95441443066f60d1b855f7ef9c364" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed May 08 20:33:20 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed May 08 20:33:20 2024 -0500" }, "message": "feat(smc): add test for pmf version check\n\nPMF is moved under vendor specific EL3 range, part of this\nwe have introduced each sub-service have an version scheme[1].\n\nAdd a simple test to check if the sub-service version\nis probed.\n\n[1]:\nhttps://trustedfirmware-a.readthedocs.io/en/latest/components/ven-el3-service.html\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: I885cd1378a8025371172e5cd82fdd111d6832619\n" }, { "commit": "2921fba58bd4535f8e944620273ade51f69db63f", "tree": "5cc656109e7ba43327e00da2b4b34e7658b8bbd2", "parents": [ "a23b8ffefeafc1b5dab19fa2fc78e9596739cbc1" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Apr 24 10:30:35 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 08 16:30:21 2024 +0100" }, "message": "chore: move test from xml file\n\nMove test suite \"SP exceptions\" from \u0027tests-spm.xml\u0027\ninto \u0027tests-memory-access.xml\u0027.\n\nChange-Id: Ia312007cd3c6c6b98ac62cdd7e2b762669fa8e71\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "a23b8ffefeafc1b5dab19fa2fc78e9596739cbc1", "tree": "7cabe04b2079369f331677c84fe442b71408b707", "parents": [ "067daca6eea89d0ac95fcedc12750521ea09b952" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Feb 23 14:50:14 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 08 16:30:16 2024 +0100" }, "message": "test(rme): rxtx buffers are in the realm PAS\n\nAdded a test for which the SPMC attempts to use the RXTX\nbuffers, in an RME enabled platform and in which the buffers\nwere changed to realm PAS.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Idb29f8687fbe5885c00e61155a5ebbdd8908d688\n" }, { "commit": "067daca6eea89d0ac95fcedc12750521ea09b952", "tree": "3372bfa2adc9c32b54417f547de0a78cb141909e", "parents": [ "dfc4d7f46fb95441443066f60d1b855f7ef9c364" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Apr 08 17:31:54 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue May 07 15:46:16 2024 +0100" }, "message": "feat(ff-a): add helper FFA_RX_RELEASE with ID\n\nAdd the helper `ffa_rx_release_with_id` for TFTF\nto mimic the releasing of RX buffer from a hypervisor.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I1edcc1568fd84af72454f3b755ccf16eca321a17\n" }, { "commit": "e538be68f9635e3919184b0ed307d40c7a00362e", "tree": "0523e57e331f29106a8e78149674fe9a6979d562", "parents": [ "dfc4d7f46fb95441443066f60d1b855f7ef9c364" ], "author": { "name": "Jing Han", "email": "jing.han@arm.com", "time": "Wed Apr 17 13:39:10 2024 +0000" }, "committer": { "name": "Jing Han", "email": "jing.han@arm.com", "time": "Tue May 07 12:54:19 2024 +0000" }, "message": "fix(lib): save and restore smcr_el2 when cpu suspend and resume\n\nChange-Id: I0c0f054e025eaafeebbe0adb5d0699def5c4fc60\nSigned-off-by: Jing Han \u003cjing.han@arm.com\u003e\n" } ], "next": "dfc4d7f46fb95441443066f60d1b855f7ef9c364" }