)]}' { "log": [ { "commit": "089c9ad705c1f393d95dd911c76a6772af45d1fd", "tree": "1842ee9a2fabfe773b56c98a76bb7e831b26b5a0", "parents": [ "b674809e4d937d44f85ef53aa2bdbb9f74b569b2" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:03:54 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Apr 25 16:09:37 2025 +0000" }, "message": "feat(handoff): add event log test\n\nAdds a new TFTF test to validate presence and correctness of the TPM\nevent log in the transfer list received from EL3. Uses event_log_dump to\nparse and output log data.\n\nChange-Id: I0b1f782429e4bfe3d1760fce52d40a9836dc27a2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "6186cf96b9713be1a7cb7badd7166203b6145793", "tree": "b003e74f5d98b31f0581a3d85f7babcad255aedd", "parents": [ "aeb5c5ccb10a569c258d2b3e24841da4d234d3df", "6cd8b7d4a7d4d2177f5b51827e9d75321e2a9f90" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Apr 22 17:45:33 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Apr 22 17:45:33 2025 +0200" }, "message": "Merge \"test(trp): test el3-rmm ide km interface\"" }, { "commit": "6cd8b7d4a7d4d2177f5b51827e9d75321e2a9f90", "tree": "8f0136a08fbd66642f159d206ac71c65ea6b2bb4", "parents": [ "118652bf8a430b3085b9b79c589e12d8f80c1113" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Mon Mar 31 17:14:46 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Apr 10 14:54:10 2025 +0200" }, "message": "test(trp): test el3-rmm ide km interface\n\nThis patch introduces a new test function that invokes\nPDEV_CREATE on TRP and tests the RMM-EL3 IDE KM interface\nimplemented in EL3.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: Ib7e9e769191f94927b55b099a8c80d40ffc2a756\n" }, { "commit": "112498c703d48dceea63fe7ab88a8b243513e7e8", "tree": "e46a2cbaba245a68f17c37e32af0df852c331705", "parents": [ "f6f797b92f41b6850a8289e279c55c6f30563ec4" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Feb 18 11:52:12 2025 +0000" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Apr 10 09:56:36 2025 +0000" }, "message": "feat(handoff): add AArch32 handoff support\n\nAdd support for testing firmware handoff in AArch32 mode. This requires\nsome tweaks to enable the boot args from TF-A to be stashed for later\nuse.\n\nChange-Id: Ib1b88688b6229b10020c936319605c7ed6307ca2\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "11e574835b289bc3c9742d76ea697a53023527bc", "tree": "4671e58c1aef29334f69dec38de3b4ded5aa05ed", "parents": [ "a2b6b37ed6eaf7d0f9dfc12a04499863b25cf559" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 28 11:46:16 2025 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 01 13:19:18 2025 -0500" }, "message": "test: deny prohibited ABIs while handling CPU_OFF psci msg\n\nFF-A spec states that SPs are prohibited from invoking Direct request,\nFFA_RUN and FFA_YIELD interfaces while handling power management\nframework message. Make the Cactus SP intentionally invoke prohibited\ninterfaces and attest that SPMC should deny such invocations.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I0a823bf950e3895cb4aff7320c6a0ef7fdec634b\n" }, { "commit": "611d095453cf001e436f795ac8209b27f46a2fdb", "tree": "2435b48f94395c106adc5529e5031ccd92ca3197", "parents": [ "78fb528d0e2ecb53c533f6accf0da1f90d289353" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jan 31 16:07:08 2025 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Apr 01 13:07:09 2025 -0500" }, "message": "feat(cactus): receive psci msg through direct req framework msg\n\nCactus receives PSCI CPU_OFF power management operation message\nthrough framework direct request message and it will respond back\nwith framework direct message if all conditions are met.\n\nCactus SP1 and SP2 explicitly subscribe to CPU_OFF power management\nmessage through their respective manifests.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I790a8698d238e29847e376b4fa9447a6241ef17e\n" }, { "commit": "a35c1db92b51bb785acef300975919bbb0a69aca", "tree": "c95b395d55d04f234c968909d6483fb356c8f251", "parents": [ "677708401f13bfa0c9d974aff8e3db3f67b77c5a" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Apr 01 12:14:25 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Apr 01 12:14:25 2025 +0100" }, "message": "fix(tests): undelegate pdev granules if DA ABI fails\n\nIn host_tdi_pdev_setup undelegate pdev and aux granules upon error\nso that the next testcase in the list doesn\u0027t encounter failure.\n\nThis issue is seen when RMM is build with RMM_V1_1\u003dON and DA ABI\nSMC_RMI_PDEV_AUX_COUNT fails.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I97614dbe7c41b89ff8b72db8cfb178d3c6067249\n" }, { "commit": "677708401f13bfa0c9d974aff8e3db3f67b77c5a", "tree": "9aa226627feb27c793ecb2894519550e18dadfd5", "parents": [ "41567dc5c36eb7cb0c621cc801e99543e95093b3", "8205a64846d581937e77919a9fe858db53324a84" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Mar 31 16:28:02 2025 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 31 16:28:02 2025 +0200" }, "message": "Merge changes from topic \"km/ffa_features\"\n\n* changes:\n refactor: refactor `get_ffa_feature_test_target`\n refactor: use an enum for FF-A errors\n" }, { "commit": "8205a64846d581937e77919a9fe858db53324a84", "tree": "77b786526b95ab4219225966828b847eaf2546ab", "parents": [ "af77b16df26371cf954fd410359f55981683d1ea" ], "author": { "name": "Karl Meakin", "email": "karl.meakin@arm.com", "time": "Wed Jun 19 15:05:19 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Mar 31 11:43:01 2025 +0100" }, "message": "refactor: refactor `get_ffa_feature_test_target`\n\nChange `get_ffa_feature_test_target` to return a `size_t` instead of an\n`unsigned int`, because `size_t` is the return type of operators like\n`sizeof()`.\n\nChange `get_ffa_feature_test_target` to require its argument to be\nnon-null (and assert that it is). This function is only used for getting\nthe array of features to test, so there is no use case where passing a\nnon-null pointer would make sense.\n\nSigned-off-by: Karl Meakin \u003ckarl.meakin@arm.com\u003e\nChange-Id: I33597f1a2f7681eda59ece08062e48c28752c111\n" }, { "commit": "2ba1e7812b494abdfb8f440a161f0ded24bee72a", "tree": "891b504323eff7bb91489d10ae33ed84613a15c3", "parents": [ "ab680e816552ea29184084482fdf63e2f94cd46a" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Mar 26 16:50:18 2025 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Mar 26 17:15:06 2025 -0500" }, "message": "fix(errata_abi): update Cortex-A710 errata list\n\nThis patch updates the out-of-date parameter of Cortex-A710\u0027s\n2058056 erratum in Errata ABI test.\n\nChange-Id: I194eb7fea0504b532c2e15710fbe4b455b7e631b\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "2bd104e2fc8bdf1355ae88ad3e16af9773c1541f", "tree": "8e10eed6f9d1169da2c006f4d017ebe4dcafa4ea", "parents": [ "9d84ad1ceb8256e942213537602c6434577b7bc0" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Fri Mar 21 15:35:27 2025 -0500" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Mar 25 04:49:16 2025 +0100" }, "message": "fix(realm): Fix the LPA2 flag setting for BRBE test\n\nThis patch fixes the LPA2 flag setting for BRBE test.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: Id7c53739cc92275a7018a44c2a3b8fdcf74ec25e\n" }, { "commit": "9d84ad1ceb8256e942213537602c6434577b7bc0", "tree": "f1069ac2c0ef008601b2892cae5960fba6665787", "parents": [ "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "fb96b980c85d916b55c78b7d22e5b6d8e086ca54" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 12 14:54:30 2025 +0100" }, "message": "Merge changes from topic \"kc/fuzz\"\n\n* changes:\n test(fuzz): add FF-A fuzzing\n test(fuzz): Fix single feature testing\n" }, { "commit": "fb96b980c85d916b55c78b7d22e5b6d8e086ca54", "tree": "2a4c319dd3761099924e160acca59d4075bf749d", "parents": [ "2b6c140b52790beebbb921dd0311efefb0bb0c5c" ], "author": { "name": "Kathleen Capella", "email": "katcap01@u203721.austin.arm.com", "time": "Thu Apr 25 17:09:33 2024 -0500" }, "committer": { "name": "Kathleen Capella", "email": "kathleen.capella@arm.com", "time": "Tue Mar 11 12:10:59 2025 -0500" }, "message": "test(fuzz): add FF-A fuzzing\n\nAdd necessary components for FF-A calls to be used in fuzzing framework\nincluding bias tree, `run_ffa_fuzz` helper function, makefile additions,\nand initial SMC description file with FF-A smc calls.\n\nCan use ffa_smc_calls.txt to generate necessary header files.\n\nSigned-off-by: Kathleen Capella \u003ckathleen.capella@arm.com\u003e\nChange-Id: Ib19714342d31cacd818471686a7e4c8910fed5c3\n" }, { "commit": "e3d37e5ce098a4fa5561cdbeb4c702c5164c39a6", "tree": "a0ec5b6bff32d2fa1294f33af597c0d54558306e", "parents": [ "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "c8f5a2ee90f2b376da910f08170af4c4dc7396ae" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 10 14:56:43 2025 +0100" }, "message": "Merge \"test: test the save restore logic for brbcr_el1\"" }, { "commit": "4dc4a8eff548674eb9074bf86ed4007b07ce3150", "tree": "62adf8c4bbb438943acb6e46b52170803509a17b", "parents": [ "3d43731d485b1405c5a224f65a7c2d381d46b093", "43980f9070347622ec9b9ff1b360357a954e96f2" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Sun Mar 09 01:28:21 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sun Mar 09 01:28:21 2025 +0100" }, "message": "Merge \"test(realm): Fix Realm tests marking all memory as RAM\"" }, { "commit": "43980f9070347622ec9b9ff1b360357a954e96f2", "tree": "64495265719ce7b62c47bc5f720d88eec5ee15e9", "parents": [ "90506fbda56864b578980bc2d433f2ba38207e61" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Mar 07 20:35:21 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Mar 07 20:35:21 2025 +0000" }, "message": "test(realm): Fix Realm tests marking all memory as RAM\n\nRealm tests only need access to part of DRAM.\nChange only required region RIPAS to RAM.\n\nChange-Id: Ia0120841e51726785062992e8a32dcd8a924a325\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "3d43731d485b1405c5a224f65a7c2d381d46b093", "tree": "c8d15de87f5a5155e57a145d43cbeb18c118f33f", "parents": [ "9b63fa56b4e21ecb87d409c6a95d1d3d5ee06376", "5668f34a89dfcee72c2a8e6aa443c7436f341d61" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 07 17:50:31 2025 +0100" }, "message": "Merge \"fix: add split workaround check in Errata ABI test\"" }, { "commit": "c8f5a2ee90f2b376da910f08170af4c4dc7396ae", "tree": "625509a3d6d8838e0c31c9e89fbf23ed9361d15f", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Tue Feb 04 15:22:01 2025 -0600" }, "committer": { "name": "Sona Mathew", "email": "sonarebecca.mathew@arm.com", "time": "Thu Mar 06 16:55:05 2025 -0600" }, "message": "test: test the save restore logic for brbcr_el1\n\nThis patch tests the save/restore logic by enabling\nbranch recording at NS-EL2. Additionally this\npatch also tests the trap logic when FEAT_FGT is enabled\nand a Realm tries to access any FEAT_BRBE related registers.\n\nSigned-off-by: Sona Mathew \u003csonarebecca.mathew@arm.com\u003e\nChange-Id: I176ea6feaf01d42cfd6231dc65a9470da8d1e37c\n" }, { "commit": "55d5db87b83b6a073ed3c954d455b862e7b2e7fe", "tree": "0019d75c61f3cbac06bc2f1e25d5944c8f9f3880", "parents": [ "7d3b999376c7416584639411f36bdadf877060d3" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Mar 03 12:56:04 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 21:08:59 2025 +0000" }, "message": "test(realm): extend ripas tests for planes\n\nTest that accessing page with RIPAS\u003dEMPTY from\nPlane N causes plane exit to P0.\n\nChange-Id: Ic57f049d0fa0140630aa7bfc0702a2dc729967a8\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "7d3b999376c7416584639411f36bdadf877060d3", "tree": "c22c6390ab2ec7977af1483c1d4dbf56bd2d388f", "parents": [ "bd729193dcdb19a5f5fa9b259770f1d1f365bad0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 25 15:39:55 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 19:50:15 2025 +0000" }, "message": "test(realm): enhance realm memory exception tests for planes\n\nExtend memory exception tests for planes.\n\nChange-Id: Ifc98b8c67e85b04b36a78f16971d17f05d6a87d2\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "5668f34a89dfcee72c2a8e6aa443c7436f341d61", "tree": "9a7778183d2dedaa383e4c517a4a17dae6a7fa49", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Mar 04 02:01:16 2025 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Mar 06 12:43:08 2025 -0600" }, "message": "fix: add split workaround check in Errata ABI test\n\nThis patch adds support to validate split workarounds\nas part of Errata ABI CPU Features testcase. It also\nimproves the test case, making sure it also\nruns on lead cpu.\n\nChange-Id: Ic21fffdf20714ad639e92ad0be96d2f154f37f04\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "bd729193dcdb19a5f5fa9b259770f1d1f365bad0", "tree": "00c47d7308aee2d02a16a3d4a5fbacaf7cf4407d", "parents": [ "78effaa2c47b04abd68273bdea4ebb4f6f9455c0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 24 17:02:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:57:56 2025 +0000" }, "message": "test(realm): add test for multi rec planes\n\nTest exercises SMC_PSCI_CPU_ON from aux plane.\nRequest is first routed to P0 and then to Host.\nHost enters P0 and then P1 on all CPUs.\n\nChange-Id: I7e34a0070ffa7305b97a0d93de62b64042771a18\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "78effaa2c47b04abd68273bdea4ebb4f6f9455c0", "tree": "9ffb7b9430ee5600da7f8e0cd5cd557752ea85fa", "parents": [ "992c62b427ad7fc425ec3c02e6c2f5e98e94d120" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 07 10:30:15 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Mar 06 09:18:01 2025 +0000" }, "message": "test(realm): validate NS EL1/EL2 context is preserved by RMM\n\n- Test validates that NS EL1/EL2 registers are preserved while\n entering and exiting realm world.\n- Test validates that accessing s2por_el1 in realm causes data abort.\n\nChange-Id: I20cbb9d0d59474507f89ee7cf8e127fff4706610\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "dc26dfe297eaed205fdbf8a0f98706044a97032d", "tree": "730acf129621c21de4c680668a5b8391446f74b1", "parents": [ "de01b5dd3ae940a16ad9f370ad1e734190553e73" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Feb 25 16:12:48 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 28 13:01:34 2025 +0000" }, "message": "test(realm): fix bug in RMI_RTT_SET_S2AP command helper\n\npass correct rec adr to RMI_RTT_SET_S2AP command.\nRSI_MEM_SET_PERM_INDEX can be called from any rec.\n\nChange-Id: I701d7f7f9de80f305d10d2582c614b3090fc2ac5\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "de01b5dd3ae940a16ad9f370ad1e734190553e73", "tree": "9dcf2ef13e4449a8322e044da38a1ed94579e171", "parents": [ "6164898b4355bf1f311a78f0796a75baf7f50983" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Dec 02 21:17:11 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Feb 28 13:01:16 2025 +0000" }, "message": "test(realm): add support for s2poe/pie for planes\n\nAdd support for s2poe/pie for planes.\nUpdate planes test to run with s2poe/s2pie\nboth enabled and disabled.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: If85b8c4cff9e8fe43978088beaf848fe4b2b9a40\n" }, { "commit": "42dd088203e40911c67106d46cfccde58d55e1b5", "tree": "48f1d07ae117eadadd1c0496cc0a8ad895abff3b", "parents": [ "2f2bd013021b4723d42c168f613c4c0ca37223bd", "c779d0d0ac9faf894963675dcccb6110e3f0229a" ], "author": { "name": "Sandrine Afsa", "email": "sandrine.afsa@arm.com", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 25 13:48:59 2025 +0100" }, "message": "Merge changes from topic \"xlnx_fix_custom_inval_entry\"\n\n* changes:\n fix(versal): platform definition of invalid entry\n feat(tftf): new interface to get an invalid entrypoint address\n" }, { "commit": "1e4f7a064f08205a0a37922e660b238be04a8137", "tree": "ccf0e6f9e63ee23a7b249eed564ceedafcee9035", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 14 10:40:56 2025 +0530" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Feb 21 03:38:16 2025 +0000" }, "message": "feat(tftf): new interface to get an invalid entrypoint address\n\nTFTF test for invalid entry address in cpu hotplug, validates\nfor default entry address 0x0 which doesn\u0027t account for platforms\nfor which 0x0 is a valid address. Added function to retrieve invalid\nentry address for default scenario and platform implementation to\nretrieve specific custom invalid entry address.\n\nChange-Id: I9f109acc8d0443dabd3088cb31852900e8e07853\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "2f2bd013021b4723d42c168f613c4c0ca37223bd", "tree": "968260569451b377582640305eea94d206d9a42c", "parents": [ "af821ebb6fa509f8036b2304c313883842d2c93e", "af8934c8574fd64bef6ac4b0201c2144b78c8fd7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 19 13:18:22 2025 +0100" }, "message": "Merge \"test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\"" }, { "commit": "effca4c7db126c7e171256a8a85b60e599274c4d", "tree": "d1abf091b8992adae634a55a98ced19523f676f1", "parents": [ "b298a166f8490bb997b794ab404afa5eaae15fa1" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 16:52:23 2025 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Feb 11 19:03:22 2025 -0600" }, "message": "refactor(errata_abi): add Cortex-X925 and update Cortex-X4\n\nUpdate errate list for Cortex-X4 and add Cortex-X925\nerratum list and support.\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: Ib4e3324e7289d8e400e9a7f90e384d36cdd8bbcb\n" }, { "commit": "5bccf1d188115e268101024018d26b710c86d3c9", "tree": "a185504f6b740a4bfc63fc62f8ee8d91f08d4791", "parents": [ "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Wed Feb 05 18:14:50 2025 +0000" }, "message": "fix(realm): fix PMU save/restore registers\n\nRemove pmxevcntr_el0 and pmxevtyper_el0 registers\nfrom saving/restoring as aliases for pmevcntrN_el0\nand pmevtyperN_el0, selected by pmselr_el0.sel.\n\nChange-Id: I3def527c46d53c3203f7c3ebc565a2aaf282309c\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "73c9d12d96b4f6e9388d12148b90e2de8ee5eeaa", "tree": "010803c4d3fb8186d23cfd2f54f923c8271b45cd", "parents": [ "23ec8506918aff276b21b9543831d4825855906d", "82cd82e9868b1f381a5c8d84195657e1583cfca1" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 05 14:19:06 2025 +0100" }, "message": "Merge \"feat(rme): add tests for FEAT_MPAM on Realms\"" }, { "commit": "82cd82e9868b1f381a5c8d84195657e1583cfca1", "tree": "c7be244d493e784e55df370f501d8c3ba9275523", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Jan 17 17:37:42 2025 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Feb 04 15:01:14 2025 +0000" }, "message": "feat(rme): add tests for FEAT_MPAM on Realms\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6e138cbf121793bdaaa3a44824c0dbff74daced1\n" }, { "commit": "c398c8f7248e9aec29bbc41c94e41005d539863c", "tree": "26f07ed4dc69dfb58120ef36ba0ac6b27477c117", "parents": [ "f00a425e1592bd410ff249c1baab8f3b067b1658" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Jan 16 14:35:48 2025 +0000" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Feb 04 11:38:28 2025 +0000" }, "message": "fix(realm): fix realm PMU tests\n\n- FEATURE_PMU_NUM_CTRS field in feature_flag was used\nto pass number of PMU event counters in realm creation.\nThe width of this field was set to 4, which was not\nenough to pass numbers \u003e 15 and was causing PMU tests\nfailures in FVP configuration with more than 15 event\ncounters implemented.\n- This patch removes all FEATURE_XXX macros for setting\nfeature_flag and replaces them with the corresponding\nRMI_FEATURE_REGISTER_0_XXX to match feature register 0.\n- In host_set_pmu_state() function was setting PMSELR_EL0\nto incorrect value 0 instead of 31 to select PMU cycle\ncounter for configurations with no event counters implemented.\n- Test host_realm_pmuv3_mul_rec() was running incorrectly\nwith number of event counters set to 0 or 31.\n- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0\ncan be constrained unpredictable depending on the\nvalue of PMSELR_EL0.SEL and number of accessible event\ncounters. See corresponding TF-RMM patch\nhttps://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573\nThis patch fixes host_set_pmu_state() and\nhost_check_pmu_state() functions to avoid unpredictable access\nto these registers.\nThis patch makes Realm PMU tests pass for all possible FVP\nconfigurations clusterN.pmu-num_counters\u003d[0...31].\n\nChange-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "042541196fbdd814a7c04ee4e24be94f1a2ab4ef", "tree": "0852b3939e094f0d2fd4b848f3ebb617bfa6efd0", "parents": [ "c8943ba881807922cb84e357461f5482475a47c3", "47078f35247dcb85f5a1ce8ea0bc52d3aee74451" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 03 12:12:03 2025 +0100" }, "message": "Merge changes I7c4ad397,I92e0aeef\n\n* changes:\n test(realm): fix multi rec PMU tests\n test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n" }, { "commit": "c8943ba881807922cb84e357461f5482475a47c3", "tree": "a951dd70d63e29f3616dc48935890f96c8b52fab", "parents": [ "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Feb 01 01:16:18 2025 +0100" }, "message": "Merge changes from topic \"fuzzinit\"\n\n* changes:\n test(fuzz) adding fuzzing for vendor-el3 smccc calls\n test(fuzz) adding fuzzing for all SDEI calls\n test(fuzz): Capability for random inputs\n" }, { "commit": "1d40d724c5c4809ff8efb23bf7ad9ceddb25831c", "tree": "fcf9d81e4b95ffd31ccf36df51df4e1bd0e19221", "parents": [ "0fa7d21bf97d14283ebf8c3df866cd05afaff91e" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jul 23 16:42:16 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 15:13:10 2025 -0600" }, "message": "test(fuzz) adding fuzzing for vendor-el3 smccc calls\n\nChange-Id: I4fd64c0a4c02de6d67a372c9c4bf86bcb9e4d091\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "0fa7d21bf97d14283ebf8c3df866cd05afaff91e", "tree": "b1927aea547dcd718dccc20301cbc301d986faec", "parents": [ "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb" ], "author": { "name": "Alex Liang", "email": "alex.liang2@arm.com", "time": "Tue Jun 18 11:17:01 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 14:03:27 2025 -0600" }, "message": "test(fuzz) adding fuzzing for all SDEI calls\n\nadded constraints for all calls\nadded fuzzer feature to start at arbitrary call number\nadded fuzzer features for function exclusion, fuzzer starting/ending call\nworked on additional fuzzing for event_register\n\nChange-Id: I9814b8387ea9e0fb00b53adbdbe0f8429845924e\nSigned-off-by: Alex Liang \u003calex.liang2@arm.com\u003e\n" }, { "commit": "47078f35247dcb85f5a1ce8ea0bc52d3aee74451", "tree": "03562b94399c44ff32b0c1f81d1c8e35016d8e4f", "parents": [ "414346805fa6589643780f6f9ce181facf2e1271" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 16 18:54:24 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 17:44:19 2025 +0000" }, "message": "test(realm): fix multi rec PMU tests\n\n- set different values of PMU event counters for each rec\n- check PMU counters are preserved for each rec\n\nChange-Id: I7c4ad3971d4a10b4515be0dfe096bebf8d903c71\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "91d9b91c9233592c72bbe27fd72ee6a208ffe678", "tree": "ff6e9cd81f0c19684cf5b58067d02d58f1738b19", "parents": [ "506b98f78e4bb38314129f85da27523f18dd8f8f", "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:53:15 2025 +0100" }, "message": "Merge changes I7a3b9103,I590fc5a1,Ie6924bcb,I484cbd32\n\n* changes:\n test(realm): add testcase to enter all planes\n test(realm): handle permission fault for planes\n test(realm): add support for planes shared buffer\n test(realm): add plane PSI interface\n" }, { "commit": "af8934c8574fd64bef6ac4b0201c2144b78c8fd7", "tree": "33c29f9b95a29b2b879fc8055d994787b5e79fce", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Fri Jul 26 14:51:14 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Jan 31 16:48:58 2025 +0000" }, "message": "test(psci): add test to validate \"psci_is_last_cpu_to_idle_at_pwrlvl\"\n\n* This patch adds a test that suspends to affinity level 2 with another\n CPU running in a different power domain.\n\n* Previously with the bug identified and resolved in commit (01959a1),\n the function \"psci_is_last_cpu_to_idle_at_pwrlvl\" checked only one\n power domain when suspending to level2. This meant that if there was\n a cpu running outside the power domain of the calling CPU, the suspend\n request would be allowed. But in this case, the request should be\n denied. This test case validates this behaviour and ensures the\n request is denied.\n\n* This patch also adds the following global variables to parameterise\n and reuse the existing functions for the new test.\n * test_should_suspend - an boolean array that allows you to leave\n some CPUs running.\n * test_should_deny - a boolean to specify if the suspend request\n should be denied.\n * cpu_finished - an array of events so that the running CPUs know\n when to terminate.\n\n* Additionally this patch also adds a function to get a CPU that is\n in a different cluster to the lead CPU.\n\nRefer to TF-A commit (01959a1) for more information on the bug.\n\nChange-Id: Ib163aa8d5347baeaa47d1ae6f59599f1c68c11a8\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "5029797b5ad87f4da330ee7c37dfbcb02d0af3cb", "tree": "506eaf722681380325bde2a5a9de784697915ba9", "parents": [ "f44fdf4fc4867afa946b0c2bb644b744a50981f5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Mar 15 12:49:22 2024 -0500" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Jan 31 10:23:24 2025 -0600" }, "message": "test(fuzz): Capability for random inputs\n\nAdding model for random inputs to SMC calls using a\nconstraint mechanism with a multi tiered sanity\nmetric.\n\nChange-Id: Ia750fa57359baa424f1af273ba24483ae7330c38\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\n" }, { "commit": "506b98f78e4bb38314129f85da27523f18dd8f8f", "tree": "da255312e5288c911622d83ee21bf8f2cf790a83", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "43d421bb292984fdc56269fb3e87e619ca0892d3" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 31 17:13:36 2025 +0100" }, "message": "Merge \"test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\"" }, { "commit": "414346805fa6589643780f6f9ce181facf2e1271", "tree": "69b825442caff18f8b25d6eee80140c80832d176", "parents": [ "158208e895d38d659d216c793d42d132ed90e598" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Dec 05 14:57:48 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 14:53:41 2025 +0000" }, "message": "test(realm): add test for RSI_PLANE_REG_READ/WRITE command\n\ntest for RSI_PLANE_REG_READ/WRITE command\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I92e0aeef48c9b2abe26e5d3b2ea62669a22d4f8b\n" }, { "commit": "158208e895d38d659d216c793d42d132ed90e598", "tree": "86cf20c9982b4b186bcc17944cd9f569701f6fe4", "parents": [ "a0736c3dbf83f3c00ca98c83534070be259fb822" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 10:12:41 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:23 2025 +0000" }, "message": "test(realm): add testcase to enter all planes\n\nTestcase creates realm with all 4 planes.\nEnters all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I7a3b9103e1fbcfe98117c02827624a2fc2d24fc2\n" }, { "commit": "a0736c3dbf83f3c00ca98c83534070be259fb822", "tree": "4ab625c28b93f9fe02b4072720ab05a342175b26", "parents": [ "69cae79515b85f13a3ee957474231e51e879c4d8" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 09:34:35 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:55:12 2025 +0000" }, "message": "test(realm): handle permission fault for planes\n\nAdd support for handling permission fault in planes.\nSet s2ap in RTTs.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I590fc5a1c43357b117fa5cb76e8c699c4c7eebad\n" }, { "commit": "69cae79515b85f13a3ee957474231e51e879c4d8", "tree": "80f41a9c19830d92bf024f5c9eabf65e2b505a5a", "parents": [ "9110508906774bb3949fa5609a5d767021a6a4e8" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 04:30:00 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:53:44 2025 +0000" }, "message": "test(realm): add support for planes shared buffer\n\n- Add support for per plane shared buffer.\n- Map shared buffer in all Aux RTT if\n realm uses multiple RTTs.\n- Support realm_printf for all planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ie6924bcb9e9bb3b8c368f796d33f84f4f6821935\n" }, { "commit": "9110508906774bb3949fa5609a5d767021a6a4e8", "tree": "8233efd6cb8467288ae76544c0682c4e89766dc2", "parents": [ "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 05:29:55 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 31 13:53:25 2025 +0000" }, "message": "test(realm): add plane PSI interface\n\nAdd Plane service routine interface.\nAux plane can communicate with primary plane using PSI\nPSI uses hvc conduit from aux plane.\nAdd initial printf support for planes\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I484cbd32791970c6e22c5d63e13b43807f4f3c06\n" }, { "commit": "43d421bb292984fdc56269fb3e87e619ca0892d3", "tree": "2d0fe5cbece559a93ff6eb935d36bc0dadf2a4d8", "parents": [ "ff52ad6026cbbd688f9c381a48110148e01dcf45" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Wed Sep 11 12:01:56 2024 -0500" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Thu Jan 30 11:51:52 2025 -0600" }, "message": "test(security): add testcase for SMCCC_ARCH_WORKAROUND_4\n\nTesting was conducted using FVP Version 11.26.11\non Cortex-X3, Cortex-X4, Neoverse-V2, Neoverse-V3\nand Cortex-X925. Additionally, negative testing\nwas performed on Cortex-X2.\n\nThis patch tests SMCCC_ARCH_WORKAROUND_4 [1] for CVE_2024_7881 [2]\n[1]: https://developer.arm.com/documentation/den0028/latest\n[2]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881\n\nChange-Id: I4c33b7a9372236ce3ef38f9d1786d5794bb7ddbc\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "e7fc4a1f18aaae688c6076eabc0e803c96df7e0b", "tree": "05125c5f936c21bd2d9cc5915bf9544333182bd9", "parents": [ "079c37c7aaf219182d7061427e22c65aaa416b37", "ff2f1150099940a2767381df1701c9007eec8e68" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 30 13:48:42 2025 +0100" }, "message": "Merge changes from topic \"qemu_tests\"\n\n* changes:\n fix(test): compile error in test_irq_spurious_gicv2.c\n feat(timer): support PPI timer interrupts\n" }, { "commit": "3fa036df6a185bcc50ef1c50b79b272e39fd7bc1", "tree": "31c1eabeaf17fcec944f87cee1464f62697ab5eb", "parents": [ "ff52ad6026cbbd688f9c381a48110148e01dcf45" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 30 09:21:53 2025 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 30 09:28:51 2025 +0000" }, "message": "test(realm): fix compilation errors\n\nFix compilation errors when LOG_LEVEL is verbose.\n\nChange-Id: Ic87a7ad901e1cd57a20d6ae14fbd4d8165e4e168\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "6681b7a6fc142f8b1ba0f97d41d239fe6e874c37", "tree": "ce9e06d8cf11d20bfe42b02034bd2a7a2255f053", "parents": [ "3e9115dc182c6240f9289912b6f528853b510e10" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Nov 01 16:27:44 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jan 27 07:38:50 2025 -0600" }, "message": "fix: skip CPU cycle allocation for SP vCPU to reach message loop\n\nWith the support added in Hafnium SPMC for secondary CPU cold boot,\nsecondary execution contexts of SPs dont need a round of CPU cycles\nthrough ffa_run to reach the message loop.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ib02f51abb31d30329d43f0937ba30d721504bc53\n" }, { "commit": "3e9115dc182c6240f9289912b6f528853b510e10", "tree": "bb75b4c42e4b096554dacad9bc3b399284f04097", "parents": [ "4686bbfe1f0122f07aa65f2d9c11fca81557ec54", "5abab7674959cb2fa3211e5199ac3115e72e86dc" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jan 13 14:18:16 2025 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 13 14:18:16 2025 +0100" }, "message": "Merge changes I62946a18,Ida808b9d,Ic71af8d0,I505a4a05\n\n* changes:\n test(realm): add support for RSI Planes ABI\n test(realm): add AUX RTT support for planes\n test(realm): allocate memory for multiple planes\n test(realm): add initial support for planes\n" }, { "commit": "5abab7674959cb2fa3211e5199ac3115e72e86dc", "tree": "86f2a0e558571dc8e5f616e31d1564f8fbf11d5a", "parents": [ "8f5dae9067e545618830abda9fc5f143c58e7c9f" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 04:57:53 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Fri Jan 10 16:39:05 2025 +0000" }, "message": "test(realm): add support for RSI Planes ABI\n\nAdd Planes RSI support.\nAdd helpers to setup initialize and enter planes.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I62946a185c47fe77a04f42751d0b0a467d41ceee\n" }, { "commit": "8f5dae9067e545618830abda9fc5f143c58e7c9f", "tree": "733dc1d8d0aeda4faae063a30dc7c46da1c1e96f", "parents": [ "31b2552f3cc950e1244377e9246a6c85467d59a0" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 03:38:31 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 09 10:28:51 2025 +0000" }, "message": "test(realm): add AUX RTT support for planes\n\n- Add support for new RMI_RTT_AUX ABIs and helpers.\n- Create and destroy aux mappings for realm creation\n with multiple planes and multiple RTTs.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ida808b9d311e8a662587257e015b0f62c110ac3b\n" }, { "commit": "31b2552f3cc950e1244377e9246a6c85467d59a0", "tree": "2b2c7558cf3359fdff5b87b9c7c064d474d060b5", "parents": [ "1ea7a8612622a7f3baf14ef3bb94d59d898231b4" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 03:13:27 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 09 10:25:59 2025 +0000" }, "message": "test(realm): allocate memory for multiple planes\n\n- Update realm create helpers to allocate memory\n and copy multiple plane images.\n- Also allocate memory for multiple Aux RTTs.\n- Increase realm heap by 2 MB.\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: Ic71af8d0b156ad60d8cb8c5bafe6f9b7df8280c7\n" }, { "commit": "1ea7a8612622a7f3baf14ef3bb94d59d898231b4", "tree": "2e0a208919dae9e7adfa2c7c95693bac3470fbca", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Wed Nov 27 02:36:40 2024 +0000" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Thu Jan 09 09:52:07 2025 +0000" }, "message": "test(realm): add initial support for planes\n\n- Added changes to RMI feature register\n and RmiRealmParams for planes\n- Updated realm create helpers to support planes\n\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\nChange-Id: I505a4a05f222e2a28eed33bded3bae687fc29eec\n" }, { "commit": "7b7ca22f1b54632558663f5816d103105ce3aaec", "tree": "e3a9111c51ba449327eeeecbb638f03b5dab3cc6", "parents": [ "566f07da79dc559c405e79327be47740b7a66686" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 13:33:18 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "test(SMCCC): test SMCCC_ARCH_FEATURE_AVAILABILITY\n\nThis test calls the function with each valid argument and checks that\nevery bit is set if its relevant feature is present in the system. It\nalso fails the test if any set bit in the return value has not been\nchecked. This should serve as a reminder to update this test for every\nnew feature that is implemented.\n\nOnly feature that tfa supports are tested with the expectation that new\nones will be added in the future.\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I801326a49810bb76bfc3b9d06780d416dcc32a40\n" }, { "commit": "566f07da79dc559c405e79327be47740b7a66686", "tree": "02ce87e53805217055fd73771267ba2f8f9edac0", "parents": [ "4e282424143dbd73cd0248d470d03cccb9005f42" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 13:31:48 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:56 2025 +0000" }, "message": "refactor(SMCCC): use a macro to check for the SMCCC version\n\nThis is similar to other macros that skip the test if a condition is failed.\n\nChange-Id: If8ff8b29473151edf1872636bce9ee0950851c42\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "4e282424143dbd73cd0248d470d03cccb9005f42", "tree": "b5da9ecc48fe84d374c9e04de6a0d3e2c7f8aa0d", "parents": [ "a4d7972176c2fdc3c66e6ba3347d24f65bac670c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Oct 25 14:34:13 2024 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 09 08:44:16 2025 +0000" }, "message": "feat: add register definitions needed for SMCCC_ARCH_FEATURE_AVAILABILITY\n\nAlso slightly optimised some redundant feature functions\n\nCo-developed-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\nChange-Id: I6dcc11060a2f3697a8aa41443e9cfc665b2b7c74\n" }, { "commit": "d1a7f4d2bd6b4867a71366b58b00759724ef99d1", "tree": "7439900358c0026fe7c781e725e6ba0b1c3fd37b", "parents": [ "5d10ae70d57bc836d417b7a7592ecc96a528bc38" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Tue Nov 26 12:50:47 2024 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 19 14:51:47 2024 +0000" }, "message": "feat: add tests to check SCTLR2, THE and D128 sysregs\n\nThis patch adds test cases for verifying that the system registers of\nFEAT_SCTLR2, FEAT_THE and FEAT_D128 (FEAT_SYSREG128) are working\ncorrectly by performing a series of reads and writes to the registers.\n\nChange-Id: I5c102daa358a7ec5d1801395bc875e9850e83939\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\n" }, { "commit": "1c06e7712d4fe6efe068f60ad8b177931dc346e8", "tree": "ebc140f0239edb16dfb4341f9d12ca33cd364cb2", "parents": [ "dc18ace1a36a4f684f1e4c7ef193a34c563d75c1" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Dec 16 13:26:48 2024 +0000" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Dec 16 13:26:48 2024 +0000" }, "message": "fix(realm): rmi_realm_params structure is not zeroed upon realm creation\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I2513a6977625f98e7d81f9cb57ee3e724fcbff81\n" }, { "commit": "dc18ace1a36a4f684f1e4c7ef193a34c563d75c1", "tree": "49bb31a7dc6df8d5b09217a4e38f5e493ffa87d8", "parents": [ "a07460f4520b05d6f01624a857e6b6c0a6a41235", "1ab21e5e0f05680e5a30093fe6a7eff99fdcb150" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Dec 12 22:42:25 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Dec 12 22:42:25 2024 +0100" }, "message": "Merge \"feat(fpmr): test FPMR register access\"" }, { "commit": "425b45479fbe0b49d15ac1dfe8d8f1b532cd29e9", "tree": "ae13a7c6fcfdd64db025b24b280d4127ac7df246", "parents": [ "f93aef1e0ff8e8d11716c23c44f8cbc51060778a" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Nov 13 18:39:45 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 17:41:57 2024 +0100" }, "message": "fix(spm): handle ME in indirect msg tests\n\nFor the following tests involving FF-A indirect messaging:\ntest_ffa_indirect_message_sp_to_vm\ntest_ffa_indirect_message_sp_to_vm_rx_realm_fail\n\nSending an indirect message from the SP triggers the SRI NS interrupt\nwhile the SP runs and initiates a managed exit.\nBack in TFTF, add a handler for processing the SRI and resume the SP\nafter managed exit using the dedicated cactus command.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I95918fd78e9dec20470307d60c8dd31d6c5b5a7c\n" }, { "commit": "f93aef1e0ff8e8d11716c23c44f8cbc51060778a", "tree": "8dd46da9ae2a912839e164daeba4d01850f327fa", "parents": [ "6ab3fe91df8c0dd9d1589411d1ed168247ad8edf" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 15:41:34 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 16:17:27 2024 +0100" }, "message": "fix(spm): omit enabling/disabling SRI physical interrupt\n\nThe SPMC takes care of enabling the SRI physical SGI interrupt on all\ncores. Omit doing it from TFTF.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ie1a4bdc898213107959eaac912aae5c6058114f5\n" }, { "commit": "6ab3fe91df8c0dd9d1589411d1ed168247ad8edf", "tree": "48ee3ae83f90f8d2d8830b040baf3e3803e95322", "parents": [ "d25c577499280db4b1923f924210b9590039ab0c" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 11:46:28 2024 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Dec 05 14:23:07 2024 +0100" }, "message": "fix(spm): fill TX buffer again after undelegate\n\nSimilarly to the fix done in [1], the RME undelegate operation on TX\nbuffer scrubs its contents in test_ffa_memory_share_fragmented_tx_realm,\nso re-init the TX buffer again with the fragment after undelegate.\n\n[1] https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/30027\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I6a716d42f79474b8d884826a0a09eac01e487176\n" }, { "commit": "cc8543823e6104d67e74892cd6d84c52f3cc4a14", "tree": "468fb7e0e6ff7d864f3483fe72c1c23d4edba18e", "parents": [ "5929bfe75a40577efa77cf23a2fc4057ced92e7e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:29:13 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 18:10:28 2024 +0000" }, "message": "feat(realm): call RMI_PDEV ABIs from host realm mgmt\n\nInitial support to invoke RMI PDEV ABIs from host realm management. The\nPDEV management testcase host_test_rmi_pdev_calls does PDEV create, get\nstate, get aux count, communicate, set public key, stop, destroy calls.\nThese calls internally retrieve device certificate, extract public key,\nand establish a secure session with the PCIe device.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: If007b5170cbaa932c4f18a01a825a8dc0b752f26\n" }, { "commit": "5929bfe75a40577efa77cf23a2fc4057ced92e7e", "tree": "054341aebc883a57faab006f4d700d596c323203", "parents": [ "67a3ffba147f4a5d996fa5e307fd59389925434e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 12:28:00 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Nov 28 18:10:28 2024 +0000" }, "message": "refactor(realm): define PCIe helpers\n\nThis patch refactors the existing PCIe and DOE\nhelpers to define generic helpers to make them\nreusable across more tests.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: I56a9f5c59715c7916f3f737ed6d3af94b0e3679f\n" }, { "commit": "2c2810f79e57e78d77899084b5439cbdd1aaa464", "tree": "5d5644927acc2f4a212ba18558c7ed57f3d1e07c", "parents": [ "ea43ac0daef913576cf214454cf81482d8cf109a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 15 17:11:24 2024 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Nov 26 05:21:39 2024 +0200" }, "message": "fix(realm): make PCIe tests default for testing\n\nThis patch moves the PCIe DOE test to the default realm world\ntestsuite.\n\nAlso fixes some build issues and hardens the PCIe functions.\n\nNote that FVP_Base_RevC model needs to have the following\noptions enabled for the PCIe tests to work :\n\n -C pci.pcie_rc.ahci0.endpoint.doe_supported\u003d1\n -C pci.pcie_rc.ahci0.endpoint.ide_supported\u003d1\n\n\nChange-Id: Icfd6b68799b0bacb44299c6a3cf99a3c425f833d\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "ea43ac0daef913576cf214454cf81482d8cf109a", "tree": "92ec8ee102ec299ca25e55fac006d80139c28135", "parents": [ "0f744702ebd52d2efcf42db52613aee5b8991fd0", "ebce902b9f4088972070a10a3c63b168621b4588" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Nov 25 11:09:52 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 25 11:09:52 2024 +0100" }, "message": "Merge \"test(realm): add test for validating RTT calls\"" }, { "commit": "88ffad277a35f0dcecd19d167021b26d2c7bc790", "tree": "bc1a7e0a794c8a79438eb9df86c5ed86757daf5e", "parents": [ "c79338af9a3e9cb24b90afd79491c85b7ef11d72" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Fri Oct 11 21:22:29 2024 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Wed Nov 20 15:06:04 2024 -0600" }, "message": "test(realm): add tests for realm attestation\n\nWith this patch, TFTF adds two tests for realm attestation. One tests\nthe full process of retrieving the attestation token from the host. The\nsecond one triggers a failure by calling RSI_ATTEST_TOKEN_CONTINUE\nwithout calling RSI_ATTEST_TOKEN_INIT first.\n\nSigned-off-by: Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: I885402377af1f02ce7e90c80dbe1079fe4c1b178\n" }, { "commit": "1ab21e5e0f05680e5a30093fe6a7eff99fdcb150", "tree": "17c76bf9488a15d760977c0631fd35ef733554a1", "parents": [ "b607317afc8c6ad5f37ac8873dfa8777c50b96aa" ], "author": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Nov 12 10:52:08 2024 -0600" }, "committer": { "name": "Arvind Ram Prakash", "email": "arvind.ramprakash@arm.com", "time": "Tue Nov 19 15:16:35 2024 -0600" }, "message": "feat(fpmr): test FPMR register access\n\nChange-Id: I326690564d01596fb4f4b449f4f314699ccfe3c4\nSigned-off-by: Arvind Ram Prakash \u003carvind.ramprakash@arm.com\u003e\n" }, { "commit": "46d0228e2a1a17c57be8f5011f183ea28e6ba518", "tree": "ce322be37116651bf3ab1d681632c176f8105233", "parents": [ "7c78f7b4a74e58512ff6998f7a5438520e58c343" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Nov 18 16:58:37 2024 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Nov 19 11:22:08 2024 +0100" }, "message": "fix(serror): use custom argument for incrementing elr_elx\n\nAdd a custom argument to increment the elr_elx after handling SError.\nIn some cases, to prevent re-triggering the instruction, ELR needs\nto be incremented by 4. In other cases, it may not be necessary.\n\nThis argument is passed to the handler, which then decides whether\nto increment elr_elx by setting the passed argument accordingly after\nhandling the SError.\n\nChange-Id: I404f3c5e24f894502a8d00c73649be0b2dd540fa\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "7c78f7b4a74e58512ff6998f7a5438520e58c343", "tree": "ea7bd3a6363d1bf5686e5cfbd2a92cabec7a3df6", "parents": [ "4c19b48e1d0aed1cfb94785c86544d2a58190ade" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Fri Oct 25 11:44:32 2024 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Tue Nov 19 10:10:16 2024 +0000" }, "message": "feat(realm): add test case for FEAT_DoubleFault2 support on TF-RMM\n\nWhen FEAT_DoubleFault2 is supported, TF-RMM must take into\naccount bit SCTLR2_EL1.EASE in order to decide whether to inject\na SEA into the sync exception vector or into the serror one.\n\nThe test on this patch verifies that TF-RMM injects the SEA\nto the right vector depending on SCTLR2.EASE bit.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I6c976fecb04d123e3efb96c5973b1466e241097f\n" }, { "commit": "ff2f1150099940a2767381df1701c9007eec8e68", "tree": "967bb3dde609bc228d80457c803adc7d65cbc641", "parents": [ "5a44078f017c581c9def5cfd697f0579fc6ff89c" ], "author": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Thu Jun 20 13:00:16 2024 +0200" }, "committer": { "name": "Jens Wiklander", "email": "jens.wiklander@linaro.org", "time": "Fri Nov 15 09:06:21 2024 +0100" }, "message": "fix(test): compile error in test_irq_spurious_gicv2.c\n\nPrior to this patch with PLATFORM_CORE_COUNT defined to 32 test_irq_spurious_gicv2.c fails to compile with the following error:\ntftf/tests/runtime_services/trusted_os/tsp/test_irq_spurious_gicv2.c: In function ‘test_multicore_spurious_interrupt’:\ntftf/tests/runtime_services/trusted_os/tsp/test_irq_spurious_gicv2.c:26:37: error: left shift count \u003e\u003d width of type [-Werror\u003dshift-count-overflow]\n 26 | #define CPU_TARGET_FIELD ((1 \u003c\u003c PLATFORM_CORE_COUNT) - 1)\n | ^~\ntftf/tests/runtime_services/trusted_os/tsp/test_irq_spurious_gicv2.c:232:48: note: in expansion of macro ‘CPU_TARGET_FIELD’\n 232 | gicv2_set_itargetsr_value(TEST_SPI_ID, CPU_TARGET_FIELD);\n | ^~~~~~~~~~~~~~~~\n\nFix this by using 0xFF as the width of each field in GIC_ITARGETSR is 8\nbits.\n\nChange-Id: I310cf7ada7230051ba3cedf6752f26c80528b198\nSigned-off-by: Jens Wiklander \u003cjens.wiklander@linaro.org\u003e\n" }, { "commit": "ebce902b9f4088972070a10a3c63b168621b4588", "tree": "8491cfde6a9444c216a9bf4b4939966103f43919", "parents": [ "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f" ], "author": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Mon Sep 23 14:36:47 2024 +0100" }, "committer": { "name": "Shruti Gupta", "email": "shruti.gupta@arm.com", "time": "Tue Nov 12 11:19:14 2024 +0100" }, "message": "test(realm): add test for validating RTT calls\n\nadd test to validate RMI_RTT_CREATE and RMI_RTT_MAP_UNPROTECTED command\nfail when LPA2 is disabled and PA \u003e\u003d 48 bits\n\nChange-Id: I6281da6b68d78bc42c1c87e2572c63c4aae63cfd\nSigned-off-by: Shruti Gupta \u003cshruti.gupta@arm.com\u003e\n" }, { "commit": "8a0c1d10d501e7778a5f90ee6f1d6ada8cbde30f", "tree": "f8979bc2f589f87671ed5e50216364e64e1dc06d", "parents": [ "a7aa825f328ce0d844f134af8f0cd7468f811d07", "e9c18128b5234f1e76aa0147666d04de61bca93b" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Nov 11 18:48:06 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 11 18:48:06 2024 +0100" }, "message": "Merge \"test: arch timer in nwd is honored across world switch\"" }, { "commit": "4b67210c4ae32e723fc5805f3b7e8c48fb8ec962", "tree": "b5d66c48a39a422a902364d694a41521c35de431", "parents": [ "0db4a3cdde090a94721a8a598cbbbf857f7cf47f" ], "author": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Mon Sep 23 13:06:15 2024 +0200" }, "committer": { "name": "Igor Podgainõi", "email": "igor.podgainoi@arm.com", "time": "Fri Nov 08 17:48:28 2024 +0100" }, "message": "feat(cm): add test to validate EL2 regs during context switch\n\nVerify that EL2 system registers are preserved when switching\nfrom Normal world to Secure world and vice versa. Do this by\nmodifying the live EL2 register state and dumping it to memory,\nthen performing an FF-A Cactus call and checking whether the\nstate matches the previously saved context.\n\nChange-Id: I0537b4d671c72c0a2fd29ac7e218bf69e1c66001\nSigned-off-by: Igor Podgainõi \u003cigor.podgainoi@arm.com\u003e\n" }, { "commit": "86e5e5d500a839920edcf71783f31b7e4fc20c42", "tree": "c9b96514811730ade3be4cd5449254025502fb07", "parents": [ "af49307617a6861c13008371a1e5397b278bb4c7" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Aug 05 19:52:29 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Nov 07 16:52:38 2024 +0000" }, "message": "feat(cm): add tests to validate EL1 regs during context switch\n\n* This patch adds a test to verify the integrity of the el1_context\n registers across world-switch.\n\n* It aims at testing the save and restore functionality provided\n by the EL3 context management library.\n\n* It validates the EL1 ctx register entries after interaction with\n TSP (S-EL1) software.\n\nChange-Id: Id435d9d7699231d66e9e7acdbb3459ec439d2aef\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "e9c18128b5234f1e76aa0147666d04de61bca93b", "tree": "0f9061891055da886d987e8245b046d8eaf4288b", "parents": [ "97ee573bf9b34d8d8352b6a8af2f2c47c0f41bf9" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Sep 10 16:28:48 2024 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Nov 06 17:31:31 2024 -0600" }, "message": "test: arch timer in nwd is honored across world switch\n\nThis patch introduces a test to ensure that the functionality of arch\n(EL1 physical) timer configured by NWd endpoint, such as an hypervisor,\nis not corrupted by SPMC when an SP also configures the arch timer for\nits own use.\n\nAlso, necessary helpers and utilities to create the test scenario have\nbeen added.\n\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I1cfd1e1117412b2b23a57af30064c41dc2e66e0b\n" }, { "commit": "72b7ce11edd6042d5a3fe75bba83fb5e7f58ee08", "tree": "6fba961e72767d7a0c58b914acc24723190802a3", "parents": [ "a62262f047c9c48c65021f4e23be7b709e8c2811" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Nov 04 13:44:39 2024 +0000" }, "committer": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Wed Nov 06 21:46:35 2024 +0100" }, "message": "feat(ls64): add LS64_ACCDATA test\n\nFEAT_LS64_ACCDATA introduces the system register ACCDATA_EL1, its value\nreplacing the first four bytes of the data provided to an ST64BV0\ninstruction. As this system register would need context switching\nbetween non-secure and secure worlds, there is an SCR_EL3 bit to allow\ntrapping accesses from lower ELs into EL3.\n\nIntroduce a check to verify that accesses to this system register do not\ntrap into EL3, if the CPUID registers advertise this feature.\nBits[63:32] of ACCDATA_EL1 are described as RES0, so mask those bits\nwhen comparing the read-back values with the written one.\n\nChange-Id: Ia32bcf7187356c701470a1757708b3d554e88629\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "a62262f047c9c48c65021f4e23be7b709e8c2811", "tree": "c9e1bef94457fea688cd23beb3cb694a3f3cb531", "parents": [ "97ee573bf9b34d8d8352b6a8af2f2c47c0f41bf9", "f2f1e27c93581b6a9770b8b70780bcd80b961b24" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Nov 06 21:36:42 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 06 21:36:42 2024 +0100" }, "message": "Merge \"feat(tcr2): add asymmetric feature testing for FEAT_TCR2\"" }, { "commit": "97ee573bf9b34d8d8352b6a8af2f2c47c0f41bf9", "tree": "a6b003f7f9c39f43d3441cb2fbf20870daa80f7d", "parents": [ "a948c86a529c14b98214915d291ed997096836e8", "357177b52669038f8748789de0f2c4ba39e8d09a" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Nov 06 11:32:24 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 06 11:32:24 2024 +0100" }, "message": "Merge \"fix(realm): fix host_realm_init_ipa_state()\u0027s retry path\"" }, { "commit": "357177b52669038f8748789de0f2c4ba39e8d09a", "tree": "9f76b4e859037498025b749b4960a0b6ddd303b7", "parents": [ "205400d4e105efde03c993cee10defdaf3190504" ], "author": { "name": "pedro martelletto", "email": "martelletto@google.com", "time": "Mon Nov 04 10:41:31 2024 +0000" }, "committer": { "name": "pedro martelletto", "email": "martelletto@google.com", "time": "Wed Nov 06 06:55:38 2024 +0000" }, "message": "fix(realm): fix host_realm_init_ipa_state()\u0027s retry path\n\nmake sure to initialise the IPA state after creating RTTs and before\nreturning success.\n\nChange-Id: I47da3b0cd343c86567c1c38ebd08a50e1129c455\nSigned-off-by: pedro martelletto \u003cmartelletto@google.com\u003e\n" }, { "commit": "bd2fd4e8d3923d46e3e8ee68f591eaaff2ed07e3", "tree": "6f643f4af1de221d2738a3b0d3092c909aa52105", "parents": [ "80354938c1384a9238b9056ad9f3468defc5d49b" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Oct 15 11:31:54 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 05 10:17:39 2024 +0000" }, "message": "test(memory share): SPMC handles GPF in FFA_MEM_FRAG_RX\n\nAttest SPMC can handle a GPF when handling a FFA_MEM_FRAG_RX.\nThe FFA_MEM_FRAG_RX accesses to a NWd RX buffer, during the\na multi-fragment retrieve request.\nThe SPMC should handle the GPF, and smoothly return\nFFA_ERROR_ABORTED to the NWd.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: Id2116755beddb9350f84155ea4a358de679ac780\n" }, { "commit": "80354938c1384a9238b9056ad9f3468defc5d49b", "tree": "9bd76349090a2c961e34647714278a3cd8249a5e", "parents": [ "c362de3e39acb112b466212713476e367ba509d2" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Oct 15 11:24:27 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 05 10:17:39 2024 +0000" }, "message": "refactor: hypervisor retrieve request helpers\n\nFactored out of hypervisor_retrieve_request the looping\npart, for retrieving the fragments of a fragmented\nretrieve request. This is to aid testing hypervisor retrieve\nrequest, when it faults in the middle of the operation.\n\nAlso added two helpers to access the size of a fragment\nand the total size for both ABIs:\n- FFA_MEM_RETRIEVE_RESP.\n- FFA_MEM_FRAG_TX.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I49d12d69eff8c132b0a29954772dd6634f590f88\n" }, { "commit": "c362de3e39acb112b466212713476e367ba509d2", "tree": "a5dc47ab586d6eb0a5ec3535b262a003eb9b6dae", "parents": [ "205400d4e105efde03c993cee10defdaf3190504" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Jun 20 12:50:14 2024 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Nov 05 10:17:23 2024 +0000" }, "message": "test(SPM): GPF during FFA_MEM_FRAG_TX\n\nTest that the SPMC recovers from a GPF when handling\nFFA_MEM_FRAG_TX interface.\n\nChange-Id: I5b98419b32cdfd26431b461aede96e88d238b78b\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "205400d4e105efde03c993cee10defdaf3190504", "tree": "88d8cddd6a8f5aee6924bb857e624319d0373b85", "parents": [ "a0c8d3f504eab3ea929ef669bc746ae5a8daa2ef", "dadd2e26e3edb16903c0e5679a4388f2202537a8" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Oct 31 18:31:44 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 31 18:31:44 2024 +0100" }, "message": "Merge \"Revert \"fvp: skip cpu cluster power-on check\"\"" }, { "commit": "f855e9fa002d8bfe25d72e726f16098190076e53", "tree": "1dabc799480b69a2ba571f9b3505da95c3d2001f", "parents": [ "d551d093073f0c5ca808eaed6076f2f62bd336fa" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:11:47 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:33:19 2024 +0000" }, "message": "fix(ff-a): report FFA_YIELD support for SPs only\n\nThe FFA_YIELD interface is only valid at the virtual\nFF-A instace, and not at the physical FF-A instance.\nI.e. SPs can use the ABI with SMC conduit into the SPMC.\nThe NWd is not expected to call FFA_YIELD into SPMC.\n\nThis patch drops FFA_YIELD from the common test target\nfor FFA_FEATURES between tftf and cactus/ivy partitions,\nadds the specific tests to both of them with expected\ndifferences.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I7d9a5729b82f3f2f77631a8ab6210fa026078d7d\n" }, { "commit": "d551d093073f0c5ca808eaed6076f2f62bd336fa", "tree": "dc4ea52bfc57413f3640bb5e410a8cc1f121e933", "parents": [ "fd43af6083438eca1540ff58468f0173da1350ff" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:09:47 2024 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed Oct 30 11:09:47 2024 +0000" }, "message": "fix(ff-a): reporting support of indirect messaging\n\nHafnium was not reporting the support of indirect messaging\nor direct messaging 2, added in FF-A v1.1 and FF-A v1.2,\nrespectively, in the returned information of the ABI\nFFA_PARTITION_INFO_GET. The patch [1] fixes this issue.\n\nThis patch makes equivalent change to the arguments expected\nfor the FFA_PARTITION_INFO_GET return on cactus partitions.\n\n[1] https://review.trustedfirmware.org/c/hafnium/hafnium/+/31712\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I29ef51a7566a09b6fbeada55725d571f0440fbcd\n" }, { "commit": "fd43af6083438eca1540ff58468f0173da1350ff", "tree": "d49a4388a0f99d2b0ea4b2e55c2aa11f9e623e20", "parents": [ "37a5034e1c96dffd897e7231d406fccb3131aa8d", "951376bb0e8af291cc412be9460e4195692fbd87" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Oct 29 12:10:22 2024 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 29 12:10:22 2024 +0100" }, "message": "Merge changes from topic \"xlnx_plat_versal2\"\n\n* changes:\n docs(versal2): add AMD Versal Gen 2 documentation\n feat(versal2): add support for AMD Versal Gen 2 platform\n" }, { "commit": "f2f1e27c93581b6a9770b8b70780bcd80b961b24", "tree": "e3f021e5f5f1af491df4544fc00fc1e433d9e6f8", "parents": [ "37a5034e1c96dffd897e7231d406fccb3131aa8d" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Sep 03 11:49:51 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Oct 24 11:19:43 2024 +0100" }, "message": "feat(tcr2): add asymmetric feature testing for FEAT_TCR2\n\nChange-Id: I07b27ff58ccf471ccc43643141e2dfe70083fd13\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "9601dc5343d4aee267a5adcebeb2495f395acc4d", "tree": "ba51882deb7e44d3b0832904d0ef0ca61b8c871b", "parents": [ "70de3ff58e06f66819e98a25a9167c6751f87330" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Wed Aug 28 17:27:18 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "feat: skip asymmetric tests when features not present\n\nThis patch skips asymmetric tests, when features are not present\nand will split them into separate tests.\n\nThe problem with the previous test structure was that you can\u0027t\ndistinguish between a trap to EL2 and an undef injection. This meant\nthat on some platforms, the tests would pass even without the\nasymmetric support patches. In these cases, it would be better if the\ntest was skipped, since there\u0027s no situation where it fails.\n\nFor example, if FEAT_SPE wasn\u0027t present on any cores, and the\nasymmetric support patches weren\u0027t applied, then the test would pass.\nThis is because the register accesses would trap to EL2.\n\nThis patch skips the test on every core that doesn\u0027t have the feature\nimplemented. It also splits the test into separate test functions.\nThis allows us to display a separate test result for each asymmetric\ntest. It also allows us to skip the whole test if the feature isn\u0027t\npresent on any cores, since in these cases the test would always pass.\n\nThe structure of the test is similar to\ntftf/tests/runtime_services/standard_service/psci/api_tests/cpu_suspend/test_suspend.c.\nThe run_asymmetric_test function takes a function as an argument, and\nruns it on all CPUs.\n\nThe whole test should only be skipped if the test was skipped on all\nCPUs. The test on each CPU can\u0027t return TEST_RESULT_SKIPPED, because\nthe whole test is skipped if any of the CPUs return\nTEST_RESULT_SKIPPED. Instead, to skip a test, the test returns\nTEST_RESULT_SUCCESS, then sets a flag in the test_skipped array. This\narray is checked at the end by the run_asymmetric_test function.\n\nChange-Id: I802431714de3eb8b059e8fc56f7e19fc94e3e8fb\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "70de3ff58e06f66819e98a25a9167c6751f87330", "tree": "2823ae213e5f1a81ffbc15db0e3a8c1f508ad941", "parents": [ "4397e4444950fcb138122d5fa047fc2250fcc375" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Tue Aug 20 11:27:25 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "refactor: clarify which kind of exceptions it catches\n\nThe function that was called \"undef_injection_handler\" doesn\u0027t just\ncatch undef injections. It also catches traps to EL2 due to registers\nnot being present. Both cases have the same EC value, so it is\nimpossible to distinguish between them.\n\nThis patch edits variable names and adds a comment to clarify this.\n\nChange-Id: Ie7405d7611afc1d2ff2207cfa4a08de3cbc9dff7\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "4397e4444950fcb138122d5fa047fc2250fcc375", "tree": "b8e9c43197838f4128523feda90644836e5085e5", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Charlie Bareham", "email": "charlie.bareham@arm.com", "time": "Tue Aug 20 10:17:38 2024 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Oct 23 18:14:11 2024 +0100" }, "message": "refactor: only register undef_injection_handler during register accesses\n\nBefore, the undef_injection_handler was registered at the start of the\ntest, and unregistered at the end. This patch makes it so the\nundef_injection_handler is only registered where a register is being\naccessed. This gives us more control in which exceptions we catch.\n\nChange-Id: I4262288543cac6b1f9ab0e6fd5092d7e3a31fb75\nSigned-off-by: Charlie Bareham \u003ccharlie.bareham@arm.com\u003e\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "7dbb6c110477adaca32d3afce88135ec76dac6e7", "tree": "26bd19cda1226669eb5c8abe0e5b4995fcb606be", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Fri Oct 04 03:22:30 2024 +0000" }, "committer": { "name": "Maheedhar Bollapalli", "email": "maheedharsai.bollapalli@amd.com", "time": "Tue Oct 22 04:39:42 2024 +0000" }, "message": "feat(versal2): add support for AMD Versal Gen 2 platform\n\nIntroduce platform support for AMD Versal Gen 2.\n\nSummary:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nTests Skipped : 194\nTests Passed : 29\nTests Failed : 0\nTests Crashed : 0\nTotal tests : 223\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nNOTICE: Exiting tests.\n\nChange-Id: I608dd556be402f97f9960c688b7d0caa6f17c5c3\nSigned-off-by: Akshay Belsare \u003cakshay.belsare@amd.com\u003e\nSigned-off-by: Michal Simek \u003cmichal.simek@amd.com\u003e\nSigned-off-by: Maheedhar Bollapalli \u003cmaheedharsai.bollapalli@amd.com\u003e\n" }, { "commit": "dadd2e26e3edb16903c0e5679a4388f2202537a8", "tree": "6f931efd4b82f48ffedde56e79997aa466a96ea9", "parents": [ "32c1669e0143b9aad3bad5af2e1069cb08047d2a" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Oct 16 22:25:58 2024 -0500" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Oct 17 16:29:19 2024 +0200" }, "message": "Revert \"fvp: skip cpu cluster power-on check\"\n\nThis reverts commit 11f6ee85b015635021083db0f494a2c2957566ef.\nThis now addressed through a TF-A patch -\nhttps://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/31902\n\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nChange-Id: Icea0cefb93723343586e5b3a57a2c9b90a9bf5c6\n" }, { "commit": "0db147aecaec8d10aff6103d038dc149710b25f7", "tree": "b21bf750fe12bc45bc707d1665459a088db4e8ef", "parents": [ "93d4df58e20da38742613eb1fe2fe401289aeaf2" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 16:46:35 2024 +0100" }, "committer": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 17:06:06 2024 +0100" }, "message": "feat(realm_payload): use random start REC\n\nThis patch modifies tests below\nhost_test_realm_create_enter\nhost_test_multiple_realm_create_enter\nhost_realm_multi_rec_single_cpu\nto start Realm execution with a random REC number.\n\nChange-Id: I5961f953efc4dab25d301a7026d0c3949701df4a\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "93d4df58e20da38742613eb1fe2fe401289aeaf2", "tree": "2de78b803f816449d34ce2ec0f869be3dcbd7ffb", "parents": [ "2fe9ef36da3f6d0b2a02423f7892739129c6a3b2" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 09:44:52 2024 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 17:57:08 2024 +0200" }, "message": "feat(realm_payload): increase maximum number of RECs\n\nThis patch changes maximum number of RECs per realm\nMAX_REC_COUNT from 8 to 17. This makes possible to\ntest calculation of REC\u0027s linear index from RmiRecMpidr\ntype which has [7:4] SBZ.\n\nChange-Id: I9ab3d94f25b263b2672012ccbd6e632265a2a745\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "5467cb50ac44eb4d3248c0cf70eaf1fd6a034c8b", "tree": "1e35ba50c44808b5b946e98fd32aa02c4723b7b3", "parents": [ "19cfac8b0cbbc1dfffc58f28a4cacb925eb4c8c9" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Oct 02 18:21:43 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 07:14:34 2024 +0200" }, "message": "fix(realm): cater for removal of SH from rtte\n\nThe RMM v1.0 REL specification removes the SH field from host_controlled\nparameters. Fix up TFTF for this change.\n\nChange-Id: Id032d4555da4b200bb9a355085b8a7f0709884fb\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\n" }, { "commit": "19cfac8b0cbbc1dfffc58f28a4cacb925eb4c8c9", "tree": "0ac8d741cacb43841f8d2a4263bb9b03ed1624c3", "parents": [ "9a60ecbf209d2faf117420b9013c52216106d157" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Aug 30 16:36:42 2024 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 01 16:55:17 2024 +0100" }, "message": "feat(realm): set number of num_bps and num_wps\n\nAs per RMM Specification number of breakpoints and\nwatchpoints passed to RMI_REALM_CREATE cannot be 0.\nThese values are passed to host_prepare_realm_payload()\nin feature_flag parameter fields which are set to 0\nby default by callers to this function.\nThis patch modifies the logic for setting num_bps\nand num_wps Realm parameters to avoid 0 values.\n\nChange-Id: Ib5420db959866620005c404c494c4ec1904b010c\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\n" } ], "next": "3a137fc469a3241cfda137975dd8c9805331023b" }