blob: d194fabaf4009d9103e0a448f2d872839219397a [file] [log] [blame]
Madhukar Pappireddy3ca23422024-07-05 16:26:12 -05001<?xml version="1.0" encoding="utf-8"?>
2
3<!--
4 Copyright (c) 2024, Arm Limited. All rights reserved.
5
6 SPDX-License-Identifier: BSD-3-Clause
7-->
8
9<testsuites>
10
11 <testsuite name="SIMD,SVE Registers context"
12 description="Validate context switch between NWd and SWd" >
13 <testcase name="Check that SIMD registers context is preserved"
14 function="test_simd_vectors_preserved" />
15 <testcase name="Check that SVE registers context is preserved"
16 function="test_sve_vectors_preserved" />
17 <testcase name="Check that SVE operations in NWd are unaffected by SWd"
18 function="test_sve_vectors_operations" />
19 <testcase name="Enter SPMC with SME SSVE enabled"
20 function="test_sme_streaming_sve" />
21 <testcase name="Enter SPMC with SME ZA enabled"
22 function="test_sme_za" />
23 <testcase name="Enter SPMC with SME SM+ZA enabled"
24 function="test_sme_streaming_sve_za" />
25 </testsuite>
26
27</testsuites>