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Varun Wadekar91535cd2020-03-12 14:32:44 -07001/*
2 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <debug.h>
8#include <drivers/console.h>
9#include <drivers/arm/gic_common.h>
10#include <drivers/arm/gic_v2.h>
11#include <platform.h>
12#include <platform_def.h>
13
14#include <xlat_tables_v2.h>
15
16/*
Varun Wadekar8dcb7372020-03-26 16:17:01 -070017 * Memory map
Varun Wadekar91535cd2020-03-12 14:32:44 -070018 */
19static const mmap_region_t tegra194_mmap[] = {
anzhou113d2d22020-06-04 13:20:18 +080020 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x2000, /* 8KB */
Varun Wadekar96b6cd22020-03-16 17:40:59 -070021 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080022 MAP_REGION_FLAT(TEGRA_TMR0_BASE, 0x1000, /* 4KB */
Varun Wadekar8dcb7372020-03-26 16:17:01 -070023 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080024 MAP_REGION_FLAT(TEGRA_WDT0_BASE, 0x1000, /* 4KB */
Varun Wadekar8dcb7372020-03-26 16:17:01 -070025 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080026 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
Varun Wadekar91535cd2020-03-12 14:32:44 -070027 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080028 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
Varun Wadekar91535cd2020-03-12 14:32:44 -070029 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080030 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB */
Varun Wadekar91535cd2020-03-12 14:32:44 -070031 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080032 MAP_REGION_FLAT(TEGRA_RTC_BASE, 0x1000, /* 4KB */
Varun Wadekar91535cd2020-03-12 14:32:44 -070033 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080034 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000, /* 4KB */
Varun Wadekar91535cd2020-03-12 14:32:44 -070035 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080036 MAP_REGION_FLAT(TEGRA_AOWAKE_BASE, 0x1000, /* 4KB */
Varun Wadekara2874422020-03-16 17:43:20 -070037 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080038 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000, /* 4KB */
Varun Wadekar96b6cd22020-03-16 17:40:59 -070039 MT_DEVICE | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080040 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000, /* 4KB */
Varun Wadekarfa6a2d22020-03-20 22:41:32 -070041 MT_DEVICE | MT_RW | MT_NS),
Varun Wadekar91535cd2020-03-12 14:32:44 -070042 MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE,
43 MT_MEMORY | MT_RW | MT_NS),
anzhou113d2d22020-06-04 13:20:18 +080044 MAP_REGION_FLAT(TEGRA_SMMU_CTX_BASE, 0x1000, /* 4KB */
Varun Wadekarfa6a2d22020-03-20 22:41:32 -070045 MT_MEMORY | MT_RW | MT_NS),
Varun Wadekar91535cd2020-03-12 14:32:44 -070046 {0}
47};
48
49const mmap_region_t *tftf_platform_get_mmap(void)
50{
51 return tegra194_mmap;
52}
53
54void tftf_plat_arch_setup(void)
55{
56 tftf_plat_configure_mmu();
57}
58
59void tftf_early_platform_setup(void)
60{
61 /* Tegra194 platforms use UARTC as the console */
anzhou113d2d22020-06-04 13:20:18 +080062 console_init(TEGRA_UARTC_BASE, TEGRA_CONSOLE_CLKRATE,
63 TEGRA_CONSOLE_BAUDRATE);
Varun Wadekar91535cd2020-03-12 14:32:44 -070064}
65
66void tftf_platform_setup(void)
67{
anzhou113d2d22020-06-04 13:20:18 +080068 gicv2_init(TEGRA_GICC_BASE, TEGRA_GICD_BASE);
Varun Wadekar91535cd2020-03-12 14:32:44 -070069 gicv2_setup_distif();
70 gicv2_probe_gic_cpu_id();
71 gicv2_setup_cpuif();
Varun Wadekar96b6cd22020-03-16 17:40:59 -070072
73 /* Setup power management dependencies */
anzhou113d2d22020-06-04 13:20:18 +080074 tegra_pwr_mgmt_setup();
Varun Wadekara2874422020-03-16 17:43:20 -070075
76 /* Configure system suspend wake sources */
anzhou113d2d22020-06-04 13:20:18 +080077 tegra_set_rtc_as_wakeup_source();
Varun Wadekar91535cd2020-03-12 14:32:44 -070078}