Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <debug.h> |
| 8 | #include <drivers/console.h> |
| 9 | #include <drivers/arm/gic_common.h> |
| 10 | #include <drivers/arm/gic_v2.h> |
| 11 | #include <platform.h> |
| 12 | #include <platform_def.h> |
| 13 | |
| 14 | #include <xlat_tables_v2.h> |
| 15 | |
| 16 | /* |
Varun Wadekar | 8dcb737 | 2020-03-26 16:17:01 -0700 | [diff] [blame] | 17 | * Memory map |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 18 | */ |
| 19 | static const mmap_region_t tegra194_mmap[] = { |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 20 | MAP_REGION_FLAT(TEGRA_MC_BASE, 0x2000, /* 8KB */ |
Varun Wadekar | 96b6cd2 | 2020-03-16 17:40:59 -0700 | [diff] [blame] | 21 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 22 | MAP_REGION_FLAT(TEGRA_TMR0_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | 8dcb737 | 2020-03-26 16:17:01 -0700 | [diff] [blame] | 23 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 24 | MAP_REGION_FLAT(TEGRA_WDT0_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | 8dcb737 | 2020-03-26 16:17:01 -0700 | [diff] [blame] | 25 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 26 | MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 27 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 28 | MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 29 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 30 | MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB */ |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 31 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 32 | MAP_REGION_FLAT(TEGRA_RTC_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 33 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 34 | MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 35 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 36 | MAP_REGION_FLAT(TEGRA_AOWAKE_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | a287442 | 2020-03-16 17:43:20 -0700 | [diff] [blame] | 37 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 38 | MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | 96b6cd2 | 2020-03-16 17:40:59 -0700 | [diff] [blame] | 39 | MT_DEVICE | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 40 | MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | fa6a2d2 | 2020-03-20 22:41:32 -0700 | [diff] [blame] | 41 | MT_DEVICE | MT_RW | MT_NS), |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 42 | MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE, |
| 43 | MT_MEMORY | MT_RW | MT_NS), |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 44 | MAP_REGION_FLAT(TEGRA_SMMU_CTX_BASE, 0x1000, /* 4KB */ |
Varun Wadekar | fa6a2d2 | 2020-03-20 22:41:32 -0700 | [diff] [blame] | 45 | MT_MEMORY | MT_RW | MT_NS), |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 46 | {0} |
| 47 | }; |
| 48 | |
| 49 | const mmap_region_t *tftf_platform_get_mmap(void) |
| 50 | { |
| 51 | return tegra194_mmap; |
| 52 | } |
| 53 | |
| 54 | void tftf_plat_arch_setup(void) |
| 55 | { |
| 56 | tftf_plat_configure_mmu(); |
| 57 | } |
| 58 | |
| 59 | void tftf_early_platform_setup(void) |
| 60 | { |
| 61 | /* Tegra194 platforms use UARTC as the console */ |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 62 | console_init(TEGRA_UARTC_BASE, TEGRA_CONSOLE_CLKRATE, |
| 63 | TEGRA_CONSOLE_BAUDRATE); |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | void tftf_platform_setup(void) |
| 67 | { |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 68 | gicv2_init(TEGRA_GICC_BASE, TEGRA_GICD_BASE); |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 69 | gicv2_setup_distif(); |
| 70 | gicv2_probe_gic_cpu_id(); |
| 71 | gicv2_setup_cpuif(); |
Varun Wadekar | 96b6cd2 | 2020-03-16 17:40:59 -0700 | [diff] [blame] | 72 | |
| 73 | /* Setup power management dependencies */ |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 74 | tegra_pwr_mgmt_setup(); |
Varun Wadekar | a287442 | 2020-03-16 17:43:20 -0700 | [diff] [blame] | 75 | |
| 76 | /* Configure system suspend wake sources */ |
anzhou | 113d2d2 | 2020-06-04 13:20:18 +0800 | [diff] [blame] | 77 | tegra_set_rtc_as_wakeup_source(); |
Varun Wadekar | 91535cd | 2020-03-12 14:32:44 -0700 | [diff] [blame] | 78 | } |