Blame - tftf/framework/aarch64/exceptions.S - TF-A/tf-a-tests.git

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Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	1	/*
				2	* Copyright (c) 2018, Arm Limited. All rights reserved.
				3	*
				4	* SPDX-License-Identifier: BSD-3-Clause
				5	*/
				6
				7	#include <asm_macros.S>
				8
				9	.globl tftf_vector
				10
Sandrine Bailleux	e760449	2019-01-14 09:37:28 +0100	[diff] [blame^]	11	/* Exception vector code for unhandled exceptions. Loops forever. */
				12	.macro unhandled_exception name
				13	vector_entry \name
				14	b \name
				15	end_vector_entry \name
				16	.endm
				17
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	18	vector_base tftf_vector
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	19
				20	/*
				21	* Current EL with SP0 : 0x0 - 0x200.
				22	*/
Sandrine Bailleux	e760449	2019-01-14 09:37:28 +0100	[diff] [blame^]	23	unhandled_exception SynchronousExceptionSP0
				24	unhandled_exception IrqSP0
				25	unhandled_exception FiqSP0
				26	unhandled_exception SErrorSP0
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	27
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	28	/*
				29	* Current EL with SPx : 0x200 - 0x400.
				30	*/
Sandrine Bailleux	e760449	2019-01-14 09:37:28 +0100	[diff] [blame^]	31	unhandled_exception SynchronousExceptionSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	32
				33	vector_entry IrqSPx
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame]	34	b irq_vector_entry
Sandrine Bailleux	452f360	2019-01-14 13:49:22 +0100	[diff] [blame]	35	end_vector_entry IrqSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	36
Sandrine Bailleux	e760449	2019-01-14 09:37:28 +0100	[diff] [blame^]	37	unhandled_exception FiqSPx
				38	unhandled_exception SErrorSPx
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	39
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	40	/*
				41	* Lower EL using AArch64 : 0x400 - 0x600.
				42	*/
Sandrine Bailleux	e760449	2019-01-14 09:37:28 +0100	[diff] [blame^]	43	unhandled_exception SynchronousExceptionA64
				44	unhandled_exception IrqA64
				45	unhandled_exception FiqA64
				46	unhandled_exception SErrorA64
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	47
Sandrine Bailleux	8b170a2	2019-01-11 18:47:26 +0100	[diff] [blame]	48	/*
				49	* Lower EL using AArch32 : 0x600 - 0x800.
				50	*/
Sandrine Bailleux	e760449	2019-01-14 09:37:28 +0100	[diff] [blame^]	51	unhandled_exception SynchronousExceptionA32
				52	unhandled_exception IrqA32
				53	unhandled_exception FiqA32
				54	unhandled_exception SErrorA32
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	55
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame]	56	/*
				57	* Exceptions will always be from the same exception level so no need to save
				58	* and restore SPSR.
				59	*/
				60	.macro save_gp_regs
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	61	stp x0, x1, [sp, #0x0]
				62	stp x2, x3, [sp, #0x10]
				63	stp x4, x5, [sp, #0x20]
				64	stp x6, x7, [sp, #0x30]
				65	stp x8, x9, [sp, #0x40]
				66	stp x10, x11, [sp, #0x50]
				67	stp x12, x13, [sp, #0x60]
				68	stp x14, x15, [sp, #0x70]
				69	stp x16, x17, [sp, #0x80]
				70	stp x18, x19, [sp, #0x90]
				71	stp x20, x21, [sp, #0xa0]
				72	stp x22, x23, [sp, #0xb0]
				73	stp x24, x25, [sp, #0xc0]
				74	stp x26, x27, [sp, #0xd0]
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame]	75	stp x28, x29, [sp, #0xe0]
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	76	mrs x0, sp_el0
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame]	77	stp x30, x0, [sp, #0xf0]
				78	.endm
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	79
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame]	80	.macro restore_gp_regs
				81	ldp x30, x0, [sp, #0xf0]
				82	msr sp_el0, x0
				83	ldp x28, x29, [sp, #0xe0]
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	84	ldp x26, x27, [sp, #0xd0]
				85	ldp x24, x25, [sp, #0xc0]
				86	ldp x22, x23, [sp, #0xb0]
				87	ldp x20, x21, [sp, #0xa0]
				88	ldp x18, x19, [sp, #0x90]
				89	ldp x16, x17, [sp, #0x80]
				90	ldp x14, x15, [sp, #0x70]
				91	ldp x12, x13, [sp, #0x60]
				92	ldp x10, x11, [sp, #0x50]
				93	ldp x8, x9, [sp, #0x40]
				94	ldp x6, x7, [sp, #0x30]
				95	ldp x4, x5, [sp, #0x20]
				96	ldp x2, x3, [sp, #0x10]
				97	ldp x0, x1, [sp, #0x0]
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame]	98	.endm
				99
				100	func irq_vector_entry
				101	sub sp, sp, #0x100
				102	save_gp_regs
				103	bl tftf_irq_handler_dispatcher
				104	restore_gp_regs
Sandrine Bailleux	3cd87d7	2018-10-09 11:12:55 +0200	[diff] [blame]	105	add sp, sp, #0x100
Sandrine Bailleux	d101967	2019-01-11 18:39:24 +0100	[diff] [blame]	106	eret
				107	endfunc irq_vector_entry