| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <tftf.h> |
| 10 | |
| 11 | .globl tftf_entrypoint |
| 12 | .globl tftf_hotplug_entry |
| 13 | |
| 14 | |
| 15 | /* ---------------------------------------------------------------------------- |
| 16 | * Cold boot entry point for the primary CPU. |
| 17 | * ---------------------------------------------------------------------------- |
| 18 | */ |
| 19 | func tftf_entrypoint |
| 20 | /* -------------------------------------------------------------------- |
| 21 | * Set the exception vectors |
| 22 | * -------------------------------------------------------------------- |
| 23 | */ |
| 24 | adr x0, tftf_vector |
| 25 | asm_write_vbar_el1_or_el2 x1 |
| 26 | |
| 27 | /* -------------------------------------------------------------------- |
| 28 | * Enable the instruction cache, stack pointer and data access |
| 29 | * alignment checks |
| 30 | * -------------------------------------------------------------------- |
| 31 | */ |
| 32 | mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) |
| 33 | asm_read_sctlr_el1_or_el2 |
| 34 | orr x0, x0, x1 |
| 35 | asm_write_sctlr_el1_or_el2 x1 |
| 36 | isb |
| 37 | |
| 38 | /* -------------------------------------------------------------------- |
| 39 | * This code is expected to be executed only by the primary CPU. |
| 40 | * Save the mpid for the first core that executes and if a secondary |
| 41 | * CPU has lost its way make it spin forever. |
| 42 | * -------------------------------------------------------------------- |
| 43 | */ |
| 44 | bl save_primary_mpid |
| 45 | |
| 46 | /* -------------------------------------------------------------------- |
| 47 | * Zero out NOBITS sections. There are 2 of them: |
| 48 | * - the .bss section; |
| 49 | * - the coherent memory section. |
| 50 | * -------------------------------------------------------------------- |
| 51 | */ |
| 52 | ldr x0, =__BSS_START__ |
| 53 | ldr x1, =__BSS_SIZE__ |
| 54 | bl zeromem16 |
| 55 | |
| 56 | ldr x0, =__COHERENT_RAM_START__ |
| 57 | ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ |
| 58 | bl zeromem16 |
| 59 | |
| 60 | /* -------------------------------------------------------------------- |
| 61 | * Give ourselves a small coherent stack to ease the pain of |
| 62 | * initializing the MMU |
| 63 | * -------------------------------------------------------------------- |
| 64 | */ |
| 65 | mrs x0, mpidr_el1 |
| 66 | bl platform_set_coherent_stack |
| 67 | |
| 68 | bl tftf_early_platform_setup |
| 69 | bl tftf_plat_arch_setup |
| 70 | |
| 71 | /* -------------------------------------------------------------------- |
| 72 | * Give ourselves a stack allocated in Normal -IS-WBWA memory |
| 73 | * -------------------------------------------------------------------- |
| 74 | */ |
| 75 | mrs x0, mpidr_el1 |
| 76 | bl platform_set_stack |
| 77 | |
| 78 | /* -------------------------------------------------------------------- |
| 79 | * tftf_cold_boot_main() will perform the remaining architectural and |
| 80 | * platform setup, initialise the test framework's state, then run the |
| 81 | * tests. |
| 82 | * -------------------------------------------------------------------- |
| 83 | */ |
| 84 | b tftf_cold_boot_main |
| 85 | |
| 86 | dead: |
| 87 | b dead |
| 88 | endfunc tftf_entrypoint |
| 89 | |
| 90 | /* ---------------------------------------------------------------------------- |
| 91 | * Entry point for a CPU that has just been powered up. |
| 92 | * In : x0 - context_id |
| 93 | * ---------------------------------------------------------------------------- |
| 94 | */ |
| 95 | func tftf_hotplug_entry |
| 96 | |
| 97 | /* -------------------------------------------------------------------- |
| 98 | * Preserve the context_id in a callee-saved register |
| 99 | * -------------------------------------------------------------------- |
| 100 | */ |
| 101 | mov x19, x0 |
| 102 | |
| 103 | /* -------------------------------------------------------------------- |
| 104 | * Set the exception vectors |
| 105 | * -------------------------------------------------------------------- |
| 106 | */ |
| 107 | adr x0, tftf_vector |
| 108 | asm_write_vbar_el1_or_el2 x1 |
| 109 | |
| 110 | /* -------------------------------------------------------------------- |
| 111 | * Enable the instruction cache, stack pointer and data access |
| 112 | * alignment checks |
| 113 | * -------------------------------------------------------------------- |
| 114 | */ |
| 115 | mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) |
| 116 | asm_read_sctlr_el1_or_el2 |
| 117 | orr x0, x0, x1 |
| 118 | asm_write_sctlr_el1_or_el2 x1 |
| 119 | isb |
| 120 | |
| 121 | /* -------------------------------------------------------------------- |
| 122 | * Give ourselves a small coherent stack to ease the pain of |
| 123 | * initializing the MMU |
| 124 | * -------------------------------------------------------------------- |
| 125 | */ |
| 126 | mrs x0, mpidr_el1 |
| 127 | bl platform_set_coherent_stack |
| 128 | |
| 129 | /* -------------------------------------------------------------------- |
| 130 | * Enable the MMU |
| 131 | * -------------------------------------------------------------------- |
| 132 | */ |
| 133 | bl tftf_plat_enable_mmu |
| 134 | |
| 135 | /* -------------------------------------------------------------------- |
| 136 | * Give ourselves a stack in normal memory. |
| 137 | * -------------------------------------------------------------------- |
| 138 | */ |
| 139 | mrs x0, mpidr_el1 |
| 140 | bl platform_set_stack |
| 141 | |
| 142 | /* -------------------------------------------------------------------- |
| 143 | * Save the context_id for later retrieval by tests |
| 144 | * -------------------------------------------------------------------- |
| 145 | */ |
| 146 | mrs x0, mpidr_el1 |
| 147 | and x0, x0, #MPID_MASK |
| 148 | bl platform_get_core_pos |
| 149 | |
| 150 | mov x1, x19 |
| 151 | |
| 152 | bl tftf_set_cpu_on_ctx_id |
| 153 | |
| 154 | /* -------------------------------------------------------------------- |
| 155 | * Jump to warm boot main function |
| 156 | * -------------------------------------------------------------------- |
| 157 | */ |
| 158 | b tftf_warm_boot_main |
| 159 | endfunc tftf_hotplug_entry |
| 160 | |
| 161 | /* ---------------------------------------------------------------------------- |
| 162 | * Saves the mpid of the primary core and if the primary core |
| 163 | * is already saved then it loops infinitely. |
| 164 | * ---------------------------------------------------------------------------- |
| 165 | */ |
| 166 | func save_primary_mpid |
| 167 | adrp x1, tftf_primary_core |
| 168 | ldr w0, [x1, :lo12:tftf_primary_core] |
| 169 | mov w2, #INVALID_MPID |
| 170 | cmp w0, w2 |
| 171 | b.ne panic |
| 172 | mov x2, #MPID_MASK |
| 173 | mrs x0, mpidr_el1 |
| 174 | and x0, x0, x2 |
| 175 | str w0, [x1, :lo12:tftf_primary_core] |
| 176 | ret |
| 177 | panic: |
| 178 | /* Primary core MPID already saved */ |
| 179 | b . |
| 180 | ret |
| 181 | endfunc save_primary_mpid |