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review.trustedfirmware.org / TF-A / tf-a-tests.git / a1497e32ae63fcf138b41bc96721a30751df4104 / . / tftf / framework / aarch64 / entrypoint.S
blob: 34ba90f5ffe92d347db92d031ac6e11ab2f9dcee [file] [log] [blame]
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]1/*
2 * Copyright (c) 2018, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <tftf.h>
10
11 .globl tftf_entrypoint
12 .globl tftf_hotplug_entry
13
14
15/* ----------------------------------------------------------------------------
16 * Cold boot entry point for the primary CPU.
17 * ----------------------------------------------------------------------------
18 */
19func tftf_entrypoint
20 /* --------------------------------------------------------------------
21 * Set the exception vectors
22 * --------------------------------------------------------------------
23 */
24 adr x0, tftf_vector
25 asm_write_vbar_el1_or_el2 x1
26
27 /* --------------------------------------------------------------------
Sandrine Bailleuxaef556a2018-10-25 12:47:55 +0200[diff] [blame]28 * Enable the instruction cache and stack pointer alignment checks.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]29 * --------------------------------------------------------------------
30 */
Sandrine Bailleuxaef556a2018-10-25 12:47:55 +0200[diff] [blame]31 mov x1, #(SCTLR_I_BIT | SCTLR_SA_BIT)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]32 asm_read_sctlr_el1_or_el2
33 orr x0, x0, x1
34 asm_write_sctlr_el1_or_el2 x1
35 isb
36
37 /* --------------------------------------------------------------------
38 * This code is expected to be executed only by the primary CPU.
39 * Save the mpid for the first core that executes and if a secondary
40 * CPU has lost its way make it spin forever.
41 * --------------------------------------------------------------------
42 */
43 bl save_primary_mpid
44
45 /* --------------------------------------------------------------------
46 * Zero out NOBITS sections. There are 2 of them:
47 * - the .bss section;
48 * - the coherent memory section.
49 * --------------------------------------------------------------------
50 */
51 ldr x0, =__BSS_START__
52 ldr x1, =__BSS_SIZE__
53 bl zeromem16
54
55 ldr x0, =__COHERENT_RAM_START__
56 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
57 bl zeromem16
58
59 /* --------------------------------------------------------------------
60 * Give ourselves a small coherent stack to ease the pain of
61 * initializing the MMU
62 * --------------------------------------------------------------------
63 */
64 mrs x0, mpidr_el1
65 bl platform_set_coherent_stack
66
67 bl tftf_early_platform_setup
68 bl tftf_plat_arch_setup
69
70 /* --------------------------------------------------------------------
71 * Give ourselves a stack allocated in Normal -IS-WBWA memory
72 * --------------------------------------------------------------------
73 */
74 mrs x0, mpidr_el1
75 bl platform_set_stack
76
77 /* --------------------------------------------------------------------
78 * tftf_cold_boot_main() will perform the remaining architectural and
79 * platform setup, initialise the test framework's state, then run the
80 * tests.
81 * --------------------------------------------------------------------
82 */
83 b tftf_cold_boot_main
84
85dead:
86 b dead
87endfunc tftf_entrypoint
88
89/* ----------------------------------------------------------------------------
90 * Entry point for a CPU that has just been powered up.
91 * In : x0 - context_id
92 * ----------------------------------------------------------------------------
93 */
94func tftf_hotplug_entry
95
96 /* --------------------------------------------------------------------
97 * Preserve the context_id in a callee-saved register
98 * --------------------------------------------------------------------
99 */
100 mov x19, x0
101
102 /* --------------------------------------------------------------------
103 * Set the exception vectors
104 * --------------------------------------------------------------------
105 */
106 adr x0, tftf_vector
107 asm_write_vbar_el1_or_el2 x1
108
109 /* --------------------------------------------------------------------
Sandrine Bailleuxaef556a2018-10-25 12:47:55 +0200[diff] [blame]110 * Enable the instruction cache and stack pointer alignment checks.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]111 * --------------------------------------------------------------------
112 */
Sandrine Bailleuxaef556a2018-10-25 12:47:55 +0200[diff] [blame]113 mov x1, #(SCTLR_I_BIT | SCTLR_SA_BIT)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]114 asm_read_sctlr_el1_or_el2
115 orr x0, x0, x1
116 asm_write_sctlr_el1_or_el2 x1
117 isb
118
119 /* --------------------------------------------------------------------
120 * Give ourselves a small coherent stack to ease the pain of
121 * initializing the MMU
122 * --------------------------------------------------------------------
123 */
124 mrs x0, mpidr_el1
125 bl platform_set_coherent_stack
126
127 /* --------------------------------------------------------------------
128 * Enable the MMU
129 * --------------------------------------------------------------------
130 */
131 bl tftf_plat_enable_mmu
132
133 /* --------------------------------------------------------------------
134 * Give ourselves a stack in normal memory.
135 * --------------------------------------------------------------------
136 */
137 mrs x0, mpidr_el1
138 bl platform_set_stack
139
140 /* --------------------------------------------------------------------
141 * Save the context_id for later retrieval by tests
142 * --------------------------------------------------------------------
143 */
144 mrs x0, mpidr_el1
Antonio Nino Diaz8c0f86b2018-11-23 13:50:59 +0000[diff] [blame]145 mov_imm x1, MPID_MASK
146 and x0, x0, x1
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]147 bl platform_get_core_pos
148
149 mov x1, x19
150
151 bl tftf_set_cpu_on_ctx_id
152
153 /* --------------------------------------------------------------------
154 * Jump to warm boot main function
155 * --------------------------------------------------------------------
156 */
157 b tftf_warm_boot_main
158endfunc tftf_hotplug_entry
159
160/* ----------------------------------------------------------------------------
161 * Saves the mpid of the primary core and if the primary core
162 * is already saved then it loops infinitely.
163 * ----------------------------------------------------------------------------
164 */
165func save_primary_mpid
166 adrp x1, tftf_primary_core
167 ldr w0, [x1, :lo12:tftf_primary_core]
168 mov w2, #INVALID_MPID
169 cmp w0, w2
170 b.ne panic
Antonio Nino Diaz8c0f86b2018-11-23 13:50:59 +0000[diff] [blame]171 mov_imm x2, MPID_MASK
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]172 mrs x0, mpidr_el1
173 and x0, x0, x2
174 str w0, [x1, :lo12:tftf_primary_core]
175 ret
176panic:
177 /* Primary core MPID already saved */
178 b .
179 ret
180endfunc save_primary_mpid