| Ruari Phipps | 9f1952c | 2020-08-24 11:32:32 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | |
| 10 | /* ----------------------------------------------------------------------------- |
| 11 | * Very simple stackless exception handlers used by the spm shim layer. |
| 12 | * ----------------------------------------------------------------------------- |
| 13 | */ |
| 14 | .globl spm_shim_exceptions_ptr |
| 15 | |
| 16 | vector_base spm_shim_exceptions_ptr |
| 17 | |
| 18 | /* ----------------------------------------------------- |
| 19 | * Current EL with SP0 : 0x0 - 0x200 |
| 20 | * ----------------------------------------------------- |
| 21 | */ |
| 22 | vector_entry_spin sync_exception_sp_el0 |
| 23 | |
| 24 | vector_entry_spin irq_sp_el0 |
| 25 | |
| 26 | vector_entry_spin fiq_ep_el0 |
| 27 | |
| 28 | vector_entry_spin serror_ep_el0 |
| 29 | |
| 30 | /* ----------------------------------------------------- |
| 31 | * Current EL with SPx: 0x200 - 0x400 |
| 32 | * ----------------------------------------------------- |
| 33 | */ |
| 34 | vector_entry_spin sync_exception_sp_elx |
| 35 | |
| 36 | vector_entry_spin irq_sp_elx |
| 37 | |
| 38 | vector_entry_spin fiq_sp_elx |
| 39 | |
| 40 | vector_entry_spin serror_sp_elx |
| 41 | |
| 42 | /* ----------------------------------------------------- |
| 43 | * Lower EL using AArch64 : 0x400 - 0x600. No exceptions |
| 44 | * are handled since secure_partition does not implement |
| 45 | * a lower EL |
| 46 | * ----------------------------------------------------- |
| 47 | */ |
| 48 | vector_entry sync_exception_aarch64 |
| 49 | msr tpidr_el1, x30 |
| 50 | mrs x30, esr_el1 |
| 51 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 52 | |
| 53 | cmp x30, #EC_AARCH64_SVC |
| 54 | b.eq do_smc |
| 55 | |
| 56 | cmp x30, #EC_AARCH32_SVC |
| 57 | b.eq do_smc |
| 58 | |
| 59 | cmp x30, #EC_AARCH64_SYS |
| 60 | b.eq handle_sys_trap |
| 61 | |
| 62 | /* Fail in all the other cases */ |
| 63 | b panic |
| 64 | |
| 65 | /* --------------------------------------------- |
| 66 | * Tell SPM that we are done initialising |
| 67 | * --------------------------------------------- |
| 68 | */ |
| 69 | do_smc: |
| 70 | mrs x30, tpidr_el1 |
| 71 | smc #0 |
| 72 | eret |
| 73 | |
| 74 | /* AArch64 system instructions trap are handled as a panic for now */ |
| 75 | handle_sys_trap: |
| 76 | panic: |
| 77 | b panic |
| 78 | end_vector_entry sync_exception_aarch64 |
| 79 | |
| 80 | vector_entry_spin irq_aarch64 |
| 81 | |
| 82 | vector_entry_spin fiq_aarch64 |
| 83 | |
| 84 | vector_entry_spin serror_aarch64 |
| 85 | |
| 86 | /* ----------------------------------------------------- |
| 87 | * Lower EL using AArch32 : 0x600 - 0x800 |
| 88 | * ----------------------------------------------------- |
| 89 | */ |
| 90 | vector_entry_spin sync_exception_aarch32 |
| 91 | |
| 92 | vector_entry_spin irq_aarch32 |
| 93 | |
| 94 | vector_entry_spin fiq_aarch32 |
| 95 | |
| 96 | vector_entry_spin serror_aarch32 |