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Maheedhar Bollapalli7dbb6c12024-10-04 03:22:30 +00001/*
2 * Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#include <arch.h>
11
12#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
13#define PLATFORM_LINKER_ARCH aarch64
14
15#define TFTF_BASE U(0x8000000)
16
17#define CACHE_WRITEBACK_GRANULE U(0x40)
18
19#define PLATFORM_CLUSTER_COUNT U(4)
20#define PLATFORM_CORE_COUNT_PER_CLUSTER U(2)
21#define PLATFORM_MAX_PE_PER_CPU U(1)
22/* Because of make_mpid from include/lib/tftf_lib.h */
23#define PLAT_MAX_PE_PER_CPU PLATFORM_MAX_PE_PER_CPU
24
25#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
26 PLATFORM_CORE_COUNT_PER_CLUSTER)
27#define PLATFORM_NUM_AFFS (PLATFORM_CORE_COUNT + \
28 PLATFORM_CLUSTER_COUNT + 1)
29#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
30#define PLAT_MAX_PWR_LEVEL MPIDR_AFFLVL2
31#define PLAT_MAX_PWR_STATES_PER_LVL U(2)
32
33
34#define PLATFORM_STACK_SIZE U(0x440)
35#define PCPU_DV_MEM_STACK_SIZE U(0x440)
36
37
38#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
39#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
40#define MAX_XLAT_TABLES U(8)
41#define MAX_MMAP_REGIONS U(16)
42
43#define DRAM_BASE U(0x0)
44#define DRAM_SIZE U(0x80000000)
45
46/*
47 * TFTF_NVM_OFFSET/SIZE correspond to the NVM partition in the partition
48 * table
49 */
50#define TFTF_NVM_SIZE U(0x600000)
51#define TFTF_NVM_OFFSET U(0x20000000)
52
53/* Local state bit width for each level in the state-ID field of power state */
54#define PLAT_LOCAL_PSTATE_WIDTH U(4)
55
56/* GIC related addresses from datasheet */
57#define GICD_REG_BASE U(0xe2000000)
58#define GICR_REG_BASE U(0xe2060000)
59
60/* GICv3 is used, dummy definition to resolve build failure */
61#define GICC_REG_BASE U(0xe2000000)
62
63/*
64 * Memory mapped devices that we must create MMU mappings for them
65 */
66#define GIC_BASE GICD_REG_BASE
67#define GIC_SIZE U(0x01000000)
68
69#define TTC_BASE U(0xF1E70000)
70#define TTC_SIZE U(0x00010000)
71
72#define SYS_CNT_BASE1 TTC_BASE
73#define SYS_CNT_SIZE TTC_SIZE
74
75#define LPD_IOU_SLCR U(0xEB410000)
76#define LPD_IOU_SLCR_SIZE U(0x00010000)
77
78/* ARM PL011 UART */
79#define PL011_UART0_BASE U(0xf1920000)
80#define PL011_BAUDRATE U(115200)
81#define PL011_UART_CLK_IN_HZ U(100000000)
82
83#define PLAT_ARM_UART_BASE PL011_UART0_BASE
84#define PLAT_ARM_UART_SIZE U(0x1000)
85
86#define CRASH_CONSOLE_BASE PL011_UART0_BASE
87#define CRASH_CONSOLE_SIZE PLAT_ARM_UART_SIZE
88
89/*******************************************************************************
90 * Non-Secure Software Generated Interrupts IDs
91 ******************************************************************************/
92#define IRQ_NS_SGI_0 0
93#define IRQ_NS_SGI_1 1
94#define IRQ_NS_SGI_2 2
95#define IRQ_NS_SGI_3 3
96#define IRQ_NS_SGI_4 4
97#define IRQ_NS_SGI_5 5
98#define IRQ_NS_SGI_6 6
99#define IRQ_NS_SGI_7 7
100
101/* Per-CPU Hypervisor Timer Interrupt ID */
102#define IRQ_PCPU_HP_TIMER U(29)
103/* Datasheet: TIME00 event*/
104#define IRQ_CNTPSIRQ1 U(29)
105
106/* Refer to AM011(v1.5), Chapter 50, Page 430 */
107#define PLAT_MAX_SPI_OFFSET_ID U(223)
108
109/*
110 * Times(in ms) used by test code for completion of different events.
111 */
112#define PLAT_SUSPEND_ENTRY_TIME U(15)
113#define PLAT_SUSPEND_ENTRY_EXIT_TIME U(30)
114
115/*
116 * Dummy definitions that we need just to compile...
117 */
118#define ARM_SECURE_SERVICE_BUFFER_BASE U(0)
119#define ARM_SECURE_SERVICE_BUFFER_SIZE U(100)
120
121/* LPD_SWDT_INT, AM011(v1.5), Chapter 50, Page 428 */
122#define IRQ_TWDOG_INTID U(0x51)
123
124#define TTC_TIMER_IRQ U(75)
Maheedhar Bollapallif675feb2024-11-13 11:37:30 +0000125#define TTC_CLK_SEL_OFFSET U(0x360)
Maheedhar Bollapalli7dbb6c12024-10-04 03:22:30 +0000126
127#endif /* PLATFORM_DEF_H */