| Amit Nagal | 7c9f2fc | 2024-02-08 16:35:08 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <utils_def.h> |
| 9 | |
| 10 | #ifndef __PLATFORM_DEF_H__ |
| 11 | #define __PLATFORM_DEF_H__ |
| 12 | |
| 13 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 14 | #define PLATFORM_LINKER_ARCH aarch64 |
| 15 | |
| 16 | #define TFTF_BASE U(0x8000000) |
| 17 | |
| 18 | #define DRAM_BASE 0x0 |
| 19 | #define DRAM_SIZE 0x80000000 |
| 20 | |
| 21 | #define PLATFORM_CLUSTER_COUNT U(1) |
| 22 | #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 |
| 23 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ |
| 24 | PLATFORM_CORE_COUNT_PER_CLUSTER) |
| 25 | #define PLATFORM_CORES_PER_CLUSTER PLATFORM_CORE_COUNT_PER_CLUSTER |
| 26 | |
| 27 | #define PLATFORM_NUM_AFFS (PLATFORM_CORE_COUNT + \ |
| 28 | PLATFORM_CLUSTER_COUNT + 1) |
| 29 | |
| 30 | #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 |
| 31 | #define PLAT_MAX_PWR_LEVEL MPIDR_AFFLVL2 |
| 32 | |
| 33 | #define PLAT_MAX_PWR_STATES_PER_LVL 2 |
| 34 | |
| 35 | #define PLATFORM_STACK_SIZE 0x440 |
| 36 | #define PCPU_DV_MEM_STACK_SIZE 0x100 |
| 37 | |
| 38 | #define TFTF_NVM_SIZE 0x600000 |
| 39 | #define TFTF_NVM_OFFSET 0x20000000 |
| 40 | |
| 41 | /* total number of system nodes implemented by the platform */ |
| 42 | #define PLATFORM_SYSTEM_COUNT U(1) |
| 43 | |
| 44 | /* UG1085 - system interrupts table */ |
| 45 | #define PLAT_MAX_SPI_OFFSET_ID 229 |
| 46 | |
| 47 | /* Local state bit width for each level in the state-ID field of power state */ |
| 48 | #define PLAT_LOCAL_PSTATE_WIDTH 4 |
| 49 | |
| 50 | #define PLAT_MAX_PWR_STATES_PER_LVL 2 |
| 51 | |
| 52 | #define IRQ_PCPU_NS_TIMER 51 |
| 53 | |
| 54 | #define IRQ_CNTPSIRQ1 80 |
| 55 | |
| 56 | #define PLAT_SUSPEND_ENTRY_TIME 15 |
| 57 | #define PLAT_SUSPEND_ENTRY_EXIT_TIME 30 |
| 58 | |
| 59 | #define IRQ_PCPU_HP_TIMER 26 |
| 60 | |
| 61 | #define ZYNQMP_UART0_BASE 0xFF000000 |
| 62 | #define ZYNQMP_UART1_BASE 0xFF010000 |
| 63 | |
| 64 | #define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE |
| 65 | #define CRASH_CONSOLE_SIZE 0x1000 |
| 66 | |
| 67 | #define ZYNQMP_CRASH_UART_CLK_IN_HZ 100000000 |
| 68 | #define ZYNQMP_UART_BAUDRATE 115200 |
| 69 | |
| 70 | #define CACHE_WRITEBACK_SHIFT 6 |
| 71 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 72 | |
| Amit Nagal | 7c9f2fc | 2024-02-08 16:35:08 +0530 | [diff] [blame] | 73 | /* Platform specific page table and MMU setup constants */ |
| 74 | |
| 75 | #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) |
| 76 | #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) |
| 77 | |
| 78 | /* Translation table constants */ |
| 79 | #define MAX_XLAT_TABLES 8 |
| 80 | #define MAX_MMAP_REGIONS 16 |
| 81 | |
| 82 | /* ZYNQMP memory map related constants */ |
| 83 | |
| 84 | /* Aggregate of all devices in the first GB */ |
| 85 | #define DEVICE0_BASE U(0xFF000000) |
| 86 | #define DEVICE0_SIZE U(0x00E00000) |
| 87 | #define DEVICE1_BASE U(0xF9000000) |
| 88 | #define DEVICE1_SIZE U(0x00800000) |
| 89 | |
| 90 | /* GIC-400 & interrupt handling related constants */ |
| 91 | |
| 92 | #define GIC_BASE DEVICE1_BASE |
| 93 | #define GIC_SIZE 0x00080000 |
| 94 | #define BASE_GICD_BASE 0xF9010000 |
| 95 | #define BASE_GICC_BASE 0xF9020000 |
| 96 | #define BASE_GICH_BASE 0xF9040000 |
| 97 | #define BASE_GICV_BASE 0xF9060000 |
| 98 | |
| 99 | #define TTC_BASE U(0xff140000) |
| 100 | #define TTC_SIZE U(0x00010000) |
| 101 | |
| 102 | #define SYS_CNT_BASE1 TTC_BASE |
| 103 | #define SYS_CNT_SIZE TTC_SIZE |
| 104 | |
| 105 | /* timer */ |
| 106 | #define LPD_IOU_SLCR U(0xff180000) |
| 107 | #define LPD_IOU_SLCR_SIZE U(0x00010000) |
| 108 | #define TTC_TIMER_IRQ U(77) |
| 109 | #define TTC_CLK_SEL_OFFSET U(0x380) |
| 110 | #define IRQ_TWDOG_INTID TTC_TIMER_IRQ |
| 111 | #endif /* __PLATFORM_DEF_H__ */ |