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review.trustedfirmware.org / TF-A / tf-a-tests.git / 6d144db95cd1ee317bf66efade0fd5d4e0909c3c / . / include / drivers / arm / gic_v2v3_common.h
blob: 8182d5dd1b84c865c5609bda7eb14b994238a695 [file] [log] [blame]
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]1/*
Boyan Karatoteva4b33342025-06-19 16:24:29 +0100[diff] [blame]2 * Copyright (c) 2018-2025, Arm Limited. All rights reserved.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __GIC_COMMON_H__
8#define __GIC_COMMON_H__
9
Boyan Karatotev5f246842025-06-16 11:42:30 +0100[diff] [blame]10#include <stdbool.h>
11
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]12/***************************************************************************
13 * Defines and prototypes common to GIC v2 and v3 drivers.
14 **************************************************************************/
15/* Distributor interface register offsets */
16#define GICD_CTLR 0x0
17#define GICD_TYPER 0x4
18#define GICD_ISENABLER 0x100
19#define GICD_ICENABLER 0x180
20#define GICD_ISPENDR 0x200
21#define GICD_ICPENDR 0x280
22#define GICD_ISACTIVER 0x300
23#define GICD_ICACTIVER 0x380
24#define GICD_IPRIORITYR 0x400
25#define GICD_ICFGR 0xC00
26
27/* Distributor interface register shifts */
28#define ISENABLER_SHIFT 5
29#define ICENABLER_SHIFT ISENABLER_SHIFT
30#define ISPENDR_SHIFT 5
31#define ICPENDR_SHIFT ISPENDR_SHIFT
32#define ISACTIVER_SHIFT 5
33#define ICACTIVER_SHIFT ISACTIVER_SHIFT
34#define IPRIORITYR_SHIFT 2
35#define ICFGR_SHIFT 4
36
37/* GICD_TYPER bit definitions */
38#define IT_LINES_NO_MASK 0x1f
39
40/* GICD Priority register mask */
41#define GIC_PRI_MASK 0xff
42
43/*
44 * Number of per-cpu interrupts to save prior to system suspend.
45 * This comprises all SGIs and PPIs.
46 */
47#define NUM_PCPU_INTR 32
48
49#ifndef __ASSEMBLY__
50
51#include <mmio.h>
52
53/* Helper to detect the GIC mode (GICv2 or GICv3) configured in the system */
Boyan Karatotev5f246842025-06-16 11:42:30 +0100[diff] [blame]54bool is_gicv3_mode(void);
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]55
56/*******************************************************************************
57 * Private GIC Distributor function prototypes for use by GIC drivers
58 ******************************************************************************/
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]59unsigned int gicd_read_isenabler(uintptr_t base, unsigned int interrupt_id);
60unsigned int gicd_read_icenabler(uintptr_t base, unsigned int interrupt_id);
61unsigned int gicd_read_ispendr(uintptr_t base, unsigned int interrupt_id);
62unsigned int gicd_read_icpendr(uintptr_t base, unsigned int interrupt_id);
63unsigned int gicd_read_isactiver(uintptr_t base, unsigned int interrupt_id);
64unsigned int gicd_read_icactiver(uintptr_t base, unsigned int interrupt_id);
65unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int interrupt_id);
66unsigned int gicd_get_ipriorityr(uintptr_t base, unsigned int interrupt_id);
67unsigned int gicd_read_icfgr(uintptr_t base, unsigned int interrupt_id);
68void gicd_write_isenabler(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]69 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]70void gicd_write_icenabler(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]71 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]72void gicd_write_ispendr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]73 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]74void gicd_write_icpendr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]75 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]76void gicd_write_isactiver(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]77 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]78void gicd_write_icactiver(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]79 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]80void gicd_write_ipriorityr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]81 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]82void gicd_write_icfgr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]83 unsigned int val);
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]84unsigned int gicd_get_isenabler(uintptr_t base, unsigned int interrupt_id);
85void gicd_set_isenabler(uintptr_t base, unsigned int interrupt_id);
86void gicd_set_icenabler(uintptr_t base, unsigned int interrupt_id);
87void gicd_set_ispendr(uintptr_t base, unsigned int interrupt_id);
88void gicd_set_icpendr(uintptr_t base, unsigned int interrupt_id);
89void gicd_set_isactiver(uintptr_t base, unsigned int interrupt_id);
90void gicd_set_icactiver(uintptr_t base, unsigned int interrupt_id);
91void gicd_set_ipriorityr(uintptr_t base, unsigned int interrupt_id,
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]92 unsigned int priority);
93
Boyan Karatotev6d144db2025-06-23 15:04:53 +0100[diff] [blame^]94static inline unsigned int gicv2v3_get_sgi_num(unsigned int irq_num,
95 unsigned int core_pos)
96{
97 /* the SGI index is the INTID */
98 return irq_num;
99}
100
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]101/*******************************************************************************
102 * Private GIC Distributor interface accessors for reading and writing
103 * entire registers
104 ******************************************************************************/
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]105static inline unsigned int gicd_read_ctlr(uintptr_t base)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]106{
107 return mmio_read_32(base + GICD_CTLR);
108}
109
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]110static inline unsigned int gicd_read_typer(uintptr_t base)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]111{
112 return mmio_read_32(base + GICD_TYPER);
113}
114
Marek Bykowskid6514442019-12-17 07:41:43 -0600[diff] [blame]115static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]116{
117 mmio_write_32(base + GICD_CTLR, val);
118}
119
120
121#endif /*__ASSEMBLY__*/
122#endif /* __GIC_COMMON_H__ */