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review.trustedfirmware.org / TF-A / tf-a-tests.git / 2623513dbbbaee21ac309fb9f14eba748806fd47 / . / tftf / tests / plat / amd / common / common_files / xpm_defs.h
blob: 2e12d58f9cf8a97ec5d1309d7cbe33acacc190e2 [file] [log] [blame]
Madhav Bhatt00d869a2025-08-25 06:17:34 +0000[diff] [blame]1/*
2 * Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef XPM_DEFS_H_
8#define XPM_DEFS_H_
9
10#include <irq.h>
11#include <smccc.h>
12#include <tftf_lib.h>
13
14#define PM_SIP_SVC 0xC2000000U
15#define PAYLOAD_ARG_CNT 7U
Madhav Bhatt9743f7d2025-08-25 05:39:36 -0700[diff] [blame]16#define NOTIFIER_SGI 15U
Madhav Bhatted5bda82025-08-25 04:01:16 -0700[diff] [blame]17#define IRQ_PRIORITY 0U
Madhav Bhatt9743f7d2025-08-25 05:39:36 -0700[diff] [blame]18#define PM_MAX_QOS 100
Madhav Bhatt00d869a2025-08-25 06:17:34 +0000[diff] [blame]19
20#define upper_32_bits(n) ((uint32_t)(((n) >> 32U)))
21#define lower_32_bits(n) ((uint32_t)((n) & 0xffffffffU))
22
23#define VERSION_MAJOR(v) ((v) >> 16)
24#define VERSION_MINOR(v) ((v) & 0xFFFF)
25
26#define PM_RET_SUCCESS 0U
27#define PM_RET_ERROR_ARGS 1U
28#define PM_NO_ACCESS 2002L
29#define PM_ERR_VERSION 2014L
30
31/* TF-A only commands */
Madhav Bhatt6b1f4732025-08-25 22:12:44 -0700[diff] [blame]32#define TF_A_FEATURE_CHECK 0xa00U
Madhav Bhatt4cb875e2025-08-25 21:51:55 -0700[diff] [blame]33#define PM_GET_CALLBACK_DATA 0xa01U
34#define PM_GET_TRUSTZONE_VERSION 0xa03U
35#define TF_A_PM_REGISTER_SGI 0xa04U
Madhav Bhatt00d869a2025-08-25 06:17:34 +0000[diff] [blame]36
Madhav Bhatt7faf8ca2025-08-25 04:59:09 -0700[diff] [blame]37/* RPU operation mode */
38#define XPM_RPU_MODE_LOCKSTEP 0U
39#define XPM_RPU_MODE_SPLIT 1U
40
Madhav Bhatt9743f7d2025-08-25 05:39:36 -0700[diff] [blame]41/* Requirement limits */
42#define XPM_MAX_LATENCY 0xFFFFU
43
Madhav Bhattdb5542a2025-08-25 22:24:47 -0700[diff] [blame]44/* SGI number used for Event management driver */
45#define XLNX_EVENT_SGI_NUM (15)
46
Madhav Bhatt95229192025-08-25 23:29:29 -0700[diff] [blame]47/**
48 * System shutdown macros
49 */
50#define PM_SHUTDOWN_TYPE_SHUTDOWN (0U)
51#define PM_SHUTDOWN_TYPE_RESET (1U)
52
53#define PM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM (0U)
54#define PM_SHUTDOWN_SUBTYPE_RST_PS_ONLY (1U)
55#define PM_SHUTDOWN_SUBTYPE_RST_SYSTEM (2U)
56
Madhav Bhatt26235132025-08-26 00:23:47 -0700[diff] [blame^]57/**
58 * State arguments of the self suspend
59 */
60#define PM_SUSPEND_STATE_CPU_IDLE 0x0U
61#define PM_SUSPEND_STATE_CPU_OFF 0x1U
62#define PM_SUSPEND_STATE_SUSPEND_TO_RAM 0xFU
63
Madhav Bhatt00d869a2025-08-25 06:17:34 +0000[diff] [blame]64/* API IDs */
65enum pm_api_id {
66 PM_API_MIN, /**< 0x0 */
67 PM_GET_API_VERSION, /**< 0x1 */
68 PM_SET_CONFIGURATION, /**< 0x2 */
69 PM_GET_NODE_STATUS, /**< 0x3 */
70 PM_GET_OP_CHARACTERISTIC, /**< 0x4 */
71 PM_REGISTER_NOTIFIER, /**< 0x5 */
72 PM_REQUEST_SUSPEND, /**< 0x6 */
73 PM_SELF_SUSPEND, /**< 0x7 */
74 PM_FORCE_POWERDOWN, /**< 0x8 */
75 PM_ABORT_SUSPEND, /**< 0x9 */
76 PM_REQUEST_WAKEUP, /**< 0xA */
77 PM_SET_WAKEUP_SOURCE, /**< 0xB */
78 PM_SYSTEM_SHUTDOWN, /**< 0xC */
79 PM_REQUEST_NODE, /**< 0xD */
80 PM_RELEASE_NODE, /**< 0xE */
81 PM_SET_REQUIREMENT, /**< 0xF */
82 PM_SET_MAX_LATENCY, /**< 0x10 */
83 PM_RESET_ASSERT, /**< 0x11 */
84 PM_RESET_GET_STATUS, /**< 0x12 */
85 PM_MMIO_WRITE, /**< 0x13 */
86 PM_MMIO_READ, /**< 0x14 */
87 PM_INIT_FINALIZE, /**< 0x15 */
88 PM_FPGA_LOAD, /**< 0x16 */
89 PM_FPGA_GET_STATUS, /**< 0x17 */
90 PM_GET_CHIPID, /**< 0x18 */
91 PM_SECURE_RSA_AES, /**< 0x19 */
92 PM_SECURE_SHA, /**< 0x1A */
93 PM_SECURE_RSA, /**< 0x1B */
94 PM_PINCTRL_REQUEST, /**< 0x1C */
95 PM_PINCTRL_RELEASE, /**< 0x1D */
96 PM_PINCTRL_GET_FUNCTION, /**< 0x1E */
97 PM_PINCTRL_SET_FUNCTION, /**< 0x1F */
98 PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */
99 PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */
100 PM_IOCTL, /**< 0x22 */
101 PM_QUERY_DATA, /**< 0x23 */
102 PM_CLOCK_ENABLE, /**< 0x24 */
103 PM_CLOCK_DISABLE, /**< 0x25 */
104 PM_CLOCK_GETSTATE, /**< 0x26 */
105 PM_CLOCK_SETDIVIDER, /**< 0x27 */
106 PM_CLOCK_GETDIVIDER, /**< 0x28 */
107 PM_CLOCK_SETRATE, /**< 0x29 */
108 /* PM_CLOCK_GETRATE API is deprecated */
109 PM_RESERVE_ID, /**< 0x2A */
110 PM_CLOCK_SETPARENT, /**< 0x2B */
111 PM_CLOCK_GETPARENT, /**< 0x2C */
112 PM_SECURE_IMAGE, /**< 0x2D */
113 PM_FPGA_READ, /**< 0x2E */
114 PM_SECURE_AES, /**< 0x2F */
115 PM_PLL_SET_PARAMETER, /**< 0x30 */
116 PM_PLL_GET_PARAMETER, /**< 0x31 */
117 PM_PLL_SET_MODE, /**< 0x32 */
118 PM_PLL_GET_MODE, /**< 0x33 */
119 PM_REGISTER_ACCESS, /**< 0x34 */
120 PM_EFUSE_ACCESS, /**< 0x35 */
121 PM_ADD_SUBSYSTEM, /**< 0x36 */
122 PM_DESTROY_SUBSYSTEM, /**< 0x37 */
123 PM_DESCRIBE_NODES, /**< 0x38 */
124 PM_ADD_NODE, /**< 0x39 */
125 PM_ADD_NODE_PARENT, /**< 0x3A */
126 PM_ADD_NODE_NAME, /**< 0x3B */
127 PM_ADD_REQUIREMENT, /**< 0x3C */
128 PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */
129 PM_INIT_NODE, /**< 0x3E */
130 PM_FEATURE_CHECK, /**< 0x3F */
131 PM_ISO_CONTROL, /**< 0x40 */
132 PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */
133 PM_SET_NODE_ACCESS, /**< 0x42 */
134 PM_BISR, /**< 0x43 */
135 PM_APPLY_TRIM, /**< 0x44 */
136 PM_NOC_CLOCK_ENABLE, /**< 0x45 */
137 PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */
138 PM_FORCE_HOUSECLEAN, /**< 0x47 */
139 PM_FPGA_GET_VERSION, /**< 0x48 */
140 PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */
141 PM_HNICX_NPI_DATA_XFER, /**< 0x4A */
142 PM_API_MAX /**< 0x4B */
143};
144
Madhav Bhatt453f76f2025-08-25 06:50:50 -0700[diff] [blame]145/**
146 * Pin Function IDs
147 */
148enum pm_pin_fun_ids {
149 PIN_FUNC_SPI0, /**< Pin function ID of SPI0 */
150 PIN_FUNC_SPI0_SS, /**< Pin function ID of SPI0_SS */
151 PIN_FUNC_SPI1, /**< Pin function ID of SPI1 */
152 PIN_FUNC_SPI1_SS, /**< Pin function ID of SPI1_SS */
153 PIN_FUNC_CAN0, /**< Pin function ID of CAN0 */
154 PIN_FUNC_CAN1, /**< Pin function ID of CAN1 */
155 PIN_FUNC_I2C0, /**< Pin function ID of I2C0 */
156 PIN_FUNC_I2C1, /**< Pin function ID of I2C1 */
157 PIN_FUNC_I2C_PMC, /**< Pin function ID of I2C_PMC */
158 PIN_FUNC_TTC0_CLK, /**< Pin function ID of TTC0_CLK */
159 PIN_FUNC_TTC0_WAV, /**< Pin function ID of TTC0_WAV */
160 PIN_FUNC_TTC1_CLK, /**< Pin function ID of TTC1_CLK */
161 PIN_FUNC_TTC1_WAV, /**< Pin function ID of TTC1_WAV */
162 PIN_FUNC_TTC2_CLK, /**< Pin function ID of TTC2_CLK */
163 PIN_FUNC_TTC2_WAV, /**< Pin function ID of TTC2_WAV */
164 PIN_FUNC_TTC3_CLK, /**< Pin function ID of TTC3_CLK */
165 PIN_FUNC_TTC3_WAV, /**< Pin function ID of TTC3_WAV */
166 PIN_FUNC_WWDT0, /**< Pin function ID of WWDT0 */
167 PIN_FUNC_WWDT1, /**< Pin function ID of WWDT1 */
168 PIN_FUNC_SYSMON_I2C0, /**< Pin function ID of SYSMON_I2C0 */
169 PIN_FUNC_SYSMON_I2C0_ALERT, /**< Pin function ID of SYSMON_I2C0_AL */
170 PIN_FUNC_UART0, /**< Pin function ID of UART0 */
171 PIN_FUNC_UART0_CTRL, /**< Pin function ID of UART0_CTRL */
172 PIN_FUNC_UART1, /**< Pin function ID of UART1 */
173 PIN_FUNC_UART1_CTRL, /**< Pin function ID of UART1_CTRL */
174 PIN_FUNC_GPIO0, /**< Pin function ID of GPIO0 */
175 PIN_FUNC_GPIO1, /**< Pin function ID of GPIO1 */
176 PIN_FUNC_GPIO2, /**< Pin function ID of GPIO2 */
177 PIN_FUNC_EMIO0, /**< Pin function ID of EMIO0 */
178 PIN_FUNC_GEM0, /**< Pin function ID of GEM0 */
179 PIN_FUNC_GEM1, /**< Pin function ID of GEM1 */
180 PIN_FUNC_TRACE0, /**< Pin function ID of TRACE0 */
181 PIN_FUNC_TRACE0_CLK, /**< Pin function ID of TRACE0_CLK */
182 PIN_FUNC_MDIO0, /**< Pin function ID of MDIO0 */
183 PIN_FUNC_MDIO1, /**< Pin function ID of MDIO1 */
184 PIN_FUNC_GEM_TSU0, /**< Pin function ID of GEM_TSU0 */
185 PIN_FUNC_PCIE0, /**< Pin function ID of PCIE0 */
186 PIN_FUNC_SMAP0, /**< Pin function ID of SMAP0 */
187 PIN_FUNC_USB0, /**< Pin function ID of USB0 */
188 PIN_FUNC_SD0, /**< Pin function ID of SD0 */
189 PIN_FUNC_SD0_PC, /**< Pin function ID of SD0_PC */
190 PIN_FUNC_SD0_CD, /**< Pin function ID of SD0_CD */
191 PIN_FUNC_SD0_WP, /**< Pin function ID of SD0_WP */
192 PIN_FUNC_SD1, /**< Pin function ID of SD1 */
193 PIN_FUNC_SD1_PC, /**< Pin function ID of SD1_PC */
194 PIN_FUNC_SD1_CD, /**< Pin function ID of SD1_CD */
195 PIN_FUNC_SD1_WP, /**< Pin function ID of SD1_WP */
196 PIN_FUNC_OSPI0, /**< Pin function ID of OSPI0 */
197 PIN_FUNC_OSPI0_SS, /**< Pin function ID of OSPI0_SS */
198 PIN_FUNC_QSPI0, /**< Pin function ID of QSPI0 */
199 PIN_FUNC_QSPI0_FBCLK, /**< Pin function ID of QSPI0_FBCLK */
200 PIN_FUNC_QSPI0_SS, /**< Pin function ID of QSPI0_SS */
201 PIN_FUNC_TEST_CLK, /**< Pin function ID of TEST_CLK */
202 PIN_FUNC_TEST_SCAN, /**< Pin function ID of TEST_SCAN */
203 PIN_FUNC_TAMPER_TRIGGER, /**< Pin function ID of TAMPER_TRIGGER */
204 MAX_FUNCTION, /**< Max Pin function */
205};
206
Madhav Bhatted5bda82025-08-25 04:01:16 -0700[diff] [blame]207/* Node capabilities */
208#define PM_CAP_ACCESS 1U
209#define PM_CAP_CONTEXT 2U
210
211/*
212 * PM notify events
213 */
214enum xpm_notify_event {
215 EVENT_STATE_CHANGE = 1U, /**< State change event */
216 EVENT_ZERO_USERS = 2U, /**< Zero user event */
217 EVENT_CPU_IDLE_FORCE_PWRDWN = 4U, /**< CPU idle event during force pwr down */
218};
219
220/**
221 * PM API callback IDs
222 */
223enum pm_api_cb_id {
224 PM_INIT_SUSPEND_CB = 30U, /**< Suspend callback */
225 PM_ACKNOWLEDGE_CB = 31U, /**< Acknowledge callback */
226 PM_NOTIFY_CB = 32U, /**< Notify callback */
227};
228
Madhav Bhatt7faf8ca2025-08-25 04:59:09 -0700[diff] [blame]229/* IOCTL IDs */
230typedef enum {
231 IOCTL_GET_RPU_OPER_MODE = 0, /**< Get RPU mode */
232 IOCTL_SET_RPU_OPER_MODE = 1, /**< Set RPU mode */
233} pm_ioctl_id;
234
Madhav Bhatt453f76f2025-08-25 06:50:50 -0700[diff] [blame]235/*
236 * Reset configuration argument
237 */
238enum xpm_reset_actions {
239 PM_RESET_ACTION_RELEASE, /**< Reset action release */
240 PM_RESET_ACTION_ASSERT, /**< Reset action assert */
241 PM_RESET_ACTION_PULSE, /**< Reset action pulse */
242};
243
244/*
245 * Pin Control Configuration
246 */
247enum pm_pinctrl_config_param {
248 PINCTRL_CONFIG_SLEW_RATE, /**< Pin config slew rate */
249 PINCTRL_CONFIG_BIAS_STATUS, /**< Pin config bias status */
250 PINCTRL_CONFIG_PULL_CTRL, /**< Pin config pull control */
251 PINCTRL_CONFIG_SCHMITT_CMOS, /**< Pin config schmitt CMOS */
252 PINCTRL_CONFIG_DRIVE_STRENGTH, /**< Pin config drive strength */
253 PINCTRL_CONFIG_VOLTAGE_STATUS, /**< Pin config voltage status */
254 PINCTRL_CONFIG_TRI_STATE, /**< Pin config tri state */
255 PINCTRL_CONFIG_MAX, /**< Max Pin config */
256};
257
258/*
259 * Pin Control Slew Rate
260 */
261enum pm_pinctrl_slew_rate {
262 PINCTRL_SLEW_RATE_FAST, /**< Fast slew rate */
263 PINCTRL_SLEW_RATE_SLOW, /**< Slow slew rate */
264};
265
Madhav Bhatt05591742025-08-25 22:56:05 -0700[diff] [blame]266/**
267 * PM operating characteristic types
268 */
269enum xpm_opchar_type {
270 PM_OPCHAR_TYPE_POWER = 1, /**< Operating characteristic ID power */
271 PM_OPCHAR_TYPE_TEMP, /**< Operating characteristic ID temp */
272 PM_OPCHAR_TYPE_LATENCY, /**< Operating characteristic ID latency */
273};
274
Madhav Bhatt7fad2892025-08-25 23:51:41 -0700[diff] [blame]275/**
276 * PLL parameters
277 */
278enum xpm_pll_config_params {
279 PM_PLL_PARAM_ID_DIV2, /**< PLL param ID DIV2 */
280 PM_PLL_PARAM_ID_FBDIV, /**< PLL param ID FBDIV */
281 PM_PLL_PARAM_ID_DATA, /**< PLL param ID DATA */
282 PM_PLL_PARAM_ID_PRE_SRC, /**< PLL param ID PRE_SRC */
283 PM_PLL_PARAM_ID_POST_SRC, /**< PLL param ID POST_SRC */
284 PM_PLL_PARAM_ID_LOCK_DLY, /**< PLL param ID LOCK_DLY */
285 PM_PLL_PARAM_ID_LOCK_CNT, /**< PLL param ID LOCK_CNT */
286 PM_PLL_PARAM_ID_LFHF, /**< PLL param ID LFHF */
287 PM_PLL_PARAM_ID_CP, /**< PLL param ID CP */
288 PM_PLL_PARAM_ID_RES, /**< PLL param ID RES */
289 PM_PLL_PARAM_MAX, /**< PLL param ID max */
290};
291
292/**
293 * PLL modes
294 */
295enum xpm_pll_mode {
296 PM_PLL_MODE_INTEGER = (0U), /**< PLL mode integer */
297 PM_PLL_MODE_FRACTIONAL = (1U), /**< PLL mode fractional */
298 PM_PLL_MODE_RESET = (2U), /**< PLL mode reset */
299};
300
Madhav Bhatt00d869a2025-08-25 06:17:34 +0000[diff] [blame]301#endif /* XPM_DEFS_H_ */