| <?xml version="1.0" encoding="utf-8"?> |
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| <!-- |
| Copyright (c) 2024, Arm Limited. All rights reserved. |
| |
| SPDX-License-Identifier: BSD-3-Clause |
| --> |
| |
| <testsuites> |
| |
| <testsuite name="SIMD,SVE Registers context" |
| description="Validate context switch between NWd and SWd" > |
| <testcase name="Check that SIMD registers context is preserved" |
| function="test_simd_vectors_preserved" /> |
| <testcase name="Check that SVE registers context is preserved" |
| function="test_sve_vectors_preserved" /> |
| <testcase name="Check that SVE operations in NWd are unaffected by SWd" |
| function="test_sve_vectors_operations" /> |
| <testcase name="Enter SPMC with SME SSVE enabled" |
| function="test_sme_streaming_sve" /> |
| <testcase name="Enter SPMC with SME ZA enabled" |
| function="test_sme_za" /> |
| <testcase name="Enter SPMC with SME SM+ZA enabled" |
| function="test_sme_streaming_sve_za" /> |
| </testsuite> |
| |
| </testsuites> |